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a
15 V, I2C Compatible 256-Position Digital Potentiometers AD5280/AD5282*
FUNCTIONAL BLOCK DIAGRAMS
A W B O1 O2
FEATURES 256 Position AD5280: 1-Channel AD5282: 2-Channel (Independently Programmable) Potentiometer Replacement 20 k , 50 k , 200 k Low Temperature Coefficient 30 ppm/C Internal Power-On Midscale Preset 5 V to 15 V Single-Supply; 5.5 V Dual-Supply Operation I2C Compatible Interface APPLICATIONS Multimedia, Video, and Audio Communications Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage Source Programmable Current Source Line Impedance Matching GENERAL DESCRIPTION
SHDN
VDD RDAC REGISTER VSS VL ADDRESS DECODE 8 SCL SDA GND AD0 AD1 A2 W2 B2 O1 SERIAL INPUT REGISTER PWR ON RESET OUTPUT REGISTER
AD5280
A1 W1 B1
The AD5280/AD5282 provides a single-/dual-channel, 256-position digitally controlled variable resistor (VR) device.1 These devices perform the same electronic adjustment function as a potentiometer, trimmer, or variable resistor. Each VR offers a completely programmable value of resistance between the A terminal and the wiper or the B terminal and the wiper. The fixed A-to-B terminal resistance of 20 k, 50 k, or 200 k has a 1% channel-to-channel matching tolerance. Nominal temperature coefficient of both parts is 30 ppm/C. Another key feature of these parts is that they can operate up to +15 V or 5 V. Wiper position programming defaults to midscale at system power-on. Once powered, the VR wiper position is programmed by an I2C compatible 2-wire serial data interface. Both parts have additional programmable logic outputs that enable users to drive digital loads, logic gates, LED drivers, and analog switches in their system. The AD5280/AD5282 are available in thin surface-mount 14-lead and 16-lead TSSOP packages. All parts are guaranteed to operate over the extended industrial temperature range of -40C to +85C. For 3-wire SPI compatible interface applications, see AD5260/AD5262 products.
* Patent Pending. NOTE 1 The terms digital potentiometer, VR, and RDAC are used interchangeably.
SHDN
OUTPUT REGISTER
VDD VSS VL ADDRESS DECODE 8 SCL SDA GND AD0 AD1 SERIAL INPUT REGISTER PWR ON RESET RDAC1 REGISTER RDAC2 REGISTER
AD5282
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
AD5280/AD5282-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS 20 k , 50 k , 200 k
Parameter Symbol Conditions
(VDD = +15 V, VSS = 0 V or VDD = +5 V, VSS = -5 V; VLOGIC = 5 V, VA = +VDD, VB = 0 V; -40 C < TA < +85 C, unless otherwise noted.)
Min -1 -1 -30 Typ1 1/4 1/4 30 60 Max +1 +1 +30 150 Unit LSB LSB % ppm/C Bits LSB LSB ppm/C LSB LSB V pF pF nA A V V V V V V A pF V V V A A A mW %/% kHz kHz kHz % s nV-s
VERSION
DC CHARACTERISTICS-RHEOSTAT MODE Specifications apply to all VRs R-DNL RWB, VA = NC Resistor Differential NL2 R-INL RWB, VA = NC Resistor Nonlinearity2 Nominal Resistor Tolerance3 RAB TA = 25C VAB = VDD, Wiper = No Connect Resistance Temperature Coefficient RAB/ T IW = VDD /R, VDD = 3 V or 5 V Wiper Resistance RW
DC CHARACTERISTICS-POTENTIOMETER DIVIDER MODE Specifications apply to all VRs Resolution N 8 Integral Nonlinearity4 INL -1 DNL -1 Differential Nonlinearity4 Voltage Divider Temperature VW / T Code = 80H Coefficient Code = FFH -2 Full-Scale Error VWFSE Zero-Scale Error VWZSE Code = 00H 0 RESISTOR TERMINALS Voltage Range5 Capacitance6 A, B Capacitance6 W Common-Mode Leakage Shutdown Current DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Output Logic High (SDO) Output Logic Low (SDO) Input Current Input Capacitance6 POWER SUPPLIES Logic Supply Power Single-Supply Range Power Dual-Supply Range Logic Supply Current Positive Supply Current Negative Supply Current Power Dissipation7 Power Supply Sensitivity VA,B,W CA,B CW ICM ISHDN VIH VIL VIH VIL VIH VIL IIL CIL VLOGIC VDD RANGE VDD/SS RANGE ILOGIC IDD ISS PDISS PSS RAB = 20 k, Code = 80H RAB = 50 k, Code = 80H RAB = 200 k, Code = 80H VA = 1 V rms, RAB = 20 k VB = 0 V DC, f = 1 kHz VA = 5 V, VB = 5 V, 1 LSB error band VA = VDD, VB = 0 V, Measure VW1 with Adjacent RDAC Making Full-Scale Code Change Measure VW1 with VW2 = 5 V p-p @ f = 10 kHz RWB = 20 k, f = 1 kHz -2- VSS f = 5 MHz, measured to GND, Code = 80H f = 1 MHz, measured to GND, Code = 80H VA = VB = VW
1/4 1/4 5 -1 +1
+1 +1
0 +2 VDD
25 55 1 5 2.4 0.8
VLOGIC = 3 V, VSS = 0 VLOGIC = 3 V, VSS = 0 VIN = 0 V or 5 V
2.1 0.6 4.9 0.4 1 5 2.7 5 4.5 0.1 0.1 0.2 0.002 310 150 35 0.014 5 15 5.5 15 5.5 60 1 1 0.3 0.01
VSS = 0 V VLOGIC = 5 V VIH = 5 V or VIL = 0 V VIH = 5 V or VIL = 0 V, VDD = +5 V, VSS = -5 V
DYNAMIC CHARACTERISTICS6, 8, 9 Bandwidth -3 dB BW_20K BW_50K BW_200K Total Harmonic Distortion THDW VW Settling Time Crosstalk tS CT
Analog Crosstalk Resistor Noise Voltage
CTA eN_WB
-62 18
dB nV/Hz REV. 0
AD5280/AD5282
Parameter Symbol Conditions
6, 10
Min
Typ1
Max 400
Unit kHz s s s s s s ns ns ns s
INTERFACE TIMING CHARACTERISTICS Applies to all parts SCL Clock Frequency fSCL tBUF Bus Free Time between STOP and START t1 t2 After this period, the first tHD:STA Hold Time (Repeated START) clock pulse is generated t3 tLOW Low Period of SCL Clock t4 tHIGH High Period of SCL Clock tSU:STA Setup Time for START Condition t5 t6 tHD:DAT Data Hold Time t7 tSU:DAT Data Setup Time tF Fall Time of Both SDA and SCL Signals t8 t9 tR Rise Time of Both SDA and SCL Signals tSU:STO Setup Time for STOP Condition t10
1.3 0.6 1.3 0.6 0.6 100 300 300 0.6
50 0.9
NOTES 1 Typicals represent average readings at 25C, VDD = +5 V, VSS = -5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VAB = VDD, Wiper (VW) = No connect. 4 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 PDISS is calculated from (I DD VDD). CMOS logic level inputs result in minimum power dissipation. 8 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 9 All dynamic characteristics use V DD = 5 V. 10 See timing diagram for location of measured values. Specifications subject to change without notice.
REV. 0
-3-
AD5280/AD5282
ABSOLUTE MAXIMUM RATINGS 1 (TA = 25C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +15 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, -7 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD AX - BX, AX - WX, BX - WX Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA VLOGIC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, 7 V Output Voltage to GND . . . . . . . . . . . . . . . . . . . . . . 0 V, 7 V Operating Temperature Range . . . . . . . . . . . -40C to +85C Thermal Resistance3 JA, TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206C/W TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C/W
Maximum Junction Temperature (TJ MAX) . . . . . . . . . 150C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature RU-14, RU-16 (Vapor Phase, 60 sec) . . . . . . . . . . . . 215C RU-14, RU-16 (Infrared, 15 sec) . . . . . . . . . . . . . . . . 220C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Maximum terminal current is bound by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 3 Package Power Dissipation (T J MAX - T A)/ JA
ORDERING GUIDE
Model AD5280BRU20 AD5280BRU20-REEL7 AD5280BRU50 AD5280BRU50-REEL7 AD5280BRU200 AD5280BRU200-REEL7 AD5282BRU20 AD5282BRU20-REEL7 AD5282BRU50 AD5282BRU50-REEL7 AD5282BRU200 AD5282BRU200-REEL7
Number of Channels 1 1 1 1 1 1 2 2 2 2 2 2
RAB (k ) 20 20 50 50 200 200 20 20 50 50 200 200
Temp -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description TSSOP-14 TSSOP-14 TSSOP-14 TSSOP-14 TSSOP-14 TSSOP-14 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16
Package Option RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16
Parts Per Container 96 1000 96 1000 96 1000 96 1000 96 1000 96 1000
Branding Information* AD5280B20 AD5280B20 AD5280B50 AD5280B50 AD5280B200 AD5280B200 AD5282B20 AD5282B20 AD5282B50 AD5282B50 AD5282B200 AD5282B200
The AD5280/AD5282 die size is 75 mm 120 mm, 9,000 sq. mm. Contains 3077 transistors. *Line 1 contains model number, Line 2 contains ADI logo followed by the end-to-end resistance value, and line 3 contains date code YYWW.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5280/AD5282 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. 0
AD5280/AD5282
PIN CONFIGURATION AD5280 PIN CONFIGURATION
A1 W2 B3 VDD 4
14 O1 13 VL
AD5282 PIN CONFIGURATION
O1 1 A1 2 W1 3 B1 4
16 A2 15 W2 14 B2
AD5280
12 O2
TOP VIEW 11 VSS (Not to Scale) 10 GND SHDN 5 SCL 6 SDA 7
9 8
13 VL TOP VIEW VDD 5 (Not to Scale) 12 VSS
AD5282
AD1 AD0
SHDN 6 SCL 7 SDA 8
11 GND 10 AD1 9
AD0
AD5280 PIN FUNCTION DESCRIPTION
AD5282 PIN FUNCTION DESCRIPTION
Pin Mnemonic Description 1 2 3 4 5 A W B VDD SHDN Resistor Terminal A Wiper Terminal W Resistor Terminal B Positive Power Supply. Specified for operation from 5 V to 15 V (Sum of |VDD| + |VSS| 15 V). Active Low, Asynchronous Connection of the Wiper W to Terminal B and Open Circuit of Terminal A. RDAC Register contents unchanged. SHDN should tie to VL if not used. Serial Clock Input Serial Data Input/Output Programmable Address Bit 0 for Multiple Package Decoding. Bits AD0 and AD1 provide four possible addresses. Programmable Address Bit 1 for Multiple Package Decoding. Bits AD0 and AD1 provide four possible addresses. Common Ground Negative Power Supply. Specified for operation from 0 V to -5 V (Sum of |VDD| + |VSS| 15 V). Logic Output Terminal O2 Logic Supply Voltage. Needs to be the same voltage as the digital logic controlling the AD5280. Logic Output Terminal O1
Pin Mnemonic Description 1 2 3 4 5 6 O1 A1 W1 B1 VDD SHDN Logic Output Terminal O1 Resistor Terminal A1 Wiper Terminal W1 Resistor Terminal B1 Positive Power Supply. Specified for operation from 5 V to 15 V (Sum of |VDD| + |VSS| 15 V). Active Low, Asynchronous Connection of the Wiper W to Terminal B and Open Circuit of Terminal A. RDAC Register contents unchanged. SHDN should tie to VL if not used. Serial Clock Input Serial Data Input/Output Programmable Address Bit 0 for Multiple Package Decoding. Bits AD0 and AD1 provide four possible addresses. Programmable Address Bit 1 for Multiple Package Decoding. Bits AD0 and AD1 provide four possible addresses. Common Ground Negative Power Supply. Specified for operation from 0 V to -5 V (Sum of |VDD| + |VSS| 15 V). Logic Supply Voltage. Needs to be the same voltage as the digital logic controlling the AD5282. Resistor Terminal B2 Wiper Terminal W2 Resistor Terminal A2
6 7 8
SCL SDA AD0
7 8 9
SCL SDA AD0
9
AD1
10
AD1
10 11 12 13
GND VSS O2 VL O1
11 12 13
GND VSS VL B2 W2 A2
14
14 15 16
REV. 0
-5-
AD5280/AD5282-Typical Performance Characteristics
1 0.8 POTENTIOMETER MODE INL - LSB RAB = 20k TA = 25 C 0.5 0.4 RAB = 20k TA = 25 C 5V +15V 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 32 64 96 128 160 192 224 256 TA = -40 C TA = +25 C TA = +85 C TA = +125 C RAB = 20k
RHEOSTAT MODE DNL - LSB
RHEOSTAT MODE INL - LSB
0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 32 64 96 128 160 192 224 256 5V +15V +5V
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.8 -0.5 0 32 64 96 128 160 192 224 256 +5V
CODE - Decimal
CODE - Decimal
CODE - Decimal
TPC 1. R-INL vs. Code vs. Supply Voltages
TPC 2. R-DNL vs. Code vs. Supply Voltages
TPC 3. INL vs. Code, VDD/VSS = 5 V
0.5 POTENTIOMETER MODE DNL - LSB
1 POTENTIOMETER MODE DNL - LSB
0.5 RAB = 20k TA = 25 C 5V +5V +15V 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 32 64 96 5V +5V
POTENTIOMETER MODE INL - LSB
0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 TA = -40 C TA = +125 C
RAB = 20k
0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 32 64 96
RAB = 20k TA = 25 C
TA = +85 C
+15V
TA = +25 C 0 32 64 96 128 160 192 224 256 CODE - Decimal
128 160 192 224 256
128 160 192 224 256
CODE - Decimal
CODE - Decimal
TPC 4. DNL vs. Code, VDD/VSS = 5 V
TPC 5. INL vs. Code vs. Supply Voltages
TPC 6. DNL vs. Code vs. Supply Voltages
1.0 Avg + 3 0.5 Avg
RINL - LSB INL - LSB
2.0 RAB = 20k TA = 25 C 1.5 Avg + 3 1.0 Avg 0.5 Avg - 3 0 -0.5 -1.0 RAB = 20k TA = 25 C
0 -0.2
FULL-SCALE ERROR - LSB
RAB = 20k
-0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 VDD/V SS = 5V/0V VDD/V SS = 5V VDD/V SS = 15V/0V
Avg - 3 0
-0.5 -1.5 -1.0 0 5 10 |VDD - V SS| - V 15 20 -2.0 0 5 10 |VDD - V SS| - V 15 20
-2.0 -40
-20
40 60 0 20 TEMPERATURE - C
80
100
TPC 7. INL Over Supply Voltage
TPC 8. RINL Over Supply Voltage
TPC 9. Full-Scale Error
-6-
REV. 0
AD5280/AD5282
2.0 1.8
ZERO-SCALE ERROR - LSB
1000 RAB = 20k
IDD/I SS SUPPLY CURRENT - nA
RAB = 20k
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -40 -20 40 60 0 20 TEMPERATURE - C 80 100 VDD/V SS = 5V VDD/V SS = 15V/0V VDD/V SS = 5V/0V
VLOGIC = 5V VIH = 5V VIL = 0V
26.0 RAB = 20k 25.5
VDD/V SS = 15V/0V
100
ISS @ V DD/V SS = 15V/0V
IDD @ V DD/V SS =
5V
ILOGIC - A
ISS @ V DD/V SS =
5V
25.0
24.5 VDD/V SS = 24.0 5V
10
23.5
1 -40
-7
26 59 92 TEMPERATURE - C
125
23.0 -40
-7
26 59 92 TEMPERATURE - C
125
TPC 10. Zero-Scale Error
TPC 11. Supply Current vs. Temperature
TPC 12. VLOGIC Supply Current vs. Temperature
RHEOSTAT MODE TEMPCO - ppm/ C
RAB = 20k TA = 25 C
600 500 400 300 200 100 0 -100 20k 50k 200k
TA = 25 C
POTENTIOMETER MODE TEMPCO - ppm/ C
1000
700
120 TA = 25 C 100 80 60 40 20 0 -20 -40 20k 50k 200k
VDD/V SS = 5V/0V VLOGIC = 5V 100
ILOGIC -
A
VDD/V SS = 5V/0V VLOGIC = 3V 10 0 1 2 VIH - V 3 4 5
-200
0
32
64
128 192 96 CODE - Decimal
224
256
128 192 96 CODE - Decimal
0
32
64
224
256
TPC 13. VLOGIC Supply Current vs. Digital Input Voltage
TPC 14. Rheostat Mode Tempco RWB/ T vs. Code, VDD/VSS = 5 V
TPC 15. Potentiometer Mode Tempco VWB/ T vs. Code, VDD/VSS = 5 V
-6 -12 -18 GAIN - dB -24 -30 -36 -42 -48 -54 -60 1k
0
0
80H 40H 20H
GAIN - dB
-6 -12 -18 -24 -30 -36 -42
0
80H 40H 20H
GAIN - dB
-6 -12 -18 -24 -30 -36 -42
80H 40H 20H 10H 08H 04H 02H 01H TA = 25 C VA = 50mV rms VDD/V SS = 5V 10k FREQUENCY - Hz 100k
10H 08H 04H 02H 01H TA = 25 C VA = 50mV rms VDD/V SS = 5V 10k 100k 1M FREQUENCY - Hz
10H 08H 04H 02H 01H TA = 25 C VA = 50mV rms VDD/V SS = 5V 10k 100k 1M FREQUENCY - Hz
-48 -54 -60 1k
-48 -54 -60 1k
TPC 16. Gain vs. Frequency vs. Code, RAB = 20 k
TPC 17. Gain vs. Frequency vs. Code, RAB = 50 k
TPC 18. Gain vs. Frequency vs. Code, RAB = 200 k
REV. 0
-7-
AD5280/AD5282
-6 -12 -18
R = 50k 150kHz
NOMALIZED GAIN FLATNESS - 0.1dB/DIV
0
R = 20k 310kHz
-6dB
TA = 25 C VDD/V SS =
500
5V
400
VDD/V SS = TA = 25 C
5V
R = 20k
GAIN - dB
-24 -30 -36 -42 -48 -54 -60 1k 10k TA = 25 C VDD/V SS = 5V VA = 50mV rms 100k 1M FREQUENCY - Hz
ILOGIC - A
R = 200k 35kHz
R= 50k
300 CODE = 55H 200
R = 200k
100 CODE = FFH
100
1k
10k
100k
0 10000
FREQUENCY - Hz
100000 1000000 FREQUENCY - Hz
10000000
TPC 19. -3 dB Bandwidth
TPC 20. Normalized Gain Flatness vs. Frequency
TPC 21. VLOGIC Supply Current vs. Frequency
80
CODE = 80H, VA = V DD, VB = 0V -PSRR @ V DD/V SS = DC 10% p-p AC 5V
A2
1.2V
852.0 s
60
PSRR - -dB
40
20
+PSRR @ V DD/V SS = DC 10% p-p AC
5V
2.04 s
0 100
1000
10000
100000
1000000
FREQUENCY - MHz
TPC 22. PSRR vs. Frequency
TPC 23. Midscale Glitch Energy Code 80H to 7FH
100
TPC 24. Large Signal Settling Time
40
VA = VB = OPEN TA = 25 C
A2
1.0V
33.41 s
CODES SET TO MIDSCALE
3 LOTS SAMPLE SIZE = 135
THEORETICAL IWB_MAX - mA
1 RAB = 20k RAB = 50k 0.1 RAB = 200k
FREQUENCY - MHz
256
10
30
20
10
1.50 s
0.01
0
32
64
96 128 192 CODE - Decimal
224
TPC 25. Digital Feedthrough vs. Time
TPC 26. IMAX vs. Code
TPC 27. Channel-to-Channel Resistance Matching (AD5282)
-8-
-0.5 -0.45 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2
0
LONG TERM CHANNEL-TO-CHANNEL RAB MATCH - %
REV. 0
AD5280/AD5282
TEST CIRCUITS
Test Circuits 1 to 11 define the test conditions used in the product specification table.
A
DUT A V B W VMS V+ = VDD 1LSB = V+/2N
+15V W VIN OFFSET GND 2.5V DUT AD8610 B -15V VOUT
Test Circuit 1. Potentiometer Divider Nonlinearity Error (INL, DNL)
NO CONNECT DUT A B VMS IW W
Test Circuit 7. Gain vs. Frequency
0.1V ISW
H
DUT W B ISW
RSW =
CODE =
0.1V
VSS TO VDD
Test Circuit 2. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
DUT A VMS2 B VMS1 RW = [VMS1 - VMS2]/I W W VW I W = VDD /R NOMINAL
Test Circuit 8. Incremental On Resistance
NC ICM
VDD DUT VSS GND
A B
W
VCM NC = NO CONNECT
NC
Test Circuit 3. Wiper Resistance
VA V+ = VDD 10% VDD V+ B PSRR (dB) = 20 LOG A W PSS (%/%) = VMS VMS% VDD%
Test Circuit 9. Common-Mode Leakage Current
VLOGIC ILOGIC
(
VMS VDD
)
SCL
SDA DIGITAL INPUT VOLTAGE
Test Circuit 4. Power Supply Sensitivity (PSS, PSSR)
A VIN OFFSET GND DUT B 5V W OP279 OFFSET BIAS VOUT
Test Circuit 10. VLOGIC Current vs. Digital Input Voltage
A1 VIN RDAC1 W1 N/C B1 VSS VDD A2 RDAC2 W2 B2 VOUT
Test Circuit 5. Inverting Gain
CTA = 20 log [VOUT/V IN]
5V
OP279 VIN OFFSET GND W A DUT B
VOUT
Test Circuit 11. Analog Crosstalk (AD5282 Only)
OFFSET BIAS
Test Circuit 6. Noninverting Gain
REV. 0
-9-
AD5280/AD5282
t8 SDA t1 t8 SCL t2
P S
t9
t6
t4 t3
t7
S
t5
P
t 10
Figure 1. Detailed Timing Diagram
Data of AD5280/AD5282 is accepted from the I2C bus in the following serial format: S 0 1 0 1 1 AD1 AD0 R/W A A/B RS SD O1 O2 X X Slave Address Byte Instruction Byte XA D7 D6 D5 D4 D3 D2 D1 D0 A Data Byte P
Where: S = Start Condition P = Stop Condition A = Acknowledge A = No Acknowledge X = Don't Care AD1, AD0 = Package Pin Programmable Address Bits R/W = Read Enable at High and Write Enable at Low
A/B = RDAC Subaddress Select. "Zero" for RDAC1 and "One" for RDAC2 RS = Midscale Reset, Active High (only affects selected channel) SD = Shutdown. Same as SHDN pin operation except inverse logic (only affects selected channel) O2, O1 = Output Logic Pin Latched Values, Default Logic 0 D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits
1
9
1
9
1
9
SCL SDA
0 1 0 1 1 AD1 AD0 R/W A/B RS SD O1 O2 X X X D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY AD5280/AD5282 START BY MASTER FRAME 1 SLAVE ADDRESS BYTE FRAME 2 INSTRUCTION BYTE
ACK. BY AD5280/AD5282 FRAME 3 DATA BYTE
ACK. BY AD5280/AD5282 STOP BY MASTER
Figure 2. Writing to the RDAC Register
1 9 1 9
SCL SDA
0 1 0 1 1 AD1 AD0 R/W D7 D6 D5 D4 D3 D2 D1 D0 A
ACK. BY AD5280/AD5282 START BY MASTER FRAME 1 SLAVE ADDRESS BYTE
NO ACK. BY MASTER STOP BY FRAME 2 MASTER DATA BYTE FROM PREVIOUSLY SELECTED RDAC REGISTER IN WRITE MODE
Figure 3. Reading Data from a Previously Selected RDAC Register in Write Mode
-10-
REV. 0
AD5280/AD5282
OPERATION
The AD5280/AD5282 provides a single-/dual-channel, 256position, digitally controlled variable resistor (VR) device. To program the VR settings, refer to the Digital Interface section. Both parts have an internal power-on preset that places the wiper at midscale during power-on, which simplifies the fault condition recovery at power-up. Operation of the power-on preset function also depends on the state of the VL pin. In addition, the shutdown SHDN pin of the AD5280/AD5282 places the RDAC in an almost zero power consumption state where terminal A is open circuited and the wiper W is connected to terminal B, resulting in only leakage currents being consumed in the VR structure. During shutdown, the VR latch settings are maintained or new settings can be programmed. When the part is returned from shutdown, the corresponding VR setting will be applied to the RDAC.
Ax SHDN
string will not be accessed; therefore, there is 1 LSB less of the nominal resistance at full scale in addition to the wiper resistance. The general equation determining the digitally programmed output resistance between W and B is: RWB (D) = D x RAB + RW 256 (1)
where: D is the decimal equivalent of the binary code loaded in the 8-bit RDAC Register. RAB is the nominal end-to-end resistance. RW is the wiper resistance contributed by the on resistance of the internal switch. Again, if RAB = 20 k and the A terminal is open circuited, the following output resistance values, RWB, will be set for the following RDAC latch codes.
Table I. Codes and Corresponding Resistances
RS D7 D6 D5 D4 D3 D2 D1 D0
D (DEC) 255 128 1 0
RWB ( ) 19982 10060 138 60
Output State Full Scale (RAB - 1 LSB + RW) Midscale 1 LSB Zero-Scale (Wiper Contact Resistance)
RS RS Wx
Note that in the zero-scale condition, a finite wiper resistance of 60 is present. Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur.
RDAC LATCH AND DECODER
RS Bx
Figure 4. AD5280/AD5282 Equivalent RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation
Similar to the mechanical potentiometer, the resistance of the RDAC between the wiper W and terminal A also produces a digitally controlled complementary resistance, RWA. When these terminals are used, the B terminal can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is: 256 - D x RAB + RW (2) 256 For RAB = 20 k and B terminal open circuited, the following output resistance, RWA, will be set for the following RDAC latch codes. RWA (D) =
Table II. Codes and Corresponding Resistances
The nominal resistance of the RDAC between terminals A and B is available in 20 k, 50 k, and 200 k. The final two or three digits of the part number determine the nominal resistance value, e.g., 20 k = 20; 50 k = 50; 200 k = 200. The nominal resistance (RAB) of the VR has 256 contact points accessed by the wiper terminal, plus the B terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings. Assuming a 20 k part is used, the wiper's first connection starts at the B terminal for data 00H. Since there is a 60 wiper contact resistance, such a connection yields a minimum of 60 resistance between terminals W and B. The second connection is the first tap point that corresponds to 138 (RWB = RAB/256 + RW = 78 + 60 ) for data 01H. The third connection is the next tap point representing 216 (78 2 + 60) for data 02H, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 19982 [RAB - 1 LSB + RW]. Figure 4 shows a simplified diagram of the equivalent RDAC circuit where the last resistor
D (DEC) 255 128 1 0
RWA ( ) 138 10060 19982 20060
Output State Full Scale Midscale 1 LSB Zero Scale
The typical distribution of the nominal resistance, RAB, from channel-to-channel matches within 1%. Device-to-device matching is process lot dependent and is possible to have 30% variation. Since the resistance element is processed in thin film technology, the change in RAB with temperature has a very low 30 ppm/C temperature coefficient.
REV. 0
-11-
AD5280/AD5282
PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation
The digital potentiometer easily generates a voltage divider at wiper-to-B and wiper-to-A to be proportional to the input voltage at A-to-B. Unlike the polarity of VDD-VSS, which must be positive, voltage across A-B, W-A, and W-B can be at either polarity provided that VSS is powered by a negative supply. If ignoring the effect of the wiper resistance for approximation, connecting A terminal to 5 V and B terminal to ground produces an output voltage at the wiper-to-B starting at 0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across A-B divided by the 256 positions of the potentiometer divider. Since AD5280/AD5282 can be supplied by dual supplies, the general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to terminals A and B is: VW (D ) = D 256 - D V+ VB 256 A 256 (3)
Byte labeled A/B is the RDAC subaddress select. A "low" selects RDAC1 and a "high" selects RDAC2 for the dualchannel AD5282. Set A/B to low for the AD5280. The second MSB, RS, is the midscale reset. A logic high on this bit moves the wiper of a selected channel to the center tap where RWA = RWB. This feature effectively writes over the contents of the register, and thus when taken out of reset mode, the RDAC will remain at midscale. The third MSB SD is a shutdown bit. A logic high causes the selected channel to open circuit at terminal A while shorting the wiper to terminal B. This operation yields almost 0 in Rheostat Mode or 0 V in Potentiometer Mode. This SD bit serves the same function as the SHDN pin except that the SHDN pin reacts to active low. Also, the SHDN pin affects both channels (AD5282) as opposed to the SD bit, which only affects the channel that is being written to. It is important to note that the shutdown operation does not disturb the contents of the register. When brought out of shutdown, the previous setting will be applied to the RDAC. The following two bits are O1 and O2. They are extra programmable logic outputs that can be used to drive other digital loads, logic gates, LED drivers, analog switches, and so on. The three LSBs are Don't Care (see Figure 2). 3. After acknowledging the Instruction Byte, the last byte in Write Mode is the Data Byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an Acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 2). 4. In the Read Mode, the Data Byte follows immediately after the acknowledgment of the Slave Address Byte. Data is transmitted over the serial bus in sequences of nine clock pulses (a slight difference with the Write Mode, where there are eight data bits followed by an Acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 3). 5. When all data bits have been read or written, a Stop condition is established by the master. A Stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In Write Mode, the master will pull the SDA line high during the tenth clock pulse to establish a Stop condition, (see Figure 2). In Read Mode, the master will issue a No Acknowledge for the ninth clock pulse (i.e., the SDA line remains high). The master will then bring the SDA line low before the tenth clock pulse, which goes high to establish a Stop condition (see Figure 3). A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing and instructing the part only once. During the write cycle, each data byte will update the RDAC output. For example, after the RDAC has acknowledged its slave address and instruction bytes, the RDAC output will update after these two bytes. If another byte is written to the RDAC while it is still addressed to a specific slave device with the same instruction, this byte will update the output of the selected slave device. If different instructions are needed, the Write Mode has to start with a new Slave Address, Instruction, and Data Byte again. Similarly, a repeated read function of the RDAC is also allowed. REV. 0
For a more accurate calculation, which includes the effect of wiper resistance, VW can be found as:
VW (D ) =
RWB (D ) RWA (D ) VA + VB R AB R AB
(4)
Operation of the digital potentiometer in the Divider Mode results in a more accurate operation overtemperature. Unlike the Rheostat Mode, the output voltage is dependent mainly on the ratio of the internal resistors RWA and RWB and not on the absolute values; therefore, the temperature drift reduces to 5 ppm/C.
DIGITAL INTERFACE 2-Wire Serial Bus
The AD5280/AD5282 are controlled via an I2C compatible serial bus. The RDACs are connected to this bus as slave devices. Referring to Figures 2 and 3, the first byte of AD5280/AD5282 is a Slave Address Byte. It has a 7-bit slave address and an R/W bit. The 5 MSBs are 01011 and the following two bits are determined by the state of the AD0 and AD1 pins of the device. AD0 and AD1 allow the user to place up to four of the I2C compatible devices on one bus. The 2-wire I2C serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, which is when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 2). The following byte is the Slave Address Byte which consists of the 7-bit slave address followed by an R/W bit (this bit determines whether data will be read from or written to the slave device). The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is termed the Acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master will read from the slave device. On the other hand, if the R/W bit is low, the master will write to the slave device. 2. A write operation contains an extra Instruction Byte more than a read operation. Such an Instruction Byte in Write Mode follows the Slave Address Byte. The MSB of the Instruction
-12-
AD5280/AD5282
READBACK RDAC VALUE MULTIPLE DEVICES ON ONE BUS
AD5280/AD5282 allows the user to read back the RDAC values in the Read Mode. However, for the AD5282 dual-channel device, the channel of interest is the one that is previously selected in the Write Mode. In the case where users need to read the RDAC values of both channels in AD5282, they can program the first subaddress in Write Mode and then change to Read Mode to read the first channel value. After that, they can change back to Write Mode with the second subaddress and finally read the second channel value in Read Mode again. Note that it is not necessary for users to issue the Frame 3 data byte in Write Mode for subsequent readback operation. Users should refer to Figures 2 and 3 for the programming format.
ADDITIONAL PROGRAMMABLE LOGIC OUTPUT
Figure 6 shows four AD5282 devices on the same serial bus. Each has a different slave address since the states of their AD0 and AD1 pins are different. This allows each RDAC within each device to be written to or read from independently. The master device output bus line drivers are open-drain pull-downs in a fully I2C compatible interface.
5V RP MASTER SDA SCL AD1 AD0 5V SDA SCL AD1 AD0 5V SDA SCL AD1 AD0 5V SDA SCL AD1 AD0 RP SDA SCL
AD5280/AD5282 features additional programmable logic outputs, O1 and O2, which can be used to drive a digital load, analog switches, and logic gates. O1 and O2 default to Logic 0. The logic states of O1 and O2 can be programmed in Frame 2 under the Write Mode (see Figure 2). These logic outputs have adequate current driving capability to sink/source milliamperes of load. Users can also activate O1 and O2 in three different ways without affecting the wiper settings. They may do the following: 1. Start, Slave Address Byte, Acknowledge, Instruction Byte with O1 and O2 specified, Acknowledge, Stop. 2. Complete the write cycle with Stop, then Start, Slave Address Byte, Acknowledge, Instruction Byte with O1 and O2 specified, Acknowledge, Stop. 3. Do not complete the write cycle by not issuing the Stop, then Start, Slave Address Byte, Acknowledge, Instruction Byte with O1 and O2 specified, Acknowledge, Stop.
SELF-CONTAINED SHUTDOWN FUNCTION
AD5282
AD5282
AD5282
AD5282
Figure 6. Multiple AD5282 Devices on One Bus
LEVEL SHIFT FOR BIDIRECTIONAL INTERFACE
While most old systems may be operated at one voltage, a new component may be optimized at another. When two systems operate the same signal at two different voltages, proper level shifting is needed. For instance, one can use a 3.3 V E2PROM to interface with a 5 V digital potentiometer. A level shift scheme is needed to enable a bidirectional communication so that the setting of the digital potentiometer can be stored to and retrieved from the E2PROM. Figure 7 shows one of the implementations. M1 and M2 can be any N-Ch signal FETs or low threshold FDV301N if VDD falls below 2.5 V.
VDD1 = 3.3V RP SDA1 M1 SCL1 3.3V E2PROM S M2 5V RP S G D G D SCL2 SDA2 RP RP VDD2 = 5V
Shutdown can be activated by strobing the SHDN pin or programming the SD bit in the Write Mode Instruction Byte. In addition, shutdown can even be implemented with the device digital output as shown in Figure 5. In this configuration, the device will be shut down during power-up, but users are allowed to program the device. Thus when O1 is programmed high, the device will exit from Shutdown Mode and respond to the new setting. This self-contained shutdown function allows absolute shutdown during power-up, which is crucial in hazardous environments, without adding extra components.
O1 SHDN RPD
AD5282
Figure 7. Level Shift for Different Potential Operation
LEVEL SHIFT FOR NEGATIVE VOLTAGE OPERATION
The digital potentiometer is popular in laser diode driver and certain telecommunications equipment level-setting applications. These applications are sometimes operated between ground and some negative supply voltage such that the systems can be biased at ground to avoid large bypass capacitors that may significantly impede the ac performance. Like most digital potentiometers, AD5280/AD5282 can be configured with a negative supply (see Figure 8).
VDD
SDA SCL
Figure 5. Shutdown by Internal Logic Output
-5V LEVEL SHIFTED LEVEL SHIFTED
VSS GND SDA SCL
Figure 8. Biased at Negative Voltage
REV. 0
-13-
AD5280/AD5282
However, the digital inputs must also be level shifted to allow proper operation since the ground is now referenced to the negative potential. As a result, Figure 9 shows one implementation with a few transistors and a few resistors. When VIN is below Q3's threshold value, Q3 is off, Q1 is off, and Q2 is on. In this state, VOUT approaches 0 V. When VIN is above 2 V, Q3 is on, Q1 is on, and Q2 is turned off. In this state, VOUT is pulled down to VSS. Beware that proper time shifting is also needed for successful communication with the device.
VDD +5V 0 Q1 0 R2 10k Q2 R3 10k VOUT 0 -5V VSS = -5V
POWER-UP SEQUENCE
Since there are ESD protection diodes that limit the voltage compliance at terminals A, B, and W (see Figure 11), it is important to power VDD/VSS before applying any voltage to terminals A, B, and W. Otherwise, the diode will be forward biased such that VDD/VSS will be powered unintentionally and may affect the rest of the user's circuit. The ideal power-up sequence is in the following order: GND, VDD, VSS, digital inputs, and VA/B/W. The order of powering VA, VB, VW, and digital inputs is not important as long as they are powered after VDD/V SS.
LAYOUT AND POWER SUPPLY BYPASSING
VIN
Q3 0
It is a good practice to employ compact, minimum lead length layout design. The leads to the input should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. Similarly, it is also a good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 F to 0.1 F disc or chip ceramics capacitors. Low ESR 1 F to 10 F tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and filter low frequency ripple (see Figure 12). Notice the digital ground should also be joined remotely to the analog ground at one point to minimize the digital ground bounce.
AD5280/AD5282
Figure 9. Level Shift for Bipolar Potential Operation
ESD PROTECTION
All digital inputs are protected with a series input resistor and parallel Zener ESD structures shown in Figure 10; applies to digital input pins, SDA, SCL, and SHDN.
340 LOGIC
VDD
C3 10 F
C4 10 F
VDD
+
C1 0.1 F
C2 0.1 F
VSS GND
+
VSS
VSS
Figure 10a. ESD Protection of Digital Pins
A, B, W
Figure 12. Power Supply Bypassing
APPLICATIONS Bipolar DC or AC Operation from Dual Supplies
VSS
Figure 10b. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5280/AD5282 positive VDD and negative VSS power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on terminals A, B, and W that exceed VDD or VSS will be clamped by the internal forward biased diodes (see Figure 11).
VDD A W B VSS
The AD5280/AD5282 can be operated from dual supplies enabling control of ground referenced ac signals or bipolar operation. The ac signal, as high as VDD/VSS, can be applied directly across terminals A-B with the output taken from terminal W. See Figure 13 for a typical circuit connection.
+5.0V
VDD C GND SCLK MOSI SCL SDA
VDD
A1 W1 B1 2.5V p-p D = 80H A2 W2 B2 5V p-p
AD5282
GND
Figure 11. Maximum Terminal Voltages Set by VDD and VSS
VSS -5.0V
Figure 13. Bipolar Operation from Dual Supplies
-14-
REV. 0
AD5280/AD5282
Gain Control Compensation 8-Bit Bipolar DAC
The digital potentiometer is commonly used in gain control such as the noninverting gain amplifier shown in Figure 14.
200k B W C2 4.7pF 47k R1 C1 25pF Vi U1 VO A
Figure 16 shows a low cost, 8-bit, bipolar DAC. It offers the same number of adjustable steps but not the precision as compared to the conventional DACs. The linearity and temperature coefficients, especially at low value codes, are skewed by the effects of the digital potentiometer wiper resistance. The output of this circuit is:
2D VO = - 1 x VREF 256
+15V
(5)
Vi
U2 U1 W B VOUT TRIM +5VREF R A R +15V
OP2177
A2 -15V 5VREF
VO
Figure 14. Typical Noninverting Gain Amplifier
Notice the RDAC B terminal parasitic capacitance is connected to the op amp noninverting node. It introduces a zero for the 1/ term with 20 dB/dec, whereas a typical op amp GBP has -20 dB/dec characteristics. A large R2 and finite C1 can cause this zero's frequency to fall well below the crossover frequency. Thus the rate of closure becomes 40 dB/dec and the system has 0 phase margin at the crossover frequency. The output may ring or oscillate if the input is a rectangular pulse or step function. Similarly, it is also likely to ring when switching between two gain values because this is equivalent to a step change at the input. Depending on the op amp GBP, reducing the feedback resistor may extend the zero's frequency far enough to overcome the problem. A better approach is to include a compensation capacitor C2 to cancel the effect caused by C1. Optimum compensation occurs when R1 x C1 = R2 x C2. This is not an option because of the variation of R2. As a result, one may use the relationship above and scale C2 as if R2 is at its maximum value. Doing so may overcompensate and compromise the performance slightly when R2 is set at low values. However, it will avoid the gain peaking, ringing, or oscillation at the worst case. For critical applications, C2 should be found empirically to suit the need. In general, C2 in the range of a few pF to no more than a few tenths of pF is usually adequate for the compensation. Similarly, there are W and A terminal capacitances connected to the output (not shown); fortunately their effect at this node is less significant and the compensation can be avoided in most cases.
Programmable Voltage Reference
VIN
GND ADR425
OP2177
U2 = AD5280 A1 -15V
Figure 16. 8-Bit Bipolar DAC
Bipolar Programmable Gain Amplifier
For applications that require bipolar gain, Figure 17 shows one implementation similar to the previous circuit. The digital potentiometer, U1, sets the adjustment range. The wiper voltage at W2 can therefore be programmed between Vi and -KVi at a given U2 setting. Configuring A2 in the Noninverting Mode allows linear gain and attentuation. The transfer function is:
VO R2 D2 = 1 + x (1 + K ) - K x Vi R1 256
(6)
where K is the ratio of RWB1/RWA1 set by U1.
VDD U2 V+
W2 A2 B2
AD5282
OP2177
V- C1 R2 A2 -kVi VDD V+ R1 VSS
VO
Vi
A1
B1 W1
For Voltage Divider Mode operation, Figure 15, it is common to buffer the output of the digital potentiometer unless the load is much larger than RWB. Not only does the buffer serve the purpose of impedance conversion, it also allows a heavier load to be driven.
5V U1 1 VIN VOUT 3 GND 2 AD1582
U1
AD5282
OP2177
V- A1
VSS
Figure 17. Bipolar Programmable Gain Amplifier
AD5280
A B W 5V
V+ AD8601 V- A1 VO
Similar to the previous example, in the simpler (and much more usual) case, where K = 1, a single digital potentiometer AD5280 is used and U1 is replaced by a matched pair of resistors to apply Vi and -Vi at the ends of the digital potentiometer. The relationship becomes:
R2 2D2 VO = 1 + - 1 x Vi R1 256
(7)
Figure 15. Programmable Voltage Reference
If R2 is large, a few pF compensation capacitor may be needed to avoid any gain peaking. -15-
REV. 0
AD5280/AD5282
Table III shows the result of adjusting D, with A2 configured as a unity gain, a gain of 2, and a gain of 10. The result is a bipolar amplifier with linearly programmable gain and 256-step resolution.
3 +5V 2 VIN SLEEP VOUT 6 U1 0 TO (2.048 + VL) B C1 1F A +5V - W RS 102
Table III. Result of Bipolar Gain Amplifier
REF191
GND 4
D 0 64 128 192 255
R1 = -1 -0.5 0 0.5 0.968
, R2 = 0
R1 = R2 -2 -1 0 1 1.937
R2 = 9R1 -10 -5 0 5
AD5280
-2.048V TO VL
V+ U2
OP8510
+ RL 100 R1 150k R2 15k +15V - +5V A V+ R2B 50 V- -5V VL IL
9.680
Programmable Voltage Source with Boosted Output
Figure 19. Programmable 4 to 20 mA Current Source
For applications that require high current adjustments such as a laser diode driver or tunable laser, a boosted voltage source can be considered (see Figure 18).
Vi 5V N1 CC A U1 B W A1 V- U1 = AD5280 A1 = AD8601, AD8605, AD8541 N1 = FDV301N, 2N7002 SIGNAL V+ LD VO RBIAS IL
The circuit is simple, but beware of two things. First, dual supply op amps are ideal because the ground potential of REF191 can swing from -2.048 V at zero scale to VL at full scale of the potentiometer setting. Although the circuit works under single supply, the programmable resolution of the system will be reduced. For applications that demand higher current capabilities, a few changes to the circuit in Figure 19 will produce an adjustable current in the range of hundreds of mA. First, the voltage reference needs to be replaced with a high current, low dropout regulator, such as the ADP3333, and the op amp needs to be swapped with a high current dual-supply model, such as the AD8532. Depending on the desired range of current, an appropriate value for RS must be calculated. Because of the high current flowing to the load, the user must pay attention to the load impedance so as not to drive the op amp beyond the positive rail.
Programmable Bidirectional Current Source
Figure 18. Programmable Booster Voltage Source
In this circuit, the inverting input of the op amp forces the VBIAS to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the supply via the N-Ch FET N1. N1's power handling must be adequate to dissipate (Vi-VO) x IL power. This circuit can source a maximum of 100 mA with a 5 V supply. A1 needs to be a rail-to-rail input type. Fore precision applications, a voltage reference such as ADR423, ADR292, or AD1584 can be applied at the input of the digital potentiometer.
Programmable 4 to 20 mA Current Source
For applications that require bidirectional current control or higher voltage compliance, a Howland current pump can be a solution (see Figure 20). If the resistors are matched, the load current is:
A programmable 4 to 20 mA current source can be implemented with the circuit shown in Figure 19. REF191 is a unique, low supply headroom and high current handling precision reference that can deliver 20 mA at 2.048 V. The load current is simply the voltage across terminals B to W of the digital potentiometer divided by RS:
(R2A + R2B ) R1 IL = xVW R2B
(9)
C1 10pF
V xD IL = REF N RS x 2
OP2177
+15V + V+ R1 150k + V- A2
(8)
AD5280
-15V R2A 14.95k VL RL 500 IL
W -5V
OP2177
- V- A1
-15V
Figure 20. Programmable Bidirectional Current Source
-16-
REV. 0
AD5280/AD5282
R2B in theory can be made as small as needed to achieve the current needed within A2's output current driving capability. In this circuit, OP2177 can deliver 5 mA in either direction, and the voltage compliance approaches 15 V. It can be shown that the output impedance is:
ZO = R1 x R2B (R1 + R2A ) R1 x R2 - R1(R2A + R2B )
PROGRAMMABLE OSCILLATOR
(10)
In a classic Wien-bridge oscillator (Figure 22), the Wien network (R, R', C, C') provides positive feedback, while R1 and R2 provide negative feedback. At the resonant frequency, fo, the overall phase shift is zero, and the positive feedback causes the circuit to oscillate. With R = R', C = C', and R2 = R2A//(R2B + Rdiode), the oscillation frequency is: O = 1 1 or fO = RC 2RC (14)
This output impedance can be infinite if resistors R1' and R2' match precisely with R1 and R2A + R2B, respectively. On the other hand, it can be negative if the resistors are not matched. As a result, C1 in the range of 1 pF to 10 pF, is needed to prevent the oscillation.
Programmable Low-Pass Filter
where R is equal RWA such that: 256 - D RAB 256 At resonance, setting: R= R2 =2 R1 (15)
In A/D conversion applications, it is common to include an antialiasing filter to band-limit the sampling signal. Dual-channel digital potentiometers can be used to construct a second order Sallen Key low-pass filter (see Figure 21). The design equations are:
(16)
VO = Vi
o 2 S 2 + o S + o Q
2
balances the bridge. In practice, R2/R1 should be set slightly larger than 2 to ensure the oscillation can start. On the other hand, the alternate turn-on of the diodes D1 and D2 ensures that R2/R1 are smaller than 2 momentarily, and therefore stabilizes the oscillation. Once the frequency is set, the oscillation amplitude can be tuned by R2B since: 2 VO = ID R2B + VD 3 (17)
(11)
O =
Q=
1 R1R2C1C 2
(12) (13)
1 1 + R1C1 R2C 2
Users can first select some convenient values for the capacitors. To achieve maximally flat bandwidth where Q = 0.707, let C1 be twice the size of C2 and let R1 = R2. As a result, the user can adjust R1 and R2 to the same settings to achieve the desirable bandwidth.
C1 C +2.5V R1 Vi A B W R R C2 ADJUSTED TO SAME SETTING C A R2 B W V+
V0, ID, and VD are interdependent variables. With proper selection of R2B, an equilibrium will be reached such that VO converges. R2B can be in series with a discrete resistor to increase the amplitude, but the total resistance cannot be too large to prevent saturation of the output.
FREQUENCY ADJUSTMENT VP C 2.2nF B R 10k A V+ W C 2.2nF +2.5V R 10k A W B
OP1177
VO
R1 = R1' = R2B = AD5282 D1 = D2 = 1N4148 VN R2B 10k R1 1k B W A V- -2.5V
U1
VO
AD8601
V- U1 -2.5V
R2A 2.1k
D1 D2
Figure 21. Sallen Key Low-Pass Filter
AMPLITUDE ADJUSTMENT
Figure 22. Programmable Oscillator with Amplitude Control
REV. 0
-17-
AD5280/AD5282
Resistance Scaling RDAC CIRCUIT SIMULATION MODEL
RDAC 20k
AD5280/AD5282 offers 20 k, 50 k, and 200 k nominal resistance. Users who need a lower resistance and the same number of step adjustments can place multiple devices in parallel. For example, Figure 23 shows a simple scheme of paralleling both channels of the AD5282. To adjust half of the resistance linearly per step, users need to program both channels to the same settings.
VDD A1 B1 LD W1 A2 B2 W2
A CA 25pF
B CB 25pF
CW 55pF W
Figure 26. RDAC Circuit Simulation Model for RDAC = 20 k
Figure 23. Reduce Resistance by Half with Linear Adjustment Characteristics
Applicable only to the Voltage Divider Mode, by paralleling a discrete resistor as shown in Figure 24, a proportionately lower voltage appears at terminal A. This translates into a finer degree of precision because the step size at terminal W will be smaller. The voltage can be found as:
The internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the RDACs. Configured as a potentiometer divider, the -3 dB bandwidth of the AD5280 (20 k resistor) measures 310 kHz at half scale. TPC 19 provides the large signal BODE plot characteristics of the three available resistor versions--20 k, 50 k, and 200 k. A parasitic simulation model is shown in Figure 26. A macro model net list for the 20 k RDAC is provided.
Macro Model Net List for RDAC
VW (D) =
D VDD x x (RAB // R2 ) (18) 256 R 3 + RAB // R2
VDD R3
A R2 R1 B 0 W
.PARAM D=256, RDAC=20E3 * .SUBCKT DPOT (A,W,B) * CA A 0 RWA A W CW W 0 RWB W B CB B 0 * .ENDS DPOT
25E-12 {(1-D/256)*RDAC+60} 55E-12 {D/256*RDAC+60} 25E-12
Figure 24. Lowering the Nominal Resistance
Figures 23 and 24 show that the digital potentiometers change steps linearly. On the other hand, log taper adjustment is usually preferred in applications like volume control. Figure 25 shows another way of resistance scaling. In this circuit, the smaller the R2 with respect to RAB, the more the pseudo log taper characteristic behaves.
Vi A R1 B W R2 VO
Figure 25. Resistor Scaling with Log Adjustment Characteristics
-18-
REV. 0
AD5280/AD5282
Resistance Tolerance, Drift, and Temperature Coefficient Mismatch Considerations
In a Rheostat Mode operation such as gain control, Figure 27, the tolerance mismatch between the digital potentiometer and the discrete resistor can cause repeatability issues among various systems. Because of the inherent matching of the silicon process, it is practical to apply the dual-channel device in this type of application. As such, R1 should be replaced by one of the channels of the digital potentiometer. R1 should be programmed to a specific value while R2 can be used for the adjustable gain. Although it adds cost, this approach minimizes the tolerance and temperature coefficient mismatch between R1 and R2. In addition, this approach also tracks the resistance drift over time. As a result, these nonideal parameters become less sensitive to the system variations.
B R2 W A
Notice the circuit in Figure 28 can also be used to track the tolerance, temperature coefficient, and drift in this particular application. However, the characteristics of the transfer function change from a linear to pseudo-logarithmic gain function.
R A W B C1
AD8601 Vi U1
VO
Figure 28. Nonlinear Gain Control with Tracking Resistance Tolerance and Drift
R1*
C1 AD8601 Vi U1 VO
*REPLACED WITH ANOTHER CHANNEL OF RDAC
Figure 27. Linear Gain Control with Tracking Resistance Tolerance and Drift
REV. 0
-19-
AD5280/AD5282
OUTLINE DIMENSIONS 14-Lead Thin Shrink Small Outline Package (TSSOP) (RU-14)
Dimensions shown in millimeters
5.10 5.00 4.90
14
8
4.50 4.40 4.30
1 7
6.40 BSC
PIN 1 1.05 1.00 0.80 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19
0.20 0.09 8 0
SEATING COPLANARITY PLANE 0.10
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
16-Lead Thin Shrink Small Outline Package (TSSOP) (RU-16)
Dimensions shown in millimeters
5.10 5.00 4.90
16
9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 1.20 MAX 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8 0 0.75 0.60 0.45
0.15 0.05
COMPLIANT TO JEDEC STANDARDS MO-153AB
-20-
REV. 0
PRINTED IN U.S.A.
C02929-0-10/02(0)
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