View KSZ8995XA_465753.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

KS8995XA
Micrel, Inc.
KS8995XA
Integrated 5-Port 10/100 QoS Switch Rev. 2.3
General Description
The KS8995XA is a highly integrated Layer-2 quality of service (QoS) switch with optimized bill of materials (BOM) cost for low port count, cost-sensitive 10/100Mbps switch systems. It also provides an extensive feature set including three different QoS priority schemes, a dual MII interface for BOM cost reduction, rate limiting to offload CPU tasks, software and hardware power-down, a MDC/MDIO control interface and port mirroring/monitoring to effectively address both current and emerging Fast Ethernet applications. The KS8995XA contains five 10/100 transceivers with patented mixed-signal low-power technology, five media access control (MAC) units, a high-speed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. All PHY units support 10BASE-T and 100BASE-TX. In addition, two of the PHY units support 100BaseFX (Ports 4 and 5).
Features
* Integrated switch with five MACs and five Fast Ethernet transceivers fully compliant to IEEE 802.3u standard * Shared memory based switch fabric with fully nonblocking configuration * 10BASE-T, 100BASE-TX and 100BASE-FX modes (FX in Ports 4 and 5) * Dual MII configuration: MII-Switch (MAC or PHY mode MII) and MII-P5 (PHY mode MII) * VLAN ID tag/untag options, per-port basis * Enable/disable option for huge frame size up to 1916 bytes per frame * Broadcast storm protection with percent control - global and per-port basis * Optimization for fiber-to-copper media conversion * Full-chip hardware power-down support (register configuration not saved) * Per-port-based software power-save on PHY (idle link detection, register configuration preserved) * QoS/CoS packets prioritization supports: per port, 802.1p and DiffServ-based
Functional Diagram
Auto MDI/MDI-X Auto MDI/MDI-X Auto MDI/MDI-X Auto MDI/MDI-X Auto MDI/MDI-X MII-P5 MDC, MDI/O MII-SW or SNI LED0[5:1] LED1[5:1] LED2[5:1]
10/100 T/Tx 1 10/100 T/Tx 2 10/100 T/Tx 3 10/100 T/Tx/Fx 4 10/100 T/Tx/Fx 5
10/100 MAC 1
1K Look-Up Engine
FIFO, Flow Control, VLAN Tagging, Priority
10/100 MAC 2 10/100 MAC 3 10/100 MAC 4 10/100 MAC 5 SNI
Queue Mgmnt
Buffer Mgmnt
Frame Buffers
LED I/F
Control Registers
EEPROM I/F
KS8995XA
Micrel, Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel + 1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
May 2005
1
M9999-051305
KS8995XA
Micrel, Inc.
Features (continued)
* 802.1p/q tag insertion or removal on a per-port basis (egress) * Port-based VLAN support * MDC and MDI/O interface support to access the MII PHY control registers (not all control registers) * MII local loopback support * On-chip 64Kbyte memory for frame buffering (not shared with 1K unicast address table) * 1.4Gbps high performance memory bandwidth * Wire-speed reception and transmission * Integrated look-up engine with dedicated 1K unicast MAC addresses * Automatic address learning, address aging and address migration * Full-duplex IEEE 802.3x and half-duplex back pressure flow control * Comprehensive LED support * 7-wire SNI support for legacy MAC interface * Automatic MDI/MDI-X crossover for plug-and-play * Disable automatic MDI/MDI-X option * Low power Core: 1.8V I/O: 2.5 or 3.3V * 0.18m CMOS technology * Commercial temperature range: 0C to +70C * Available in 128-pin PQFP package
Applications
* * * * * * * * * Broadband gateway/firewall/VPN Integrated DSL or cable modem multi-port router Wireless LAN access point plus gateway Home networking expansion Standalone 10/100 switch Hotel/campus/MxU gateway Enterprise VoIP gateway/phone FTTx customer premise equipment Media converter
Ordering Information
Part Number KS8995XA KSZ8995XA Temp. Range 0C to +70C 0C to +70C Package 128-Pin PQFP 128-Pin PQFP Lead Finish Standard Pb-Free
M9999-051305
2
May 2005
KS8995XA
Micrel, Inc.
Revision History
Revision 2.0 2.1 2.2 2.3 Date 10/15/03 4/1/04 1/19/05 4/13/05 Summary of Changes Created. Editorial changes on TTL input and output electrical characteristics. Insert recommeneded reset circuit. Switched pins names for pins 7 & 8 on page 16. Changed VDDIO to 3.3V. Changed Jitter to 16 ns Max.
May 2005
3
M9999-051305
KS8995XA
Micrel, Inc.
Table of Contents
System Level Applications .............................................................................................................................................................. 6 Pin Description (by Number) ........................................................................................................................................................... 8 Pin Description (by Name) ............................................................................................................................................................ 13 Pin Configuration ........................................................................................................................................................................... 18 Introduction ............................................................................................................................................................................ 19 Functional Overview: Physical Layer Transceiver ..................................................................................................................... 19 100BASE-TX Transmit ............................................................................................................................................................ 19 100BASE-TX Receive ............................................................................................................................................................. 19 PLL Clock Synthesizer ............................................................................................................................................................ 19 Scrambler/De-scrambler (100BASE-TX only) ......................................................................................................................... 19 100BaseFX Operation ............................................................................................................................................................. 19 100BaseFX Signal Detection ................................................................................................................................................... 20 100BaseFX Far End Fault ....................................................................................................................................................... 20 10BASE-T Transmit ................................................................................................................................................................. 20 10BASE-T Receive .................................................................................................................................................................. 20 Power Management ................................................................................................................................................................ 20 MDI/MDI-X Auto Crossover ..................................................................................................................................................... 20 Auto-Negotiation ...................................................................................................................................................................... 20 Functional Overview: Switch Core ............................................................................................................................................... 21 Address Look Up ..................................................................................................................................................................... 21 Learning Migration Aging ............................................................................................................................................................................ 21 ............................................................................................................................................................................ 21 ............................................................................................................................................................................ 21
Switching Engine ..................................................................................................................................................................... 21 MAC (Media Access Controller) Operation ............................................................................................................................. 22 Inter-Packet Gap ............................................................................................................................................................. 22 Backoff Algorithm ............................................................................................................................................................ 22 Late Collision .................................................................................................................................................................. 22 Illegal Frame ................................................................................................................................................................... 22 Flow Control .................................................................................................................................................................... 22 Half-Duplex Back Pressure ............................................................................................................................................. 22 Broadcast Storm Protection ............................................................................................................................................ 23 MII Interface Operation .................................................................................................................................................................. 23 SNI Interface Operation ................................................................................................................................................................. 25 Advanced Functionality ................................................................................................................................................................. 25 QoS Support ............................................................................................................................................................................ 25 Rate Limit Support ................................................................................................................................................................... 27 Configuration Interface ............................................................................................................................................................ 28 I2C Master Serial Bus Configuration ............................................................................................................................... 28 MII Management Interface (MIIM) .................................................................................................................................................. 28 Register Map ............................................................................................................................................................................ 29 Global Registers ...................................................................................................................................................................... 29 Register 0 (0x00): Chip ID0 ............................................................................................................................................ 29 Register 1 (0x01): Chip ID1/Start Switch ....................................................................................................................... 29 Register 2 (0x02): Global Control 0 ................................................................................................................................ 29 Register 3 (0x03): Global Control 1 ................................................................................................................................ 30 Register 4 (0x04): Global Control 2 ................................................................................................................................ 31 Register 5 (0x05): Global Control 3 ................................................................................................................................ 31 Register 6 (0x06): Global Control 4 ................................................................................................................................ 32 Register 7 (0x07): Global Control 5 ................................................................................................................................ 32 M9999-051305
4
May 2005
KS8995XA
Micrel, Inc.
Register 8 (0x08): Global Control 6 ................................................................................................................................ 32 Register 9 (0x09): Global Control 7 ................................................................................................................................ 32 Register 10 (0x0A): Global Control 8 ............................................................................................................................. 32 Register 11 (0x0B): Global Control 9 ............................................................................................................................. 33
Port Registers .......................................................................................................................................................................... 33 Register 16 (0x10): Port 1 Control 0 .............................................................................................................................. 33 Register 17 (0x11): Port 1 Control 1 .............................................................................................................................. 34 Register 18 (0x12): Port 1 Control 2 .............................................................................................................................. 34 Register 19 (0x13): Port 1 Control 3 .............................................................................................................................. 35 Register 20 (0x14): Port 1 Control 4 .............................................................................................................................. 35 Register 21 (0x15): Port 1 Control 5 .............................................................................................................................. 35 Register 22 (0x16): Port 1 Control 6 .............................................................................................................................. 35 Register 23 (0x17): Port 1 Control 7 .............................................................................................................................. 36 Register 24 (0x18): Port 1 Control 8 .............................................................................................................................. 36 Register 25 (0x19): Port 1 Control 9 .............................................................................................................................. 36 Register 26 (0x1A): Port 1 Control 10 ............................................................................................................................ 36 Register 27 (0x1B): Port 1 Control 11 ............................................................................................................................ 37 Register 28 (0x1C): Port 1 Control 12 ............................................................................................................................ 37 Register 29 (0x1D): Port 1 Control 13 ............................................................................................................................ 38 Register 30 (0x1E): Port 1 Status 0 ............................................................................................................................... 39 Register 31 (0x1F): Port 1 Control 14 ............................................................................................................................ 39 Advanced Control Registers .................................................................................................................................................... 39 Register 96 (0x60): TOS Priority Control Register 0 ...................................................................................................... 39 Register 97 (0x61): TOS Priority Control Register 1 ...................................................................................................... 40 Register 98 (0x62): TOS Priority Control Register 2 ...................................................................................................... 40 Register 99 (0x63): TOS Priority Control Register 3 ...................................................................................................... 40 Register 100 (0x64): TOS Priority Control Register 4 .................................................................................................... 40 Register 101 (0x65): TOS Priority Control Register 5 .................................................................................................... 40 Register 102 (0x66): TOS Priority Control Register 6 .................................................................................................... 40 Register 103 (0x67): TOS Priority Control Register 7 .................................................................................................... 40 Register 104 (0x68): MAC Address Register 0 .............................................................................................................. 40 Register 105 (0x69): MAC Address Register 1 .............................................................................................................. 40 Register 106 (0x6A): MAC Address Register 2 .............................................................................................................. 40 Register 107 (0x6B): MAC Address Register 3 .............................................................................................................. 40 Register 108 (0x6C): MAC Address Register 4 ............................................................................................................. 40 Register 109 (0X6D): MAC Address Register 5 ............................................................................................................. 40 MIIM Registers ........................................................................................................................................................................ 40 Register 0: MII Control ................................................................................................................................................... 40 Register 1: MII Status .................................................................................................................................................... 41 Register 2: PHYID HIGH ................................................................................................................................................ 41 Register 3: PHYID LOW ................................................................................................................................................ 41 Register 4: Advertisement Ability ................................................................................................................................... 41 Register 5: Link Partner Ability ....................................................................................................................................... 42 Absolute Maximum Ratings .......................................................................................................................................................... 43 Operating Ratings .......................................................................................................................................................................... 43 Electrical Characteristics .............................................................................................................................................................. 43 Timing Diagrams ............................................................................................................................................................................ 45 Selection of Isolation Transformers ............................................................................................................................................. 50 Package Information ...................................................................................................................................................................... 51
May 2005
5
M9999-051305
KS8995XA
Micrel, Inc.
System Level Applications
10/100 MAC 1
Switch Controller On-Chip Frame Buffers
10/100 PHY 1 10/100 PHY 2 10/100 PHY 3 10/100 PHY 4 10/100 PHY 5
EEPROM I/F 1-port WAN I/F EEPROM 4-port LAN
10/100 MAC 2 10/100 MAC 3 10/100 MAC 4 10/100 MAC 5
Ethernet MAC CPU Ethernet MAC
MII-SW
MII-P5
KS8995XA
External WAN port PHY not required.
Figure 1. Broadband Gateway
Switch Controller On-Chip Frame Buffers
10/100 MAC 1 10/100 MAC 2 10/100 MAC 3 10/100 MAC 4 10/100 MAC 5
10/100 PHY 1 10/100 PHY 2 10/100 PHY 3 10/100 PHY 4 10/100 PHY 5
EEPROM I/F EEPROM 4-port LAN
WAN PHY & AFE (XDSL, CM...)
CPU Ethernet MAC MII-SW
MII-P5
KS8995XA
Figure 2. Integrated Broadband Router
M9999-051305
6
May 2005
KS8995XA
Micrel, Inc.
10/100 MAC 1
Switch Controller On-Chip Frame Buffers
10/100 PHY 1 10/100 PHY 2 10/100 PHY 3 10/100 PHY 4 10/100 PHY 5
EEPROM I/F
EEPROM
10/100 MAC 2 10/100 MAC 3 10/100 MAC 4 10/100 MAC 5
5-port LAN
KS8995XA
Figure 3. Standalone Switch
May 2005
7
M9999-051305
KS8995XA
Micrel, Inc.
Pin Description (by Number)
Pin Number 1 Pin Name MDI-XDIS Type(1) I Port 1-5 Pin Function(2) Disable auto MDI/MDI-X. PD (default) = normal operation. PU = disable auto MDI/MDI-X on all ports. Analog ground. 1.8V analog VDD. 1 1 Physical receive signal + (differential). Physical receive signal - (differential). Analog ground. 1 1 Physical transmit signal + (differential). Physical transmit signal - (differential). 2.5V or 3.3V analog VDD. 2 2 Physical receive signal + (differential). Physical receive signal - (differential). Analog ground. 2 2 Physical transmit signal + (differential). Physical transmit signal - (differential). 1.8V analog VDD. Analog ground. Set physical transmit output current. Pull-down with a 3.01k 1% resistor. P I I Gnd O O P I I Gnd O O Gnd 4 4 4 4 3 3 3 3 2.5V or 3.3V analog VDD. Physical receive signal + (differential). Physical receive signal - (differential). Analog ground. Physical transmit signal + (differential). Physical transmit signal - (differential). 2.5V or 3.3V analog VDD. Physical receive signal + (differential). Physical receive signal - (differential). Analog ground. Physical transmit signal + (differential). Physical transmit signal - (differential). Analog ground.
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground.
GNDA VDDAR RXP1 RXM1 GNDA TXP1 TXM1 VDDAT RXP2 RXM2 GNDA TXP2 TXM2 VDDAR GNDA ISET VDDAT RXP3 RXM3 GNDA TXP3 TXM3 VDDAT RXP4 RXM4 GNDA TXP4 TXM4 GNDA
Gnd P I I Gnd O O P I I Gnd O O P Gnd
Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. 2. PU = Strap pin pull-up. PD = Strap pull-down. Otri = Output tristated.
M9999-051305
8
May 2005
KS8995XA
Pin Number 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62
Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. 2. PU = Strap pin pull-up. PD = Strap pull-down. Otri = Output tristated.
Micrel, Inc.
Pin Name VDDAR RXP5 RXM5 GNDA TXP5 TXM5 VDDAT FXSD5 FXSD4 GNDA VDDAR GNDA VDDAR GNDA NC / MUX1 NC / MUX2 PWRDN_N RESERVE/NC GNDD VDDC PMTXEN PMTXD3 PMTXD2 PMTXD1 PMTXD0 PMTXER PMTXC GNDD VDDIO PMRXC PMRXDV PMRXD3 Gnd P Ipd Ipd Ipd Ipd Ipd Ipd O Gnd P O Ipd/O Ipd/O 5 5 5 5 5 5 5 5 5 5 Type(1) P I I Gnd O O P I I Gnd P Gnd P Gnd I I Ipu 5 4 5 5 5 5 Port Pin Function(2) 1.8V analog VDD. Physical receive signal + (differential). Physical receive signal - (differential). Analog ground. Physical transmit signal + (differential). Physical transmit signal - (differential). 2.5V or 3.3V analog VDD. Fiber signal detect/factory test pin. Fiber signal detect/factory test pin. Analog ground. 1.8V analog VDD. Analog ground. 1.8V analog VDD. Analog ground. No connect. Factory test pin. No connect. Factory test pin. Full-chip power down. Active low. Reserved pin. No connect. Digital ground. 1.8V digital core VDD. PHY[5] MII transmit enable. PHY[5] MII transmit bit 3. PHY[5] MII transmit bit 2. PHY[5] MII transmit bit 1. PHY[5] MII transmit bit 0. PHY[5] MII transmit error. PHY[5] MII transmit clock. PHY mode MII. Digital ground. 3.3V digital VDD for digital I/O circuitry. PHY[5] MII receive clock. PHY mode MII. PHY[5] MII receive data valid. PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow control; PU = disable flow control.
May 2005
9
M9999-051305
KS8995XA
Pin Number 63 64 65 Pin Name PMRXD2 PMRXD1 PMRXD0 Type(1) Ipd/O Ipd/O Ipd/O Port 5 5 5 Pin Function(2)
Micrel, Inc.
PHY[5] MII receive bit 2. Strap option: PD (default) = disable back pressure; PU = enable back pressure. PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive collision packets; PU = does not drop excessive collision packets. PHY[5] MII receive bit 0. Strap option: PD (default) = disable aggressive back-off algorithm in half-duplex mode; PU = enable for performance enhancement. PHY[5] MII receive error. Strap option: PD (default) = packet size 1518/1522 bytes; PU = 1536 bytes. PHY[5] MII carrier sense/force duplex mode. See "Register 28." PHY[5] MII collision detect/force flow control. See "Register 18." Switch MII transmit enable. Switch MII transmit bit 3. Switch MII transmit bit 2. Switch MII transmit bit 1. Switch MII transmit bit 0. Switch MII transmit error. Switch MII transmit clock. PHY or MAC mode MII. Digital ground. 3.3V digital VDD for digital I/O circuitry. Switch MII receive clock. PHY or MAC mode MII. Switch MII receive data valid. Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MII full-duplex flow control; PU = Enable Switch MII full-duplex flow control. Switch MII receive bit 2. Strap option: PD (default) = Switch MII in full-duplex mode; PU = Switch MII in half-duplex mode. Switch MII receive bit 1. Strap option: PD (default) = Switch MII in 100Mbps mode; PU = Switch MII in 10Mbps mode. Switch MII receive bit 0; Strap option: see "Register 11[1]." Switch MII collision detect. Switch mode carrier sense.
66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground.
PMRXER PCRS PCOL SMTXEN SMTXD3 SMTXD2 SMTXD1 SMTXD0 SMTXER SMTXC GNDD VDDIO SMRXC SMRXDV SMRXD3 SMRXD2 SMRXD1 SMRXD0 SCOL SCRS
Ipd/O Ipd/O Ipd/O Ipd Ipd Ipd Ipd Ipd Ipd I/O Gnd P I/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O
5 5 5
Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. 2. PU = Strap pin pull-up. PD = Strap pull-down. Otri = Output tristated.
M9999-051305
10
May 2005
KS8995XA
Pin Number 86 Pin Name SCONF1 Type(1) Ipd Port Pin Function(2) Dual MII configuration pin. Pin# (91, 86, 87): 000 001 010 011 100 101 110 111 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108
Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. 2. PU = Strap pin pull-up. PD = Strap pull-down. Otri = Output tristated.
Micrel, Inc.
Switch MII Disable, Otri PHY Mode MII MAC Mode MII PHY Mode SNI Disable PHY Mode MII MAC Mode MII PHY Mode SNI
PHY [5] MII Disable, Otri Disable, Otri Disable, Otri Disable, Otri Disable PHY Mode MII PHY Mode MII PHY Mode MII
SCONF0 GNDD VDDC LED5-2 LED5-1 LED5-0 LED4-2 LED4-1 LED4-0 LED3-2 LED3-1 LED3-0 GNDD VDDIO LED2-2 LED2-1 LED2-0 LED1-2 LED1-1 LED1-0 MDC MDIO
Ipd Gnd P Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Gnd P Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu Ipu/O 2 2 2 1 1 1 All All 5 5 5 4 4 4 3 3 3
Dual MII configuration pin. Digital ground. 1.8V digital core VDD. LED indicator 2. Aging setup. See "Aging" section. LED indicator 1. Strap option: PU (default): enable PHY MII I/F. PD: tristate all PHY MII output. See "Pin# 86 SCONF1." LED indicator 0. LED indicator 2. LED indicator 1. LED indicator 0. LED indicator 2. LED indicator 1. LED indicator 0. Digital ground. 3.3V digital VDD for digital I/O. LED indicator 2. LED indicator 1. LED indicator 0. LED indicator 2. LED indicator 1. LED indicator 0. Switch or PHY[5] MII management data clock. Switch or PHY[5] MII management data I/O.
May 2005
11
M9999-051305
KS8995XA
Pin Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
Note: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. NC = No connect.
Micrel, Inc.
Pin Name Reserved SCL SDA Reserved PS1 PS0 RST_N GNDD VDDC TESTEN SCANEN NC X1 X2 VDDAP GNDA VDDAR GNDA GNDA TEST2 Ipd Ipd Ipu Gnd P Ipd Ipd NC I O P Gnd P Gnd Gnd I/O I/O Type(1) Port All All All All Pin Function No connect. Output clock at 81kHz in I2C master mode. Serial data input/output in I2C master mode. No connect No connect or pull-down. No connect or pull-down. Reset the KS8995XA. Active low. Digital ground. 1.8V digital core VDD. Factory test pin. Factory test pin. No connection. 25MHz crystal clock connection/or 3.3V tolerant oscillator input. Oscillator should be 100ppm. 25MHz crystal clock connection. 1.8V analog VDD for PLL. Analog ground. 1.8V analog VDD. Analog ground. Analog ground. Factory test pin.
M9999-051305
12
May 2005
KS8995XA
Micrel, Inc.
Pin Description (by Name)
Pin Number 39 38 2 6 12 16 21 27 30 34 40 42 44 120 124 126 127 49 58 76 88 99 116 17 106 105 104 103 102 101 98 97
Note: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. NC = No connect.
Pin Name FXSD4 FXSD5 GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA NC GNDA GNDA GNDA GNDD GNDD GNDD GNDD GNDD GNDD ISET LED1-0 LED1-1 LED1-2 LED2-0 LED2-1 LED2-2 LED3-0 LED3-1
Type(1) I I Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd NC Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd
Port 4 5
Pin Function Fiber signal detect/factory test pin. Fiber signal detect/factory test pin. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. No connection. Analog ground. Analog ground. Analog ground. Digital ground. Digital ground. Digital ground. Digital ground. Digital ground. Digital ground. Set physical transmit output current. Pull down with a 3.01k 1% resistor.
Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O
1 1 1 2 2 2 3 3
LED indicator 0. LED indicator 1. LED indicator 2. LED indicator 0. LED indicator 1. LED indicator 2. LED indicator 0. LED indicator 1.
May 2005
13
M9999-051305
KS8995XA
Pin Number 96 95 94 93 92 91 90 107 108 45 46 68 67 60 65 Pin Name LED3-2 LED4-0 LED4-1 LED4-2 LED5-0 LED5-1 LED5-2 MDC MDIO NC / MUX1 NC / MUX2 PCOL PCRS PMRXC PMRXD0 Ipd/O Ipd/O O Ipd/O Type(1) Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu Ipu/O Port 3 4 4 4 5 5 5 All All I I 5 5 5 5 Pin Function(2) LED indicator 2. LED indicator 0. LED indicator 1. LED indicator 2. LED indicator 0.
Micrel, Inc.
LED indicator 1. Strap option: PU (default): enable PHY MII I/F Pd: tristate all PHY MII output. See "Pin# 86 SCONF1." LED indicator 2. Aging setup. See "Aging" section. Switch or PHY[5] MII management data clock. Switch or PHY[5] MII management data I/O. No connect. Factory test pin. No connect. Factory test pin. PHY[5] MII collision detect/ Force flow control. See "Register 18." PHY[5] MII carrier sense/Force duplex mode. See "Register 28." PHY[5] MII receive clock. PHY mode MII. PHY[5] MII receive bit 0. Strap option: PD (default) = disable aggressive back-off algorithm in half-duplex mode; PU = enable for performance enhancement. PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive collision packets; PU = does not drop excessive collision packets. PHY[5] MII receive bit 2. Strap option: PD (default) = disable back pressure; PU = enable back pressure. PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow control; PU = disable flow control. PHY[5] MII receive data valid. PHY[5] MII receive error. Strap option: PD (default) = packet size 1518/ 1522 bytes; PU = 1536 bytes. PHY[5] MII transmit clock. PHY mode MII. PHY[5] MII transmit bit 0. PHY[5] MII transmit bit 1. PHY[5] MII transmit bit 2. PHY[5] MII transmit bit 3. PHY[5] MII transmit enable. PHY[5] MII transmit error. No connect or pull down. No connect or pull down.
64 63 62 61 66 57 55 54 53 52 51 56 114 113
Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground.
PMRXD1 PMRXD2 PMRXD3 PMRXDV PMRXER PMTXC PMTXD0 PMTXD1 PMTXD2 PMTXD3 PMTXEN PMTXER PS0 PS1
Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O O Ipd Ipd Ipd Ipd Ipd Ipd Ipd Ipd
5 5 5 5 5 5 5 5 5 5 5 5
Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. 2. PU = Strap pin pull-up. PD = Strap pull-down.
M9999-051305
14
May 2005
KS8995XA
Pin Number 47 48 109 112 115 5 11 20 26 33 4 10 19 25 32 119 110 84 87 86 Pin Name PWRDN_N RESERVE/NC Reserved Reserved RST_N RXM1 RXM2 RXM3 RXM4 RXM5 RXP1 RXP2 RXP3 RXP4 RXP5 SCANEN SCL SCOL SCONF0 SCONF1 Ipu I I I I I I I I I I Ipd I/O Ipd/O Ipd Ipd All 1 2 3 4 5 1 2 3 4 5 All All Type(1) Ipu Port Pin Function(2) Full-chip power down. Active low. Reserved pin. No connect. No connect. No connect. Reset the KS8995X. Active low. Physical receive signal - (differential). Physical receive signal - (differential). Physical receive signal - (differential). Physical receive signal - (differential). Physical receive signal - (differential). Physical receive signal + (differential). Physical receive signal + (differential). Physical receive signal + (differential). Physical receive signal + (differential). Physical receive signal + (differential). Factory test pin. Output clock at 81kHz in I2C master mode. See "Pin# 113." Switch MII collision detect. Dual MII configuration pin. Dual MII configuration pin. Pin# (91, 86, 87): 000 001 010 011 100 101 110 111 85 111 78 83
Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. 2. Otri = Output tristated.
Micrel, Inc.
Switch MII Disable, Otri PHY Mode MII MAC Mode MII PHY Mode SNI Disable PHY Mode MII MAC Mode MII PHY Mode SNI
PHY [5] MII Disable, Otri Disable, Otri Disable, Otri Disable, Otri Disable PHY Mode MII PHY Mode MII PHY Mode MII
SCRS SDA SMRXC SMRXD0
Ipd/O I /O I/O Ipd/O All
Switch MII carrier sense. Serial data input/output in I2C master mode. See "Pin# 113." Switch MII receive clock. PHY or MAC mode MII. Switch MII receive bit 0; strap option: see "Register 11[1]."
May 2005
15
M9999-051305
KS8995XA
Pin Number 82 81 80 79 75 73 72 71 70 69 74 1 128 118 7 13 22 28 35 8 14 23 29 36 123 3 15 31 41 43 125
Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. 2. PU = Strap pin pull-up. PD = Strap pull-down.
Micrel, Inc.
Pin Name SMRXD1 SMRXD2 SMRXD3 SMRXDV SMTXC SMTXD0 SMTXD1 SMTXD2 SMTXD3 SMTXEN SMTXER MDIXDIS TEST2 TESTEN TXP1 TXP2 TXP3 TXP4 TXP5 TXM1 TXM2 TXM3 TXM4 TXM5 VDDAP VDDAR VDDAR VDDAR VDDAR VDDAR VDDAR Ipd O O O O O O O O O O P P P P P P P 1 2 3 4 5 1 2 3 4 5 Type(1) Ipd/O Ipd/O Ipd/O Ipd/O I/O Ipd Ipd Ipd Ipd Ipd Ipd I 1-5 Port Pin Function(2) Switch MII receive bit 1. Strap option: PD (default) = Switch MII in 100Mbps mode; PU = Switch MII in 10Mbps mode. Switch MII receive bit 2. Strap option: PD (default) = Switch MII in fullduplex mode; PU = Switch MII in half-duplex mode. Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MII full-duplex flow control; PU = Enable Switch MII full-duplex flow control. Switch MII receive data valid. Switch MII transmit clock. PHY or MAC mode MII. Switch MII transmit bit 0. Switch MII transmit bit 1. Switch MII transmit bit 2. Switch MII transmit bit 3. Switch MII transmit enable. Switch MII transmit error. Disable auto MDI/MDI-X. Factory test pin. Factory test pin. Physical transmit signal + (differential). Physical transmit signal + (differential). Physical transmit signal + (differential). Physical transmit signal + (differential). Physical transmit signal + (differential). Physical transmit signal - (differential). Physical transmit signal - (differential). Physical transmit signal - (differential). Physical transmit signal - (differential). Physical transmit signal - (differential). 1.8V analog VDD for PLL. 1.8V analog VDD. 1.8V analog VDD. 1.8V analog VDD. 1.8V analog VDD. 1.8V analog VDD. 1.8V analog VDD.
M9999-051305
16
May 2005
KS8995XA
Pin Number 9 18 24 37 50 89 117 59 77 100 121 122
Note: 1. P = Power supply. I = Input. O = Output.
Micrel, Inc.
Pin Name VDDAT VDDAT VDDAT VDDAT VDDC VDDC VDDC VDDIO VDDIO VDDIO X1 X2 Type(1) P P P P P P P P P P I O Port Pin Function 2.5V or 3.3V analog VDD. 2.5V or 3.3V analog VDD. 2.5V or 3.3V analog VDD. 2.5V or 3.3V analog VDD. 1.8V digital core VDD. 1.8V digital core VDD. 1.8V digital core VDD. 3.3V digital VDD for digital I/O circuitry. 3.3V digital VDD for digital I/O circuitry. 3.3V digital VDD for digital I/O circuitry. 25MHz crystal clock connection/or 3.3V tolerant oscillator input. Oscillator should be 100ppm. 25MHz crystal clock connection.
May 2005
17
M9999-051305
KS8995XA
M9999-051305
LED2-0 LED1-2 LED1-1 LED1-0 MDC MDIO SPIQ SPIC/SCL SPID/SDA SPIS_N PS1 PS0 RST_N GNDD VDDC TESTEN SCANEN NC X1 X2 VDDAP GNDA VDDAR GNDA GNDA TEST2 103 1
Pin Configuration
128-Pin PQFP (PQ)
18
39
65
MDIXDIS GNDA VDDAR RXP1 RXM1 GNDA TXP1 TXM1 VDDAT RXP2 RXM2 GNDA TXP2 TXM2 VDDAR GNDA ISET VDDAT RXP3 RXM3 GNDA TXP3 TXM3 VDDAT RXP4 RXM4 GNDA TXP4 TXM4 GNDA VDDAR RXP5 RXM5 GNDA TXP5 TXM5 VDDAT FXSD5
LED2-1 LED2-2 VDDIO GNDD LED3-0 LED3-1 LED3-2 LED4-0 LED4-1 LED4-2 LED5-0 LED5-1 LED5-2 VDDC GNDD SCONF0 SCONF1 SCRS SCOL SMRXD0 SMRXD1 SMRXD2 SMRXD3 SMRXDV SMRXC VDDIO GNDD SMTXC SMTXER SMTXD0 SMTXD1 SMTXD2 SMTXD3 SMTEXN PCOL PCRS PMRXER PMRXD0
PMRXD1 PMRXD2 PMRXD3 PMRXDV PMRXC VDDIO GNDD PMTXC PMTXER PMTXD0 PMTXD1 PMTXD2 PMTXD3 PMTXEN VDDC GNDD RESERVE PWRDN_N MUX2 MUX1 GNDA VDDAR GNDA VDDAR GNDA FXSD4
Micrel, Inc.
May 2005
KS8995XA
Micrel, Inc.
Introduction
The KS8995XA contains five 10/100 physical layer transceivers and five media access control (MAC) units with an integrated Layer 2 switch. The device runs in three modes. The first mode is as a five-port integrated switch. The second is as a five-port switch with the fifth port decoupled from the physical port. In this mode access to the fifth MAC is provided through a media independent interface (MII) . This is useful for implementing an integrated broadband router. The third mode uses the dual MII feature to recover the use of the fifth PHY. This allows the additional broadband gateway configuration, where the fifth PHY may be accessed through the MII-P5 port. The KS8995XA is optimized for an unmanaged design in which the configuration is achieved through I/O strapping or EEPROM programming at system reset time. On the media side, the KS8995XA supports IEEE 802.3 10BASE-T, 100BASE-TX on all ports, and 100BASE-FX on ports 4 and 5. The KS8995XA can be used as two separate media converters. Physical signal transmission and reception are enhanced through the use of patented analog circuitry that makes the design more efficient and allows for lower power consumption and smaller chip die size. The major enhancements from the KS8995E to the KS8995XA are support for programmable rate limiting, a dual MII interface, MDC/MDIO control interface for IEEE 802.3-defined register configuration (not all the registers), per-port broadcast storm protection, local loopback and lower power consumption. The KS8995XA is pin-compatible to the managed switch, the KS8995M.
Functional Overview: Physical Layer Transceiver
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding followed by a scrambler. The serialized data is further converted from NRZ to NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 3.01k resistor for the 1:1 transformer ratio. It has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX transmitter.
100BASE-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristics to optimize the performance. In this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then it tunes itself for optimization. This is an ongoing process and can self-adjust against environmental changes such as temperature variations. The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of baseline wander and improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
PLL Clock Synthesizer
The KS8995XA generates 125MHz, 42MHz, 25MHz, and 10MHz clocks for system timing. Internal clocks are generated from an external 25MHz crystal.
Scrambler/De-Scrambler (100BASE-TX only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. The data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047-bit nonrepetitive sequence. The receiver will then de-scramble the incoming data stream with the same sequence at the transmitter.
100BASE-FX Operation
100BASE-FX operation is very similar to 100BASE-TX operation except that the scrambler/de-scrambler and MLT3 encoder/ decoder are bypassed on transmission and reception. In this mode the auto-negotiation feature is bypassed since there is no standard that supports fiber auto-negotiation.
May 2005
19
M9999-051305
KS8995XA
Micrel, Inc.
100BASE-FX Signal Detection
The physical port runs in 100BASE-FX mode if FXSDx >0.6V for ports 4 and 5 only. This signal is internally referenced to 1.25V.The fiber module interface should be set by a voltage divider such that FXSDx `H' is above this 1.25V reference, indicating signal detect, and FXSDx `L' is below the 1.25V reference to indicate no signal. When FXSDx is below 0.6V then 100BASE-FX mode is disabled.
100BASE-FX Far End Fault
Far end fault occurs when the signal detection is logically false from the receive fiber module. When this occurs, the transmission side signals the other end of the link by sending 84 1's followed by a zero in the idle period between frames. The far end fault may be disabled through register settings.
10BASE-T Transmit
The output 10BASE-T driver is incorporated into the 100BASE-T driver to allow transmission with the same magnetics. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents are at least 27dB below the fundamental when driven by an all-ones Manchester-encoded signal.
10BASE-T Receive
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with short pulsewidths in order to prevent noises at the RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KS8995XA decodes a data frame. The receiver clock is maintained active during idle periods in between data reception.
Power Management
The KS8995XA features a per port power down mode. To save power the user can power down ports that are not in use by setting port control registers or MII control registers. In addition, it also supports full chip power down mode. When activated, the entire chip will be shutdown.
MDI/MDI-X Auto Crossover
The KS8995XA supports MDI/MDI-X auto crossover. This facilitates the use of either a straight connection CAT-5 cable or a crossover CAT-5 cable. The auto-sense function will detect remote transmit and receive pairs, and correctly assign the transmit and receive pairs from the Micrel device. This can be highly useful when end users are unaware of cable types and can also save on an additional uplink configuration connection. The auto crossover feature may be disabled through the port control registers.
Auto-Negotiation
The KS8995XA conforms to the auto-negotiation protocol as described by the 802.3 committee. Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the best common mode of operation. In auto-negotiation the link partners advertise capabilities across the link to each other. If auto-negotiation is not supported or the link partner to the KS8995XA is forced to bypass auto-negotiation, then the mode is set by observing the signal at the receiver. This is known as parallel mode because while the transmitter is sending auto-negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol. The flow for the link set up is depicted in Figure 4.
M9999-051305
20
May 2005
KS8995XA
Start Auto Negotiation
Micrel, Inc.
Force Link Setting
No
Parallel Operation
Yes
Bypass Auto-Negotiation and Set Link Mode
Attempt Auto-Negotiation
Listen for 100BaseTX Idles
Listen for 10BaseT Link Pulses
No
Join Flow
Link Mode Set ?
Yes
Link Mode Set
Figure 4. Auto-Negotiation
Functional Overview: Switch Core
Address Look-Up
The internal look-up table stores MAC addresses and their associated information. It contains a 1K unicast address table plus switching information. The KS8995XA is guaranteed to learn 1K addresses and distinguishes itself from hash-based look-up tables which, depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn.
Learning
The internal look-up engine will update its table with a new entry if the following conditions are met: * The received packet's source address (SA) does not exist in the look-up table. * The received packet is good; the packet has no receiving errors, and is of legal length. The look-up engine will insert the qualified SA into the table, along with the port number, time stamp. If the table is full, the last entry of the table will be deleted first to make room for the new entry.
Migration
The internal look-up engine also monitors whether a station is moved. If it happens, it will update the table accordingly. Migration happens when the following conditions are met: * The received packet's SA is in the table but the associated source port information is different. * The received packet is good; the packet has no receiving errors, and is of legal length. The look-up engine will update the existing record in the table with the new source port information.
Aging
The look-up engine will update the time stamp information of a record whenever the corresponding SA appears. The time stamp is used in the aging process. If a record is not updated for a period of time, the look-up engine will remove the record from the table. The look-up engine constantly performs the aging process and will continuously remove aging records. The aging period is 300 75 seconds. This feature can be enabled or disabled through register 3 or by external pull-up or pull-down resistors on LED[5][2]. See "Register 3" section.
Switching Engine
The KS8995XA features a high performance switching engine to move data to and from the MAC's packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The KS8995XA has a 64kB internal frame buffer. This resource is shared between all five ports. The buffer sharing mode can be programmed through Register 2. See "Register 2." In one mode, ports are allowed to use any free buffers in the buffer pool. In the second mode, each port is only allowed to use 1/5 of the total buffer pool. There are a total of 512 buffers available. Each buffer is sized at 128B.
May 2005
21
M9999-051305
KS8995XA
Micrel, Inc.
Media Access Controller (MAC) Operation
The KS8995XA strictly abides by IEEE 802.3 standards to maximize compatibility.
Inter-Packet Gap (IPG) If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If the current packet is experiencing collision, the 96-bit time IPG is measured from MCRS and the next MTXEN. Backoff Algorithm The KS8995XA implements the IEEE Std. 802.3 binary exponential back-off algorithm, and optional "aggressive mode" back off. After 16 collisions, the packet will be optionally dropped depending on the chip configuration in Register 3. See "Register 3." Late Collision If a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be dropped. Illegal Frames The KS8995XA discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes in Register 4. For special applications, the KS8995XA can also be programmed to accept frames up to 1916 bytes in Register 4. Since the KS8995XA supports VLAN tags, the maximum sizing is adjusted when these tags are present. Flow Control The KS8995XA supports standard 802.3x flow control frames on both transmit and receive sides. On the receive side, if the KS8995XA receives a pause control frame, the KS8995XA will not transmit the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. During this period (being flow controlled), only flow control packets from the KS8995XA will be transmitted. On the transmit side, the KS8995XA has intelligent and efficient ways to determine when to invoke flow control. The flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues. The KS8995XA will flow control a port, which just received a packet, if the destination port resource is being used up. The KS8995XA will issue a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802.3x. Once the resource is freed up, the KS8995XA will send out the other flow control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to prevent the flow control mechanism from being activated and deactivated too many times. The KS8995XA will flow control all ports if the receive queue becomes full. Half-Duplex Back Pressure A half-duplex back pressure option (note: not in 802.3 standards) is also provided. The activation and deactivation conditions are the same as the above in full-duplex mode. If back pressure is required, the KS8995XA will send preambles to defer the other stations' transmission (carrier sense deference). To avoid jabber and excessive deference defined in 802.3 standard, after a certain time it will discontinue the carrier sense but it will raise the carrier sense quickly. This short silent time (no carrier sense) is to prevent other stations from sending out packets and keeps other stations in carrier sense deferred state. If the port has packets to send during a back pressure situation, the carrier-sense-type back pressure will be interrupted and those packets will be transmitted instead. If there are no more packets to send, carrier-sense-type back pressure will be active again until switch resources are free. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is generated immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets. To ensure no packet loss in 10BASE-T or 100BASE-TX half-duplex modes, the user must enable the following: * Aggressive backoff (register 3, bit 0) * No excessive collision drop (register 4, bit 3) * Back pressure (register 4, bit 5) These bits are not set as the default because this is not the IEEE standard.
M9999-051305
22
May 2005
KS8995XA
Micrel, Inc.
Broadcast Storm Protection The KS8995XA has an intelligent option to protect the switch system from receiving too many broadcast packets. Broadcast packets will be forwarded to all ports except the source port, and thus use too many switch resources (bandwidth and available space in transmit queues). The KS8995XA has the option to include "multicast packets" for storm control. The broadcast storm rate parameters are programmed globally, and can be enabled or disabled on a per port basis. The rate is based on a 50ms interval for 100BT and a 500ms interval for 10BT. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during the interval. The rate definition is described in Register 6 and Register 7. The default setting for registers 6 and 7 is 0x4A, which is 74 decimal. This is equal to a rate of 1%, calculated as follows: 148,800 frames/sec x 50ms/interval x 1% = 74 frames/interval (approx.) = 0x4A
MII Interface Operation
The media independent interface (MII) is specified by the IEEE 802.3 committee and provides a common interface between physical layer and MAC layer devices. The KS8995XA provides two such interfaces. The MII-P5 interface is used to connect to the fifth PHY, whereas the MII-SW interface is used to connect to the fifth MAC. Each of these MII interfaces contains two distinct groups of signals, one for transmission and the other for receiving. The table below describes the signals used in the MII-P5 interface. The MII-P5 interface operates in PHY mode only, while the MII-SW interface operates in either MAC mode or PHY mode. These interfaces are nibble-wide data interfaces and therefore run at 1/4 the network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has indicators that convey when the data is valid and without physical layer errors. For half-duplex operation, there is a signal that indicates a collision has occurred during transmission. Note that the signal MRXER is not provided on the MII-SW interface for PHY mode operation and the signal MTXER is not provided on the MII-SW interface for MAC mode operation. Normally MRXER would indicate a receive error coming from the physical layer device. MTXER would indicate a transmit error from the MAC device. These signals are not appropriate for this configuration. For PHY mode operation, if the device interfacing with the KS8995XA has an MRXER pin, it should be tied low. For MAC mode operation, if the device interfacing with the KS8995XA has an MTXER pin, it should be tied low.
MII Signal MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC MDC MDIO
Description Transmit enable Transmit error Transmit data bit 3 Transmit data bit 2 Transmit data bit 1 Transmit data bit 0 Transmit clock Collision detection Carrier sense Receive data valid Receive error Receive data bit 3 Receive data bit 2 Receive data bit 1 Receive data bit 0 Receive clock Management data clock Management data I/O
KS8995XA Signal PMTXEN PMTXER PMTXD[3] PMTXD[2] PMTXD[1] PMTXD[0] PMTXC PCOL PCRS PMRXDV PMRXER PMRXD[3] PMRXD[2] PMRXD[1] PMRXD[0] PMRXC MDC MDIO
Table 1. MII - P5 Signals (PHY Mode)
May 2005
23
M9999-051305
KS8995XA
Micrel, Inc.
PHY Mode Connection External MAC MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC KS8995XA Signal SMTXEN SMTXER SMTXD[3] SMTXD[2] SMTXD[1] SMTXD[0] SMTXC SCOL SCRS SMRXDV Not used SMRXD[3] SMRXD[2] SMRXD[1] SMRXD[0] SMRXC Description Transmit enable Transmit error Transmit data bit 3 Transmit data bit 2 Transmit data bit 1 Transmit data bit 0 Transmit clock Collision detection Carrier sense Receive data valid Receive error Receive data bit 3 Receive data bit 2 Receive data bit 1 Receive data bit 0 Receive clock
MAC Mode Connection External PHY MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC KS8995XA Signal SMRXDV Not used SMRXD[3] SMRXD[2] SMRXD[1] SMRXD[0] SMRXC SCOL SCRS SMTXEN SMTXER SMTXD[3] SMTXD[2] SMTXD[1] SMTXD[0] SMTXC
Table 2. MII - SW Signals
M9999-051305
24
May 2005
KS8995XA
Micrel, Inc.
SNI Interface Operation
The serial network interface (SNI) is compatible with some controllers used for network layer protocol processing. This interface can be directly connected to these types of devices. The signals are divided into two groups, one for transmission and the other for reception. The signals involved are described in the table below.
SNI Signal TXEN TXD TXC COL CRS RXD RXC Description Transmit Enable Serial Transmit Data Transmit Clock Collision Detection Carrier Sense Serial Receive Data Receive Clock KS8995XA Signal SMTXEN SMTXD[0] SMTXC SCOL SMRXDV SMRXD[0] SMRXC
Table 3. SNI Signals This interface is a bit-wide data interface and therefore runs at the network bit rate (not encoded). An additional signal on the transmit side indicates when data is valid. Likewise, the receive side has an indicator that conveys when the data is valid. For half-duplex operation there is a signal that indicates a collision has occurred during transmission.
Advanced Functionality
QoS Support
The KS8995XA is a QoS switch, meaning that is it able to identify selected packets on its ingress ports, prioritize them, and service the packets according to their priority on the egress ports. In this way, the KS8995XA can provide statistically better service to the high priority packets that are latency sensitive, or require higher bandwidth. The KS8995XA supports ingress QoS classification using three different mechanisms: port-based priority, 802.1p tag-based priority, and DSCP priority for IPv4 packets. Port-based priority is useful when the user wants to give a device on a given port high priority. For example in Figure 7, port 1 is given high priority because it is connected to an IP phone and port 4 is given lower priority because it is connected to a computer whose data traffic may be less sensitive to network congestion. Each port on the KS8995XA can be set as high or low priority with an EEPROM. The port priority is set in bit 4 of registers 0x10, 0x20, 0x30, 0x40, 0x50 for ports 1, 2, 3, 4 and 5, respectively. Port-based priority is overridden by the OR'ed result of the 802.1p and DSCP priorities if they are all enabled at the same time.
WAN
Router P5[0]=1, Hi/Lo Tx Priority Queues enabled
Hi-Pri Queue
P5 Lo-Pri
Queue
8995XA
P1 P1[3]=1 High Priority Port
IP Phone
P2
P3
P4
P4[3]=0 Low Priority Port
Figure 7. Port-Based Priority
May 2005
25
M9999-051305
KS8995XA
Micrel, Inc.
The KS8995XA can classify tagged packets using the 802.1p tag-based priority. In this prioritization scheme, the user can enable the 802.1p classification on a per port basis in bit 5 of registers 0x10, 0x20, 0x30, 0x40 and 0x50 for ports 1, 2, 3, 4, and 5, respectively. Then the user specifies the 802.1p base priority in register 0x02, bits [6-4]. When a tagged packet is received, the KS8995XA examines the 3 bit 802.1p priority field shown in Figure 8. These 3 bits are compared against the base priority. The prioritization policy is as follows:
Comparison 802.1p Priority Base Priority 802.1p Priority < Base Priority Priority High Low
Table 4. 802.1p Priority
Bytes
8 Preamble
6 DA
6 SA
4 TCI
2 Length LLC
46-1500 Data
4 CRC
Bits
16 Tagged Packet Type (8100 for Ethernet)
3 802.1p
1
CFI
12 VLAN ID
Figure 8. 802.3 Tagged Packet
Bytes 8 Preamble 6 DA 6 SA 4 Tag 2 2 Type Data CRC 46-1500 4
Bits
4 IP Ver. 0x4
46 Header Size DiffServ
2 Res.
Figure 9. IPv4 Packet In order to support QoS from end-to-end in a network, the KS8995XA can also classify packets based on the IPv4 DiffServ field shown in Figure 9. The DiffServ field consists of 6 bits, which can be used to specify 64 code points. The KS8995XA provides 64 bits (DSCP[63:0]) in 8 registers (0x60 to 0x67), in which the user specifies the priority of each of the 64 code points. The DiffServ classification is enabled on a per port basis in bit 6 of registers 0x10, 0x20, 0x30, 0x40 and 0x50 for ports 1, 2, 3, 4, and 5, respectively. If the DiffServ classification is enabled on a port, the KS8995XA will decode the IPv4 DiffServ field and look at the user defined code point bit to determine if the packet is high priority or low priority. If the code point is a `1', the packet is high priority. If the code point is `0', the packet is low priority.
M9999-051305
26
May 2005
KS8995XA
DiffServ Field (Binary) 000000 000001 000010 000011 000100 Code Point DSCP[0] DSCP[1] DSCP[2] DSCP[3] DSCP[4] KS8995X (Reg. and Bit) 0x67, bit 0 0x67, bit 1 0x67, bit 2 0x67, bit 3 0x67, bit 4
Micrel, Inc.
* * *
111011 111100 111101 111110 111111
* * *
DSCP[59] DSCP[60] DSCP[61] DSCP[62] DSCP[63]
* * *
0x60, bit 3 0x60, bit 4 0x60, bit 5 0x60, bit 6 0x60, bit 7
Table 5. DiffServ Code Point Once classification of the packets has been determined either by port-based priority, 802.1p tag-based priority or DiffServ priority, they are placed in either the high or low priority queue on the egress port. The user can enable the egress priority queues on a per port basis by setting bit 0 of registers 0x10, 0x20, 0x30, 0x40, and 0x50 for ports 1, 2, 3, 4 and 5, respectively. If the egress priority queue for a given port is not set, the port will treat all packets as if they are the same priority, even though packets are classified on their ingress ports. If the egress priority queue for a given port is enabled, packets are serviced based on the user programmable egress policy. The priority scheme selection is set in register 0x05 bits[3-2] as shown in Table 6.
Register 0x05, bit 3 0 0 1 1 Register 0x05, bit 2 0 1 0 1
Egress Priority Scheme Always deliver high priority packets first Deliver high/low priority packets at a ratio of 10/1 Deliver high/low priority packets at a ratio of 5/1 Deliver high/low priority packets at a ratio of 2/1
Table 6. Transmit Priority Ratio The KS8995XA offers support for port-based, 802.1p tag-based, and IPv4 DiffServ priority, as well as programmable egress policies. These KS8995XA QoS features enable identifying, classifying and forwarding packets based on their priority. The system designer is able to use this device to build network elements that give more control over system resources, priority service to mission critical applications, and can be integrated into the next generation of multimedia networks.
Rate Limit Support
KS8995XA supports hardware rate limiting on "receive" and "transmit" independently on a per port basis. It also supports rate limiting in a priority or non-priority environment. The rate limit starts from 0Kbps and goes up to the line rate in steps of 32Kbps. The KS8995XA uses one second as an interval. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during this interval. For receive, if the number of bytes exceeds the programmed limit, the switch will stop receiving packets on the port until the "one second" interval expires. There is an option provided for flow control to prevent packet loss. If the rate limit is programmed greater than or equal to 128Kbps and the byte counter is 8K bytes below the limit, the flow control will be triggered. If the rate limit is programmed lower than 128Kbps and the byte counter is 2K bytes below the limit, the flow control will be triggered. For transmit, if the number of bytes exceeds the programmed limit, the switch will stop transmitting packets on the port until the "one second" interval expires. If priority is enabled, the KS8995XA can support different rate controls for both high priority and low priority packets. This can be programmed through Registers 21 - 27.
May 2005
27
M9999-051305
KS8995XA
Micrel, Inc.
Configuration Interface
The KS8995XA functions as a unmanaged switch. If no EEPROM exists, the KS8995XA will operate from its default and strapin settings.
I2C Master Serial Bus Configuration If a 2-wire EEPROM exists, the KS8995XA can perform more advanced features like broadcast storm protection and rate control. The EEPROM should have the entire valid configuration data from register 0 to register 109 defined in the memory map, except the status registers. The configuration access time (tprgm) is less than 15ms as shown in Figure 10.
RST_N SCL SDA
.... .... ....
tprgm<15 ms
Figure 10. EEPROM Configuration Timing Diagram
To configure the KS8995XA with a pre-configured EEPROM use the following steps: * At the board level, connect pin 110 on the KS8995XA to the SCL pin on the EEPROM. Connect pin 111 on the KS8995XA to the SDA pin on the EEPROM. * Be sure the board-level reset signal is connected to the KS8995XA reset signal on pin 115 (RST_N). * Program the contents of the EEPROM before placing it on the board with the desired configuration data. Note that the first byte in the EEPROM must be "95" for the loading to occur properly. If this value is not correct, all other data will be ignored. * Place EEPROM on the board and power up the board. Assert the active-low board level reset to RST_N on the KS8995XA. After the reset is de-asserted, the KS8995XA will begin reading configuration data from the EEPROM. The configuration access time (tprgm) is less than 15ms. Note: For proper operation, make sure pin 47 (PWRDN_N) is not asserted during the reset operation.
MII Management Interface (MIIM)
A standard MIIM interface is provided for all five PHY devices in the KS8995XA. An external device with MDC/MDIO capability is able to read PHY status or to configure PHY settings. For details on the MIIM interface standard, please reference the IEEE 802.3 specification (section 22.2.4.5). The MIIM interface does not have access to all the configuration registers in the KS8995XA. It can only access the standard MII registers. See "MIIM Registers" section.
M9999-051305
28
May 2005
KS8995XA
Micrel, Inc.
Register Map
Offset Decimal 0-1 2-11 12-15 16-29 30-31 32-45 46-47 48-61 62-63 64-77 78-79 80-93 94-95 96-103 104-109 Hex 0x00-0x01 0x02-0x0B 0x0C-0x0F 0x10-0x1D 0x1E-0x2F 0x20-0x2D 0x2E-0x2F 0x30-0x3D 0x3E-0x3F 0x40-0x4D 0x4E-0x4F 0x50-0x5D 0x5E-0x5F 0x60-0x67 0x68-0x6D Description Chip ID Registers Global Control Registers Reserved Port 1 Control Registers Port 1 Status Registers Port 2 Control Registers Port 2 Status Registers Port 3 Control Registers Port 3 Status Registers Port 4 Control Registers Port 4 Status Registers Port 5 Control Registers Port 5 Status Registers TOS Priority Control Registers MAC Address Registers
Global Registers
Address Name Description Mode Default Register 0 (0x00): Chip ID0 7-0 Family ID Chip family RO 0x95
Register 1 (0x01): Chip ID1/Start Switch 7-4 3-1 0 Chip ID Revision ID Start switch 0x0 is assigned to 95 series. (95XA) Revision ID The chip starts automatically after trying to read the external EEPROM. If EEPROM does not exist, the chip will use default values for all internal registers. If EEPROM is present, the contents in the EEPROM will be checked. The switch will check: (1) Register 0 = 0x95, (2) Register 1 [7:4] = 0x0. If this check is OK, the contents in the EEPROM will override chip register default values. RO RO RW 0x0 0x2 --
Register 2 (0x02): Global Control 0 7 6-4 Reserved 802.1p base priority Reserved Used to classify priority for incoming 802.1q packets. "User priority" is compared against this value : classified as high priority < : classified as low priority 1 = enable PHY MII interface (note: if not enabled, the switch will tri-state all outputs.) R/W R/W 0x0 0x4
3
Enable PHY MII
R/W
Pin LED[5][1] strap option. Pull-down (0): isolate. Pull-up (1): Enable. Note: LED[5][1] has internal pull-up.
May 2005
29
M9999-051305
KS8995XA
Address Name Description Mode Default
Micrel, Inc.
Register 2 (0x02): Global Control 0 (continued) 2 Buffer share mode 1 = buffer pool is shared by all ports. A port can use more buffer when other ports are not busy. 0 = a port is only allowed to use 1/5 of the buffer pool. 1 = the switch will drop packets with 0x8808 in T/L filed, or DA=01-80-C2-00-00-01. 0 = the switch will drop packets qualified as "flow control" packets. 1 = link change from "link" to "no link" will cause fast aging (<800s) to age address table faster. After an age cycle is complete, the age logic will return to normal (300 75 seconds). Note: If any port is unplugged, all addresses will be automatically aged out. R/W 0x1
1
UNH mode
R/W
0
0
Link change age
R/W
0
Register 3 (0x03): Global Control 1 7 Pass all frames 1 = switch all packets including bad ones. Used solely for debugging purpose. Works in conjunction with sniffer mode. Reserved 0 = will enable transmit flow control based on AN result 1 = will not enable transmit flow control regardless of AN result. R/W 0
6 5
Reserved IEEE 802.3x transmit flow control disable
R/W R/W
0 Pin PMRXD3 strap option. Pull-down (0): Enable TX flow control. Pull-up (1): Disable TX/RX flow control. Note: PMRXD3 has internal pulldown. Pin PMRXD3 strap option. Pull-down (0): Enable RX flow control. Pull-up (1): Disable TX/RX flow control. Note: PMRXD3 has internal pulldown. 0
4
IEEE 802.3x receive flow control disable
0 = will enable receive flow control based on AN result 1 = will not enable receive flow control regardless of AN result. Note: Bit 5 and bit 4 default values are controlled by the same pin, but they can be programmed independently.
R/W
3
Frame length field check Aging enable
1 = will check frame length field in the IEEE packets. If the actual length does not match, the packet will be dropped. (for L/T < 1500) 1 = Enable age function in the chip 0 = Disable aging function
R/W
2
R/W
Pin LED[5][2] strap option. Pull-down (0): Aging disable. Pull-up (1): Aging Enable. Note: LED[5][2] has internal pull-up. 0 Pin PMRXD0 strap option. Pull-down (0): Disable aggressive back off. Pull-up (1): Aggressive backoff. Note: PMRXD0 has internal pulldown.
1 0
Fast age enable Aggressive back off enable
1 = turn on fast age (800s) 1 = enable more aggressive back off algorithm in halfduplex mode to enhance performance. This is not an IEEE standard.
R/W R/W
M9999-051305
30
May 2005
KS8995XA
Address Name Description Mode Default
Micrel, Inc.
Register 4 (0x04): Global Control 2 7 6 Reserved Multicast storm protection disable Reserved 1 = "Broadcast Storm Protection" does not include multicast packets. Only DA=FFFFFFFFFFFF packets will be regulated. 0 = "Broadcast Storm Protection" includes DA = FFFFFFFFFFFF and DA[40] = 1 packets. Reserved 1 = fair mode is selected. In this mode, if a flow control port and a non-flow control port talk to the same destination port, packets from the non-flow control port may be dropped. This is to prevent the flow control port from being flow controlled for an extended period of time. 0 = in this mode, if a flow control port and a non-flow control port talk to the same destination port, the flow control port will be flow controlled. This may not be "fair" to the flow control port. 1 = the switch will not drop packets when 16 or more collisions occur. 0 = the switch will drop packets when 16 or more collisions occur. R/W R/W 1 1
5 4
Reserved Flow control and back pressure fair mode
R/W R/W
1 1
3
No excessive collision drop
R/W
Pin PMRXD1 strap option. Pull-down (0): Drop excessive collision packets. Pull-up (1): Don't drop excessive collision packets. Note: PMRXD1 has internal pulldown. 0
2
Huge packet support
1 = will accept packet sizes up to 1916 bytes (inclusive). This bit setting will override setting from bit 1 of the same register. 0 = the max packet size will be determined by bit 1 of this register. 1 = will accept packet sizes up to 1536 bytes (inclusive). 0 = 1522 bytes for tagged packets (not including. packets with STPID from CPU to ports 1-4), 1518 bytes for untagged packets. Any packets larger than the specified value will be dropped.
R/W
1
Legal maximum packet size check disable
R/W
Pin PMRXER strap option. Pull-down (0): 1518/1522 byte packets. Pull-up value will be dropped. (1): 1536 byte packets Note: PMRXER has internal pull down. 0
0
Priority buffer reserve
1 = each output queue is pre-allocated 48 buffers, used exclusively for high priority packets. It is recommended to enable this when priority queue feature is turned on. 0 = no reserved buffers for high priority packets.
R/W
Register 5 (0x05): Global Control 3 7 6 5 4 3-2 Reserved Reserved Reserved Reserved Priority scheme select Reserved Reserved Reserved Reserved 00 = always deliver high priority packets first. 01 = deliver high/low packets at ratio 10/1. 10 = deliver high/low packets at ratio 5/1. 11 = deliver high/low packets at ratio 2/1. R/W R/W R/W R/W R/W 0 0 0 0 00
May 2005
31
M9999-051305
KS8995XA
Address Name Description Mode Default
Micrel, Inc.
Register 5 (0x05): Global Control 3 (continued) 1 0 Reserved Sniff mode select Reserved 1 = will do Rx AND Tx sniff (both source port and destination port need to match). 0 = will do Rx OR Tx sniff (either source port or destination port needs to match). This is the mode used to implement Rx only sniff. R/W R/W 0 0
Register 6 (0x06): Global Control 4 7 Switch MII back pressure enable Switch MII half duplex mode 1 = enable half-duplex back pressure on switch MII interface. 0 = disable back pressure on switch MII interface. 1 = enable MII interface half-duplex mode. 0 = enable MII interface full-duplex mode. R/W 0
6
R/W
Pin SMRXD2 strap option. Pull-down (0): Full-duplex mode. Pull-up (1): Halfduplex mode. Note: SMRXD2 has internal pulldown. Pin SMRXD3 strap option. Pull-down (0): disable flow control. Pull-up (1): enable flow control Note: SMRXD3 has internal pulldown. Pin SMRXD1 strap option. Pull-down (0): Enable 100Mbps Pull-up (1): Enable 10Mpbs. Note: SMRXD1 has internal pull-down. 0 000
5
Switch MII flow control enable
1 = enable full-duplex flow control on switch MII interface. 0 = disable full-duplex flow control on switch MII interface.
R/W
4
Switch MII 10BT
1 = the switch interface is in 10Mbps mode. 0 = the switch interface is in 100Mbps mode.
R/W
3 2-0
Null VID replacement Broadcast storm protection rate bit [10:8]
1 = will replace null VID with port VID (12 bits). 0 = no replacement for null VID. This along with the next register determines how many "64 byte blocks" of packet data allowed on an input port in a preset period. The period is 50ms for 100BT or 500ms for 10BT. The default is 1%.
R/W R/W
Register 7 (0x07): Global Control 5 7-0 Broadcast storm protection rate bit [7:0] This along with the previous register determines how many "64 byte blocks" of packet data are allowed on an input port in a preset period. The period is 50ms for 100BT or 500ms for 10BT. The default is 1%. R/W 0x4A(1)
Note: 1. 148,800 frames/sec x 50ms/interval x 1% = 74 frames/interval (approx.) = 0x4A.
Register 8 (0x08): Global Control 6 7-0 Factory testing Reserved R/W 0x24
Register 9 (0x09): Global Control 7 7-0 Factory testing Reserved R/W 0x24
Register 10 (0x0A): Global Control 8 7-0 M9999-051305 Factory testing Reserved R/W 0x24
32
May 2005
KS8995XA
Address Name Description Mode Default
Micrel, Inc.
Register 11 (0x0B): Global Control 9 7-4 3 2 1 Reserved PHY power save Factory setting LED mode N/A 0 = disable PHY power save mode. 1 = enable PHY power save mode. Reserved 0 = led mode 0 1 = led mode 1 0 R/W R/W R/W 0 0 Pin SMRXD0 strap option. Pull-down(0): Enabled led mode 0. Pull-up(1): Enabled. led mode 1. Note: SMRXD0 has internal pull-down 0. Mode 0 LEDX_2 LEDX_1 LEDX_0 0 Reserved Reserved Lnk/Act Fulld/Col Speed Mode 1 100Lnk/Act 10Lnk/Act Fulld RW 0
Port Registers
The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated.
Register 16 (0x10): Port 1 Control 0 Register 32 (0x20): Port 2 Control 0 Register 48 (0x30): Port 3 Control 0 Register 64 (0x40): Port 4 Control 0 Register 80 (0x50): Port 5 Control 0 Address 7 Name Broadcast storm protection enable DiffServ priority classification enable 802.1p priority classification enable Port-based priority classification enable Description 1 = enable broadcast storm protection for ingress packets on the port. 0 = disable broadcast storm protection. 1 = enable DiffServ priority classification for ingress packets on port. 0 = disable DiffServ function. 1 = enable 802.1p priority classification for ingress packets on port. 0 = disable 802.1p. 1 = ingress packets on the port will be classified as high priority if "DiffServ" or "802.1p" classification is not enabled or fails to classify. 0 = ingress packets on port will be classified as low priority if "DiffServ" or "802.1p" classification is not enabled or fails to classify. Note: "DiffServ", "802.1p" and port priority can be enabled at the same time. The OR'ed result of 802.1p and DSCP overwrites the port priority. 3 2 Reserved Tag insertion Reserved R/W 0 0 Mode R/W Default 0
6
R/W
0
5
R/W
0
4
R/W
0
1 = when packets are output on the port, the switch will R/W add 802.1q tags to packets without 802.1q tags when received. The switch will not add tags to packets already tagged. The tag inserted is the ingress port's "port VID." 0 = disable tag insertion.
May 2005
33
M9999-051305
KS8995XA
Address 1 Name Tag removal Description 1 = when packets are output on the port, the switch will remove 802.1q tags from packets with 802.1q tags when received. The switch will not modify packets received without tags. 0 = disable tag removal. 1 = the port output queue is split into high and low priority queues. 0 = single output queue on the port. There is no priority differentiation even though packets are classified into high or low priority. Mode R/W Default 0
Micrel, Inc.
0
Priority enable
R/W
0
Register 17 (0x11): Port 1 Control 1 Register 33 (0x21): Port 2 Control 1 Register 49 (0x31): Port 3 Control 1 Register 65 (0x41): Port 4 Control 1 Register 81 (0x51): Port 5 Control 1 Address 7 Name Sniffer port Description 1 = port is designated as sniffer port and will transmit packets that are monitored. 0 = port is a normal port. 1 = all the packets received on the port will be marked as "monitored packets" and forwarded to the designated "sniffer port." 0 = no receive monitoring. 1 = all the packets transmitted on the port will be marked as "monitored packets" and forwarded to the designated "sniffer port." 0 = no transmit monitoring. Define the port's Port VLAN membership. Bit 4 stands for port 5, bit 3 for port 4...bit 0 for port 1. The port can only communicate within the membership. A `1' includes a port in the membership, a `0' excludes a port from membership. Mode R/W Default 0
6
Receive sniff
R/W
0
5
Transmit sniff
R/W
0
4-0
Port VLAN membership
R/W
0x1f
Register 18 (0x12): Port 1 Control 2 Register 34 (0x22): Port 2 Control 2 Register 50 (0x32): Port 3 Control 2 Register 66 (0x42): Port 4 Control 2 Register 82 (0x52): Port 5 Control 2 Address 7 6 5 Name Reserved Reserved Discard non-PVID packets Force flow control Description Reserved Reserved 1 = the switch will discard packets whose VID does not match ingress port default VID. 0 = no packets will be discarded. 1 = will always enable Rx and Tx flow control on the port, regardless of AN result. 0 = the flow control is enabled based on AN result. Note: Setting a port for both half-duplex and forced flow control is an illegal configuration. For half-duplex enable back pressure. R/W R/W Mode Default 0x0 0 0
4
R/W
0 For port 4 only, there is a special configuration pin to set the default, Pin PCOL strap option. Pull-down (0): No force flow control. Pull-up (1): Force flow control. Note: PCOL has internal pull-down.
M9999-051305
34
May 2005
KS8995XA
Address 3 Name Back pressure enable Description 1 = enable port half-duplex back pressure. 0 = disable port half-duplex back pressure. Mode R/W Default
Micrel, Inc.
Pin PMRXD2 strap option. Pull-down (0): disable back pressure. Pull-up(1): enable back pressure. Note: PMRXD2 has internal pull-down. 1 1 0
2 1 0
Transmit enable Receive enable Learning disable
1 = enable packet transmission on the port. 0 = disable packet transmission on the port. 1 = enable packet reception on the port. 0 = disable packet reception on the port. 1 = disable switch address learning capability. 0 = enable switch address learning.
R/W R/W R/W
Register 19 (0x13): Port 1 Control 3 Register 35 (0x23): Port 2 Control 3 Register 51 (0x33): Port 3 Control 3 Register 67 (0x43): Port 4 Control 3 Register 83 (0x53): Port 5 Control 3 Address 7-0 Name Default tag [15:8] Description Port's default tag, containing: 7-5: user priority bits 4: CFI bit 3-0 : VID[11:8] Mode R/W Default 0
Register 20 (0x14): Port 1 Control 4 Register 36 (0x24): Port 2 Control 4 Register 52 (0x34): Port 3 Control 4 Register 68 (0x44): Port 4 Control 4 Register 84 (0x54): Port 5 Control 4 Address 7-0 Name Default tag [7:0] Description Default port 1's tag, containing: 7-0: VID[7:0] Mode R/W Default 1
Note: Registers 19 and 20 (and those corresponding to other ports) serve two purposes: (1) Associated with the ingress untagged packets, and used for egress tagging; (2) Default VID for the ingress untagged or null-VID-tagged packets, and used for address look up.
Register 21 (0x15): Port 1 Control 5 Register 37 (0x25): Port 2 Control 5 Register 53 (0x35): Port 3 Control 5 Register 69 (0x45): Port 4 Control 5 Register 85 (0x55): Port 5 Control 5 Address 7-0 Name Transmit high priority rate control [7:0] Description This along with port control 7, bits [3:0] form a 12-bit field to determine how many "32Kbps" high priority blocks can be transmitted (in a unit of 4K bytes in a one second period). Mode R/W Default 0
Register 22 (0x16): Port 1 Control 6 Register 38 (0x26): Port 2 Control 6 Register 54 (0x36): Port 3 Control 6 Register 70 (0x46): Port 4 Control 6 Register 86 (0x56): Port 5 Control 6 Address 7-0 Name Transmit low priority rate control [7:0] Description This along with port control 7, bits [7:4] form a 12-bit field to determine how many "32Kbps" low priority blocks can be transmitted (in a unit of 4K bytes in a one second period). Mode R/W Default 0
May 2005
35
M9999-051305
KS8995XA
Register 23 (0x17): Port 1 Control 7 Register 39 (0x27): Port 2 Control 7 Register 55 (0x37): Port 3 Control 7 Register 71 (0x47): Port 4 Control 7 Register 87 (0x57): Port 5 Control 7 Address 7-4 Name Transmit low priority rate control [11:8] Description This along with port control 6, bits [7:0] form a 12-bit field to determine how many "32Kbps" low priority blocks can be transmitted (in a unit of 4K bytes in a one second period). This along with port control 5, bits [7:0] form a 12-bit field to determine how many "32Kbps" high priority blocks can be transmitted (in unit of 4K bytes in a one second period). Mode R/W Default 0
Micrel, Inc.
3-0
Transmit high priority rate control [11:8]
R/W
0
Register 24 (0x18): Port 1 Control 8 Register 40 (0x28): Port 2 Control 8 Register 56 (0x38): Port 3 Control 8 Register 72 (0x48): Port 4 Control 8 Register 88 (0x58): Port 5 Control 8 Address 7-0 Name Receive high priority rate control [7:0] Description This along with port control 10, bits [3:0] form a 12-bit field to determine how many "32Kbps" high priority blocks can be received (in a unit of 4K bytes in a one second period). Mode R/W Default 0
Register 25 (0x19): Port 1 Control 9 Register 41 (0x29): Port 2 Control 9 Register 57 (0x39): Port 3 Control 9 Register 73 (0x49): Port 4 Control 9 Register 89 (0x59): Port 5 Control 9 Address 7-0 Name Receive low priority rate control [7:0] Description This along with port control 10, bits [7:4] form a 12-bit field to determine how many "32Kbps" low priority blocks can be received (in a unit of 4K bytes in a one second period). Mode R/W Default 0
Register 26 (0x1A): Port 1 Control 10 Register 42 (0x2A): Port 2 Control 10 Register 58 (0x3A): Port 3 Control 10 Register 74 (0x4A): Port 4 Control 10 Register 90 (0x5A): Port 5 Control 10 Address 7-4 Name Receive low priority rate control [11:8] Description This along with port control 9, bits [7:0] form a 12-bit field to determine how many "32Kbps" low priority blocks can be received (in a unit of 4K bytes in a one second period). This along with port control 8, bits [7:0] form a 12-bit field to determine how many "32Kbps" high priority blocks can be received (in a unit of 4K bytes in a one second period). Mode R/W Default 0
3-0
Receive high priority rate control [11:8]
R/W
0
M9999-051305
36
May 2005
KS8995XA
Register 27 (0x1B): Port 1 Control 11 Register 43 (0x2B): Port 2 Control 11 Register 59 (0x3B): Port 3 Control 11 Register 75 (0x4B): Port 4 Control 11 Register 91 (0x5B): Port 5 Control 11 Address 7 Name Receive differential priority rate control Description 1 = If bit 6 is also `1' this will enable receive rate control for this port on low priority packets at the low priority rate. If bit 5 is also `1', this will enable receive rate control on high priority packets at the high priority rate. 0 = receive rate control will be based on the low priority rate for all packets on this port. 1 = enable port's low priority receive rate control feature. 0 = disable port's low priority receive rate control. Mode R/W Default 0
Micrel, Inc.
6 5
Low priority receive rate control enable High priority receive rate control enable
R/W
0 0
1 = if bit 7 is also `1' this will enable the port's high R/W priority receive rate control feature. If bit 7 is a `0' and bit 6 is a `1', all receive packets on this port will be rate controlled at the low priority rate. 0 = disable port's high priority receive rate control feature. 1 = flow control may be asserted if the port's low priority receive rate is exceeded. 0 = flow control is not asserted if the port's low priority receive rate is exceeded. 1 = flow control may be asserted if the port's high priority receive rate is exceeded. To use this, differential receive rate control must be on. 0 = flow control is not asserted if the port's high priority receive rate is exceeded. 1 = transmit rate control on both high and low priority packets based on the rate counters defined by the high and low priority packets respectively. 0 = transmit rate control on any packets. The rate counters defined in low priority will be used. 1 = enable the port's low priority transmit rate control feature. 0 = disable the port's low priority transmit rate control feature. 1 = enable the port's high priority transmit rate control feature. 0 = disable the port's high priority transmit rate control feature. R/W
4
Low priority receive rate flow control enable
0
3
High priority receive rate flow control enable
R/W
0
2
Transmit differential priority rate control
R/W
0
1
Low priority transmit rate control enable
R/W
0
0
High priority transmit rate control enable
R/W
0
Register 28 (0x1C): Port 1 Control 12 Register 44 (0x2C): Port 2 Control 12 Register 60 (0x3C): Port 3 Control 12 Register 76 (0x4C): Port 4 Control 12 Register 92 (0x5C): Port 5 Control 12
Note: Port Control 12 and 13, and Port Status 0 contents can be accessed by MIIM (MDC/MDIO) interface via the standard MIIM register definition.
Address 7
Name Disable auto-negotiation
Description 1 = disable auto-negotiation, speed and duplex are decided by bit 6 and 5 of the same register. 0 = auto-negotiation is on. 1 = forced 100BT if AN is disabled (bit 7). 0 = forced 10BT if AN is disabled (bit 7).
Mode R/W
Default 0
6
Forced speed
R/W
1
May 2005
37
M9999-051305
KS8995XA
Address 5 Name Forced duplex Description 1 = forced full-duplex if (1) AN is disabled or (2) AN is enabled but failed. 0 = forced half-duplex if (1) AN is disabled or (2) AN is enabled but failed. Mode R/W Default
Micrel, Inc.
0 For port 4 only, there is a special configure pin to set the default pin PCRS strap option. Pull-down (0): Force half-duplex. Pull-up (1): Force full-duplex. Note: PCRS has internal pull down. 1
4
Advertised flow control capability Advertised 100BT full-duplex capability Advertised 100BT half-duplex capability Advertised 10BT full-duplex capability Advertised 10BT half-duplex capability
1 = advertise flow control capability. 0 = suppress flow control capability from transmission to link partner. 1 = advertise 100BT full-duplex capability. 0 = suppress 100BT full-duplex capability from transmission to link partner. 1 = advertise 100BT half-duplex capability. 0 = suppress 100BT half-duplex capability from transmission to link partner. 1 = advertise 10BT full-duplex capability. 0 = suppress 10BT full-duplex capability from transmission to link partner. 1 = advertise 10BT half-duplex capability. 0 = suppress 10BT half-duplex capability from transmission to link partner.
R/W
3
R/W
1
2
R/W
1
1
R/W
1
0
R/W
1
Register 29 (0x1D): Port 1 Control 13 Register 45 (0x2D): Port 2 Control 13 Register 61 (0x3D): Port 3 Control 13 Register 77 (0x4D): Port 4 Control 13 Register 93 (0x5D): Port 5 Control 13 Address 7 Name LED off Description 1 = turn off all port's LEDs (LEDx_2, LEDx_1, LEDx_0, where "x" is the port number). These pins will be driven high if this bit is set to one. 0 = normal operation. 1 = disable port's transmitter. 0 = normal operation. 1 = restart auto-negotiation. 0 = normal operation. 1 = disable far end fault detection and pattern transmission. 0 = enable far end fault detection and pattern transmission. 1 = power down. 0 = normal operation. 1 = disable auto MDI/MDI-X function. 0 = enable auto MDI/MDI-X function. 1 = if auto MDI/MDI-X is disabled, force PHY into MDI mode. 0 = do not force PHY into MDI mode. 1 = perform MAC loopback. 0 = normal operation. Mode R/W Default 0
6 5 4 3 2 1
Txids Restart AN Disable far end fault Power down Disable auto MDI/MDI-X Forced MDI
R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0
0
MAC loopback
R/W
0
Register 30 (0x1E): Port 1 Status 0
M9999-051305
38
May 2005
KS8995XA
Register 46 (0x2E): Port 2 Status 0 Register 62 (0x3E): Port 3 Status 0 Register 78 (0x4E): Port 4 Status 0 Register 94 (0x5E): Port 5 Status 0 Address 7 6 5 4 3 2 1 0 Name MDIX status AN done Link good Partner flow control capability Partner 100BT full-duplex capability Partner 100BT half-duplex capability Partner 10BT full-duplex capability Partner 10BT half-duplex capability Description 1 = MDI. 0 = MDI-X. 1 = AN done. 0 = AN not done. 1 = link good. 0 = link not good. 1 = link partner flow control capable. 0 = link partner not flow control capable. 1 = link partner 100BT full-duplex capable. 0 = link partner not 100BT full-duplex capable. 1 = link partner 100BT half-duplex capable. 0 = link partner not 100BT half-duplex capable. 1 = link partner 10BT full-duplex capable. 0 = link partner not 10BT full-duplex capable. 1 = link partner 10BT half-duplex capable. 0 = link partner not 10BT half-duplex capable. Mode RO RO RO RO RO RO RO RO Default 0 0 0 0 0 0 0 0
Micrel, Inc.
Register 31 (0x1F): Port 1 Control 14 Register 47 (0x2F): Port 2 Control 14 Register 63 (0x3F): Port 3 Control 14 Register 79 (0x4F): Port 4 Control 14 Register 95 (0x5F): Port 5 Control 14 Address 7 Name PHY loopback Description 1 = perform PHY loopback, i.e. loopback MAC's Tx back to Rx. 0 = normal operation. 1 = perform remote loopback, i.e. loopback PHY's Rx back to Tx. 0 = normal operation. 1 = electrical isolation of PHY from MII and TX+/TX-. 0 = normal operation. 1 = PHY soft reset. 0 = normal operation. 1 = force link in the PHY. 0 = normal operation. N/A 1 = far end fault status detected. 0 = no far end fault status detected. Mode R/W Default 0
6
Remote loopback
R/W
0
5 4 3 2-1 0
PHY isolate Soft reset Force link Reserved Far end fault
R/W R/W R/W RO RO
0 0 0 0 0
Advanced Control Registers
The IPv4 TOS priority control registers implement a fully decoded 64 bit differentiated services code point (DSCP) register used to determine priority from the 6 bit TOS field in the IP header. The most significant 6 bits of the TOS field are fully decoded into 64 possibilities, and the singular code that results is compared against the corresponding bit in the DSCP register. If the register bit is a 1, the priority is high; if it is a 0, the priority is low.
Address Name Description Mode Default
Register 96 (0x60): TOS Priority Control Register 0 7-0 DSCP[63:56] R/W 00000000
May 2005
39
M9999-051305
KS8995XA
Address Name Description Mode Default
Micrel, Inc.
Register 97 (0x61): TOS Priority Control Register 1 7-0 DSCP[55:48] R/W 00000000
Register 98 (0x62): TOS Priority Control Register 2 7-0 DSCP[47:40] R/W 00000000
Register 99 (0x63): TOS Priority Control Register 3 7-0 DSCP[39:32] R/W 00000000
Register 100 (0x64): TOS Priority Control Register 4 7-0 DSCP[31:24] R/W 00000000
Register 101 (0x65): TOS Priority Control Register 5 7-0 DSCP[23:16] R/W 00000000
Register 102 (0x66): TOS Priority Control Register 6 7-0 DSCP[15:8] R/W 00000000
Register 103 (0x67): TOS Priority Control Register 7 7-0 DSCP[7:0] R/W 00000000
Registers 104 to 109 define the switching engine's MAC address. This 48-bit address is used as the source address in MAC pause control frames.
Register 104 (0x68): MAC Address Register 0 7-0 MACA[47:40] R/W 0x00
Register 105 (0x69): MAC Address Register 1 7-0 MACA[39:32] R/W 0x10
Register 106 (0x6A): MAC Address Register 2 7-0 MACA[31:24] R/W 0xA1
Register 107 (0x6B): MAC Address Register 3 7-0 MACA[23:16] R/W 0xff
Register 108 (0x6C): MAC Address Register 4 7-0 MACA[15:8] R/W 0xff
Register 109 (0X6D): MAC Address Register 5 7-0 MACA[7:0] R/W 0xff
MIIM Registers
The "PHYAD" defined by IEEE is assigned as "0x1" for port 1, "0x2" for port 2, "0x3" for port 3, "0x4" for port 4, "0x5" for port 5. The "REGAD" supported are 0,1,2,3,4,5.
Address Name Description Mode Default
Register 0: MII Control 15 14 13 12 11 10 Soft reset Loop back Force 100 AN enable Power down Isolate 1 = PHY soft reset. 0 = normal operation. 1 = loop back mode (loop back at PHY). 0 = normal operation. 1 = 100Mbps. 0 = 10Mbps. 1 = auto-negotiation enabled. 0 = auto-negotiation disabled. 1 = power down. 0 = normal operation. Not supported. RO R/W R/W R/W R/W RO 0 0 1 1 0 0
M9999-051305
40
May 2005
KS8995XA
Address 9 8 7 6 5 4 3 2 1 0 Name Restart AN Force full-duplex Collision test Reserved Reserved Force MDI Disable auto MDIX Disable far end fault Disable transmit Disable LED 1 = force MDI. 0 = normal operation. 1 = disable auto MDI-X. 0 = normal operation. 1 = disable far end fault detection. 0 = normal operation. 1 = disable transmit. 0 = normal operation. 1 = disable LED. 0 = normal operation. Description 1 = restart auto-negotiation. 0 = normal operation. 1 = full-duplex. 0 = half-duplex. Not supported. Mode R/W R/W RO RO RO R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0
Micrel, Inc.
Register 1: MII Status 15 14 13 12 11 10-7 6 5 4 3 2 1 0 T4 capable 100 Full capable 100 Half capable 10 Full capable 10 Half capable Reserved Preamble suppressed AN complete Far end fault AN capable Link status Jabber test Extended capable Not supported. 1 = auto-negotiation complete. 0 = auto-negotiation not completed. 1 = far end fault detected. 0 = no far end fault detected. 1 = auto-negotiation capable. 0 = not auto-negotiation capable. 1 = link is up. 0 = link is down. Not supported. 0 = not extended register capable. 0 = not 100 BASET4 capable. 1 = 100BASE-TX full-duplex capable. 0 = not capable of 100BASE-TX full-duplex. 1 = 100BASE-TX half-duplex capable. 0 = not 100BASE-TX half-duplex capable. 1 = 10BASE-T full-duplex capable. 0 = not 10BASE-T full-duplex capable. 1 = 10BASE-T half-duplex capable. 0 = not 10BASE-T half-duplex capable. RO RO RO RO RO RO RO RO RO RO RO RO RO 0 1 1 1 1 0 0 0 0 1 0 0 0
Register 2: PHYID HIGH 15-0 Phyid high High order PHYID bits. RO 0x0022
Register 3: PHYID LOW 15-0 Phyid low Low order PHYID bits. RO 0x1450
Register 4: Advertisement Ability 15 14 13 12-11 Next page Reserved Remote fault Reserved Not supported. Not supported. RO RO RO RO 0 0 0 0 M9999-051305
May 2005
41
KS8995XA
Address 10 9 8 7 6 5 4-0 Name Pause Reserved Adv 100 Full Adv 100 Half Adv 10 Full Adv 10 Half Selector field 1 = advertise 100 full-duplex ability. 0 = do not advertise 100 full-duplex ability. 1 = advertise 100 half-duplex ability. 0 = do not advertise 100 half-duplex ability. 1 = advertise 10 full-duplex ability. 0 = do not advertise 10 full-duplex ability. 1 = advertise 10 half-duplex ability. 0 = do not advertise 10 half-duplex ability. 802.3 Description 1 = advertise pause ability. 0 = do not advertise pause ability. Mode R/W R/W R/W R/W R/W R/W RO Default 1 0 1 1 1 1 00001
Micrel, Inc.
Register 5: Link Partner Ability 15 14 13 12-11 10 9 8 7 6 5 4-0 Next page LP ACK Remote fault Reserved Pause Reserved Adv 100 full Adv 100 half Adv 10 full Adv 10 half Reserved Link partner 100 full capability. Link partner 100 half capability. Link partner 10 full capability. Link partner 10 half capability. Link partner pause capability. Not supported. Not supported. Not supported. RO RO RO RO RO RO RO RO RO RO RO 0 0 0 0 0 0 0 0 0 0 00000
M9999-051305
42
May 2005
KS8995XA
Micrel, Inc.
Absolute Maximum Ratings(1)
Supply Voltage (VDDAR, VDDAP, VDDC) ............................. -0.5V to +2.4V (VDDAT, VDDIO) ........................................ -0.5V to +4.0V Input Voltage (All Inputs) ............................. -0.5V to +4.0V Output Voltage (All Outputs) ....................... -0.5V to +4.0V Lead Temperature (soldering, 10 sec.) ..................... 270C Storage Temperature (TS) ....................... -55C to +150C
Operating Ratings(2)
Supply Voltage (VDDAR, VDDAP, VDDC) ............................. +1.7V to +1.9V (VDDAT) ................... +3.15V to +3.45V or +2.4V to +2.6V (VDDIO) ................................................ +3.15V to +3.45V Ambient Temperature (TA) Commercial .............................................. -0C to +70C Package Thermal Resistance(3) PQFP (JA) No Air Flow ................................. 42.91C/W
Electrical Characteristics(4, 5)
Symbol Parameter Condition Min Typ Max Units 100BASE-TX Operation -- All Ports 100% Utilization IDDC IDDIO IDDC IDDIO IDDC IDDIO TTL Inputs VIH VIL IIN TTL Outputs VOH VOL |IOZ| VO VIMB tr, tt Output High Voltage Output Low Voltage Output Tri-State Leakage IOH = -8mA IOL = 8mA +2.4 +0.4 10 V V A Input High Voltage Input Low Voltage Input Current (Excluding Pull-up/Pull-down) VIN = GND ~ VDDIO -10 +2.0 +0.8 10 V V A 100BASE-TX (Digital Core/PLL + Analog RX) VDDC, VDDAP, VDDAR 194 223 206 226 mA mA
100BASE-TX (Digital IO + Transmitter) VDDIO, VDDAT 10BASE-TX Operation -- All Ports 100% Utilization 10BASE-TX (Digital Core + Analog RX) 10BASE-TX (Digital IO + Transmitter) VDDC, VDDAP VDDIO, VDDAT
152 336
161 347
mA mA
Auto-Negotiation Mode 10BASE-TX (Digital Core + Analog RX) VDDC, VDDAP 10BASE-TX (Digital IO + Transmitter) VDDIO, VDDAT 137 21 146 23 mA mA
100BASE-TX Transmit (measured differentially after 1:1 transformer) Peak Differential Output Voltage Output Voltage Imbalance Rise/Fall Time Rise/Fall Time Imbalance
Notes: 1. Exceeding the absolute maximum rating may damage the device. 2. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level (ground to VDD). 3. No heat spreader in package. 4. Specification for packaged product only. 5. Measurements were taken with operating ratings.
100 termination on the differential output 100 termination on the differential output
0.95
1.05 2
V % ns ns
3 0
5 0.5
May 2005
43
M9999-051305
KS8995XA
Symbol Parameter Condition Min Typ
Micrel, Inc.
Max Units
100BASE-TX Transmit (measured differentially after 1:1 transformer) Duty Cycle Distortion Overshoot VSET Reference Voltage of ISET Output Jitters 10BASE-T Receive VSQ VP Squelch Threshold 5MHz square wave 400 mV Peak-to-peak 0.5 0.7 1.4 0.5 5 ns % V ns
10BASE-T Transmit (measured differentially after 1:1 transformer) VDDAT = 2.5V Peak Differential Output Voltage Jitters Added Rise/Fall Times 100 termination on the differential output 100 termination on the differential output 28 2.3 16 30 V ns ns
M9999-051305
44
May 2005
KS8995XA
Micrel, Inc.
Timing Diagrams
ts1 Receive Timing tcyc1 th1
SCL SDA
Figure 11. EEPROM Interface Input Receive Timing Diagram
tcyc1 Transmit Timing
SCL SDA
tov1
Figure 12. EEPROM Interface Output Transmit Timing Diagram
Symbol tCYC1 tS1 tH1 tOV1
Parameter Clock Cycle Set-Up Time Hold Time Output Valid
Min
Typ 16384
Max
Units ns ns ns
20 20 4096 4112 4128
ns
Table 7. EEPROM Timing Parameters
May 2005
45
M9999-051305
KS8995XA
Micrel, Inc.
ts2 Receive Timing
tcyc2
th2
MTXC MTXEN
MTXD[0]
Figure 13. SNI Input Timing
tcyc2 Transmit Timing
MRXC MRXDV MCOL MRXD[0]
tov2
Figure 14. SNI Output Timing
Symbol tCYC2 tS2 tH2 tO2
Parameter Clock Cycle Set-Up Time Hold Time Output Valid
Min
Typ 100
Max
Units ns ns ns
10 0 0 3 6
ns
Table 8. SNI Timing Parameters
M9999-051305
46
May 2005
KS8995XA
Micrel, Inc.
ts3 Receive Timing
tcyc3
th3
MRXCLK MTXEN MTXER MTXD[3:0]
Figure 15. MAC Mode MII Timing - Data Received from MII
tcyc3 Transmit Timing
MTXCLK MRXDV
tov3
MRXD[3:0]
Figure 16. MAC Mode MII Timing - Data Transmitted from MII
Symbol tCYC3 tCYC3 tS3 tH3 tOV3
Parameter Clock Cycle (100BASE-T) Clock Cycle (10BASE-T) Set-Up Time Hold Time Output Valid
Min
Typ 40 400
Max
Units ns ns ns ns
10 5 7 11 16
ns
Table 9. MAC Mode MII Timing Parameters
May 2005
47
M9999-051305
KS8995XA
Micrel, Inc.
ts4 Receive Timing
tcyc4
th4
MTXCLK MTXEN MTXER MTXD[3:0]
Figure 17. PHY Mode MII Timing - Data Received from MII
tcyc4 Transmit Timing
MRXCLK MRXDV
tov4
MRXD[3:0]
Figure 18. PHY Mode MII Timing - Data Transmitted from MII
Symbol tCYC4 tCYC4 tS4 tH4 tOV4
Parameter Clock Cycle (100BASE-T) Clock Cycle (10BASE-T) Set-Up Time Hold Time Output Valid
Min
Typ 40 400
Max
Units ns ns ns ns
10 0 18 25 28
ns
Table 10. PHY Mode MII Timing Parameters
M9999-051305
48
May 2005
KS8995XA
Micrel, Inc.
Supply Voltage tsr
RST_N tcs tch
Strap-In Value trc Strap-In / Output Pin
Figure 19. Reset Timing
Symbol tSR tCS tCH tRC
Parameter Stable Supply Voltages to Reset High Configuration Set-Up Time Configuration Hold Time Reset to Strap-In Pin Output
Min 10 50 50 50
Typ
Max
Units ms ns ns ns
Table 11. Reset Timing Parameters
Reset Circuit Diagram
Micrel recommendeds the following discrete reset circuit as shown in Figure 20 when powering up the KS8895XA device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend the reset circuit as shown in Figure 21.
VCC
D1 KS8995X RST C 10F
R 10k
CPU/FPGA RST_OUT_n D2
D1, D2: 1N4148
Figure 20. Recommended Reset Circuit.
VCC D1: 1N4148 D1 KS8995X RST C 10F R 10k
Figure 21. Recommended Circuit for Interfacing with CPU/FPGA Reset At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out from CPU/FPGA provides warm reset after power up. It is also recommended to power up the VDD core voltage earlier than VDDIO voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same time. May 2005 49
M9999-051305
KS8995XA
Micrel, Inc.
Selection of Isolation Transformer(1)
One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics.
Characteristics Name Turns Ratio Open-Circuit Inductance (min.) Leakage Inductance (max.) Inter-Winding Capacitance (max.) D.C. Resistance (max.) Insertion Loss (max.) HIPOT (min.) Value 1 CT : 1 CT 350H 0.4H 12pF 0.9 1.0dB 1500Vrms 0MHz to 65MHz 100mV, 100kHz, 8mA 1MHz (min.) Test Condition
Note: 1. The IEEE 802.3u standard for 100BASE-TX assumes a transformer loss of 0.5dB. For the transmit line transformer, insertion loss of up to 1.3dB can be compensated by increasing the line drive current by means of reducing the ISET resistor value.
The following transformer vendors provide compatible magnetic parts for Micrel's device:
4-Port Integrated Vendor Part Pulse Bel Fuse YCL Transpower Delta LanKom H1164 558-5999-Q9 PH406466 HB826-2 LF8731 SQ-H48W Auto MDIX Yes Yes Yes Yes Yes Yes Number of Ports 4 4 4 4 4 4 Single-Port Vendor Pulse Bel Fuse YCL Transpower Delta LanKom Part H1102 S558-5999-U7 PT163020 HB726 LF8505 LF-H41S Auto MDIX Yes Yes Yes Yes Yes Yes Number of Ports 1 1 1 1 1 1
Table 12. Qualified Magnetics Lists
M9999-051305
50
May 2005
KS8995XA
Micrel, Inc.
Package Information
128-Pin PQFP (PQ) MICREL INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
This information furnished by Micrel in this data sheet is believed to be accurate and reliable. However no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2003 Micrel, Incorporated.
May 2005
51
M9999-051305

▲Up To Search▲

Price & Availability of KSZ8995XA

	To Download KSZ8995XA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .