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8051 Embedded Monitor Controller Flash Type with ISP 4U t
GENERAL DESCRIPTIONS The MTV312M micro-controller is an 8051 CPU core embedded device especially tailored for CRT/LCD Monitor applications. It includes an 8051 CPU core, 1024-byte SRAM, 14 built-in PWM DACs, VESA DDC interface, 4-channel A/D converter, and a 64Kbyte internal program Flash-ROM.
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MTV312M64
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BLOCK DIAGRAM
P1.0-7 P3.0-2 P3.4-5
P0.0-7 P2.0-3 RD WR ALE INT1
8051 CORE
RST X1 X2
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P6.0-7 P5.0-6 P4.0-2
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FEATURES * 8051 core, 12MHz operating frequency with double CPU clock option * 0.35um process; 5V/3.3V power supply and I/O; 3.3V core operating * 1024-byte RAM; 64K-byte program Flash-ROM support In System Programming (ISP) * Maximum 14 channels of PWM DAC * Maximum 31 I/O pins * SYNC processor for composite separation/insertion, H/V polarity/frequency check and polarity adjustment * Built-in low power reset circuit * Built-in self-test pattern generator with four freerunning timings * Compliant with VESA DDC1/2B/2Bi/2B+ standard * Dual slave IIC addresses; H/W auto transfer DDC1/DDC2x data * Single master IIC interface for internal device communication * Maximum 4-channel 6-bit ADC * Watchdog timer with programmable interval * Flash-ROM program code protection selection * 40-pin DIP, 42-pin SDIP or 44-pin PLCC package
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RD WR ALE INT1
XFR
AUXRAM & DDCRAM
AD0-3
ADC
H/VSYNC CONTROL
HSYNC VSYNC HBLANK VBLANK ISCL ISDA HSCL HSDA
PWM DAC AUX I/O
DA0-13
DDC & IIC INTERFACE
Myson Century, Inc. Taiwan: No. 2, Industry East Rd. III, Science-Based Industrial Park, Hsin-Chu, Taiwan Tel: 886-3-5784866 Fax: 886-3-5784349
USA: 4020 Moorpark Avenue Suite 115 San Jose, CA, 95117 Tel: 408-243-8388 Fax: 408-243-3188
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sales@myson.com.tw www.myson.com.tw Rev. 1.2 March 2003 page 1 of 34
MTV312M64
PIN CONNECTION
DA2/P5.2 DA1/P5.1 DA0/P5.0 VDD3 VDD VSS X2 X1 ISDA/P3.4/T0 ISCL/P3.5/T1 STOUT/P4.2 P6.2/AD2/HLFHI P1.0 P1.1 P3.2/INT0 P1.2 P1.3 P1.4 P1.5 P1.6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33
VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5.5 DA8/HLFHO DA9/HALFV HBLANK/P4.1 VBLANK/P4.0 DA7/HCLAMP DA6/P5.6 RST P6.6/DA12 P6.5/DA11 P6.4/DA10 HSCL/P3.0/Rxd HSDA/P3.1/Txd P6.0/AD0 P6.1/AD1 P1.7
DA2/P5.2 DA1/P5.1 DA0/P5.0 VDD3 NC NC RST VDD VSS X2 X1 ISDA/P3.4/T0 ISCL/P3.5/T1 STOUT/P4.2 P6.2/AD2/HLFHI P1.0 P1.1 P3.2/INT0 P1.2 P1.3 P1.4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35
VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5.5 DA8/HLFHO DA9/HALFV HBLANK/P4.1 VBLANK/P4.0 DA7/HCLAMP DA6/P5.6 P6.6/DA12 P6.5/DA11 P6.4/DA10 HSCL/P3.0/Rxd HSDA/P3.1/Txd P6.0/AD0 P6.1/AD1 P1.7 P1.6 P1.5
MTV312MN 40-pin PDIP
32 31 30 29 28 27 26 25 24 23 22 21
MTV312MS 42-pin SDIP
34 33 32 31 30 29 28 27 26 25 24 23 22
DA0/P5.0
DA2/P5.2 DA1/P5.1
DA3/P5.3 HSYNC
DA4/P5.4
DA5/P5.5
VSYNC
VDD3 4
NC 6 RST VDD P6.3/AD3 VSS X2 X1 ISDA/P3.4/T0 ISCL/P3.5/T1 STOUT/P4.2 P6.2/AD2/HLFHI P1.0 7 8 9 10 11 12 13 14 15 16 17 18 P1.1
NC 5 19 P3.2/INT0
3 21 P1.3
MTV312MV 44-pin PLCC
2 22 P1.4
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44
43
42
41
40 39 38 37 36 35 34 33 32 31 30 29 DA8/HLFHO DA9/HALFV HBLANK/P4.1 VBLANK/P4.0 DA7/HCLAMP DA6/P5.6 P6.7/DA13 P6.6/DA12 P6.5/DA11 P6.4/DA10 HSCL/P3.0/Rxd
20 P1.2
23 P1.5
24 P1.6
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26
27 P6.0/AD0
28 HSDA/P3.1/Txd
P6.1/AD1 P1.7
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MTV312M64
PIN CONFIGURATION A "CMOS output pin" means it can sink and drive at least 4mA current. It is not recommended to use such pin as input function. A "open drain pin" means it can sink at least 4mA current but only drive 10~20uA to VDD. It can be used as input or output function and needs an external pull up resistor. A "8051 standard pin" is a pseudo open drain pin. It can sink at least 4mA current when output is at low level, and drives at least 4mA current for 160nS when output transits from low to high, then keeps driving at 100uA to maintain the pin at high level. It can be used as input or output function. It needs an external pull up resistor when driving heavy load device.
4mA
10uA
120uA
2 OSC period delay 4mA Output Data Input Data
Pin
8051 Standard Pin
4mA No Current
Output Data 4mA
Pin
Input Data 4mA Output Data
Pin
CMOS Output Pin
Open Drain Pin
POWER CONFIGURATION The MTV312M can work on 5V or 3.3V power supply system. In 5V power system, the VDD pin is connected to 5V power and the VDD3 needs an external capacitor, all output pins can swing from 0~5V, input pins can accept 0~5V input range. And ADC conversion range is 5V. However, X1 and X2 pins must be kept below 3.3V. In 3.3V power system, the VDD and VDD3 are connected to 3.3V power, all output pins swing from 0~3.3V, HSYNC, VSYNC and open drain pin can accept 0~5V input range, other pins must be kept below 3.3V. And the ADC conversion range is 3.3V.
5V VDD VDD3 10u 3.3V VDD VDD3
MTV312M in 5V System
MTV312M in 3.3V System
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MTV312M64
PIN DESCRIPTION
Name VDD3 VDD VSS X2 X1 RST DA0/P5.0 DA1/P5.1 DA2/P5.2 DA3/P5.3 DA4/P5.4 DA5/P5.5 DA6/P5.6 DA7/HCLAMP DA8/HLFHO DA9/HALFV HSCL/P3.0/Rxd HSDA/P3.1/Txd P3.2/INT0 ISDA/P3.4/T0 ISCL/P3.5/T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P6.0/AD0 P6.1/AD1 P6.2/AD2/HLFHI P6.3/AD3 P6.4/DA10 P6.5/DA11 P6.6/DA12 P6.7/DA13 VBLANK/P4.0 PIN NO. 40 4 5 6 7 8 29 3 2 1 38 37 36 30 31 35 34 25 24 15 9 10 13 14 16 17 18 19 20 21 23 22 12 26 27 28 32 42 4 8 9 10 11 7 3 2 1 40 39 38 32 33 37 36 28 27 18 12 13 16 17 19 20 21 22 23 24 26 25 15 29 30 31 34 44 4 8 10 11 12 7 3 2 1 42 41 40 34 35 39 38 29 28 19 13 14 17 18 20 21 22 23 24 25 27 26 16 9 30 31 32 33 36 Type O O I I I/O I/O I/O I/O I/O I/O I/O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O 3.3V core power 5V or 3.3V Positive Power Supply Ground Oscillator output Oscillator input Active high reset PWM DAC output / General purpose I/O (CMOS) PWM DAC output / General purpose I/O (CMOS) PWM DAC output / General purpose I/O (CMOS) PWM DAC output / General purpose I/O (CMOS) PWM DAC output / General purpose I/O (CMOS) PWM DAC output / General purpose I/O (CMOS) PWM DAC output / General purpose I/O (CMOS) PWM DAC output / Hsync clamp pulse output (CMOS) PWM DAC output / Hsync half freq. Output (open drain) PWM DAC output / Vsync half freq. Output (open drain) Slave IIC clock / General purpose I/O / Rxd (open drain) Slave IIC data / General purpose I/O / Txd (open drain) General purpose I/O / INT0 (8051 standard) Master IIC data / General purpose I/O / T0 (open drain) Master IIC clock / General purpose I/O / T1 (open drain) General purpose I/O (CMOS output or 8051 standard) General purpose I/O (CMOS output or 8051 standard) General purpose I/O (CMOS output or 8051 standard) General purpose I/O (CMOS output or 8051 standard) General purpose I/O (CMOS output or 8051 standard) General purpose I/O (CMOS output or 8051 standard) General purpose I/O (CMOS output or 8051 standard) General purpose I/O (CMOS output or 8051 standard) General purpose I/O / ADC Input (CMOS) General purpose I/O / ADC Input (CMOS) General purpose I/O / ADC Input / Half Hsync input (CMOS) General purpose I/O / ADC Input (CMOS) General purpose I/O / PWM DAC output (CMOS) General purpose I/O / PWM DAC output (CMOS) General purpose I/O / PWM DAC output (CMOS) General purpose I/O / PWM DAC output (CMOS) Vertical blank (CMOS) / General purpose Output (CMOS) Description
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MTV312M64
HBLANK/P4.1 STOUT/P4.2 HSYNC VSYNC 33 11 39 40 35 14 41 42 37 15 43 44 O O I I Horizontal blank (CMOS) / General purpose Output (CMOS) Self-test video output (CMOS) / General purpose Output (CMOS) Horizontal SYNC or Composite SYNC Input Vertical SYNC input
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MTV312M64
FUNCTIONAL DESCRIPTIONS 8051 CPU Core The CPU core of MTV312M is compatible with the industry standard 8051, which includes 256 bytes RAM, Special Function Registers (SFR), two timers, five interrupt sources and a serial interface. The CPU core fetches its program code from the 64K bytes Flash in MTV312M. It uses Port0 and Port2 to access the "external special function register" (XFR) and external auxiliary RAM (AUXRAM). The CPU core can run at double rate when FclkE is set. Once the bit is set, the CPU runs as if a 24MHz X'tal is applied on MTV312M, but the peripherals (IIC, DDC, H/V processor) still run at the original frequency. Note: All registers listed in this document reside in 8051's external RAM area (XFR). For internal RAM memory map, please refer to 8051 spec. Memory Allocation i) Internal Special Function Registers (SFR) The SFR is a group of registers that are the same as standard 8051. ii) Internal RAM There are total 256 bytes internal RAM in MTV312M, the same as standard 8052. iii) External Special Function Registers (XFR) The XFR is a group of registers allocated in the 8051 external RAM area F00h - FFFh. These registers are used for special functions. Programs can use "MOVX" instruction to access these registers. iv) Auxiliary RAM (AUXRAM) There are total 512 bytes auxiliary RAM allocated in the 8051 external RAM area 800h - 9FFh. Programs can use "MOVX" instruction to access the AUXRAM. v) Dual Port RAM (DDCRAM)
There are 256 bytes Dual Port RAM allocated in the 8051 external RAM area E00h - EFFh. Programs can use "MOVX" instruction to access the RAM. The external DDC1/2 Host can access the RAM as if a 24LC02 EEPROM is connected onto the interface.
FFh
Internal RAM
Accessible by indirect addressing only (Using MOV A,@Ri instruction)
SFR
Accessible by direct addressing
FFFh
XFR
Accessible by indirect external RAM addressing (Using MOVX instruction)
EFFh
DDCRAM
Accessible by indirect external RAM addressing (Using MOVX instruction)
80h 7Fh
F00h
Internal RAM
Accessible by direct and indirect addressing
E00h 9FFh
AUXRAM
Accessible by indirect external RAM addressing (Using MOVX instruction
00h
800h
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MTV312M64
Chip Configuration The Chip Configuration registers define configuration of the chip and function of the pins.
Reg name PADMOD PADMOD PADMOD PADMOD PADMOD PADMOD OPTION addr F50h(w) F51h(w) F52h(w) F53h(w) F54h(w) F55h(w) F56h(w) P67oe COP17 PWMF HIICE bit7 DA13E bit6 DA12E P56E IIICE P56oe P66oe COP16 DIV253 bit5 DA11E P55E HLFVE P55oe P65oe COP15 FclkE Bit4 DA10E P54E HLFHE P54oe P64oe COP14 bit3 AD3E P53E HCLPE P53oe P63oe COP13 ENSCL bit2 AD2E P52E P42E P52oe P62oe COP12 Msel bit1 AD1E P51E P41E P51oe P61oe COP11 MIICF1 bit0 AD0E P50E P40E P50oe P60oe COP10 MIICF0
PADMOD (w) : Pad mode control registers. (All are "0" in Chip Reset) DA13E = 1 =0 DA12E = 1 =0 DA11E = 1 =0 DA10E = 1 =0 AD3E = 1 =0 AD2E = 1 =0 AD1E = 1 =0 AD0E = 1 =0 P56E P55E P54E P53E P52E P51E P50E =1 =0 =1 =0 =1 =0 =1 =0 =1 =0 =1 =0 =1 =0 HIICE = 1 Pin "P6.7/DA13" is DA13. Pin "P6.7/DA13" is P6.7. Pin "P6.6/DA12" is DA12. Pin "P6.6/DA12" is P6.6. Pin "P6.5/DA11" is DA11. Pin "P6.5/DA11" is P6.5. Pin "P6.4/DA10" is DA10. Pin "P6.4/DA10" is P6.4. Pin "P6.3/AD3" is AD3. Pin "P6.3/AD3" is P6.3. Pin "P6.2/AD2" is AD2. Pin "P6.2/AD2" is P6.2. Pin "P6.1/AD1" is AD1. Pin "P6.1/AD1" is P6.1. Pin "P6.0/AD0" is AD0. Pin "P6.0/AD0" is P6.0. Pin "DA6/P5.6" is P5.6. Pin "DA6/P5.6" is DA6. Pin "DA5/P5.5" is P5.5. Pin "DA5/P5.5" is DA5. Pin "DA4/P5.4" is P5.4. Pin "DA4/P5.4" is DA4. Pin "DA3/P5.3" is P5.3. Pin "DA3/P5.3" is DA3. Pin "DA2/P5.2" is P5.2. Pin "DA2/P5.2" is DA2. Pin "DA1/P5.1" is P5.1. Pin "DA1/P5.1" is DA1. Pin "DA0/P5.0" is P5.0. Pin "DA0/P5.0" is DA0. Pin "HSCL/P3.0/Rxd" is HSCL; pin "HSDA/P3.1/Txd" is HSDA.
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MTV312M64
=0 IIICE =1 =0 HLFVE = 1 =0 HLFHE = 1 =0 HCLPE = 1 =0 P42E P41E P40E =1 =0 =1 =0 =1 =0 P56oe = 1 =0 P55oe = 1 =0 P54oe = 1 =0 P53oe = 1 =0 P52oe = 1 =0 P51oe = 1 =0 P50oe = 1 =0 P67oe = 1 =0 P66oe = 1 =0 P65oe = 1 =0 P64oe = 1 =0 P63oe = 1 =0 P62oe = 1 =0 P61oe = 1 =0 Pin "HSCL/P3.0/Rxd" is P3.0/Rxd; Pin "ISDA/P3.4/T0" is ISDA; Pin "ISDA/P3.4/T0" is P3.4/T0; Pin "DA9/HALFV" is DA9. Pin "DA8/HALFH" is HSYNC half frequency output. Pin "DA8/HALFH" is DA8. Pin "DA7/HCLAMP" is HSYNC clamp pulse output. Pin "DA7/HCLAMP" is DA7. Pin "STOUT/P4.2" is P4.2. Pin "STOUT/P4.2" is STOUT. Pin "HBLANK/P4.1" is P4.1. Pin "HBLANK/P4.1" is HBLANK. Pin "VBLANK/P4.0" is P4.0. Pin "VBLANK/P4.0" is VBLANK. P5.6 is output pin. P5.6 is input pin. P5.5 is output pin. P5.5 is input pin. P5.4 is output pin. P5.4 is input pin. P5.3 is output pin. P5.3 is input pin. P5.2 is output pin. P5.2 is input pin. P5.1 is output pin. P5.1 is input pin. P5.0 is output pin. P5.0 is input pin. P6.7 is output pin. P6.7 is input pin. P6.6 is output pin. P6.6 is input pin. P6.5 is output pin. P6.5 is input pin. P6.4 is output pin. P6.4 is input pin. P6.3 is output pin. P6.3 is input pin. P6.2 is output pin. P6.2 is input pin. P6.1 is output pin. P6.1 is input pin.
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pin "HSDA/P3.1/Txd" is P3.1/Txd. pin "ISCL/P3.5/T1" is ISCL. pin "ISCL/P3.5/T1" is P3.5/T1.
Pin "DA9/HALFV" is VSYNC half frequency output.
MTV312M64
P60oe = 1 =0 COP17 = 1 =0 COP16 = 1 =0 COP15 = 1 =0 COP14 = 1 =0 COP13 = 1 =0 COP12 = 1 =0 COP11 = 1 =0 COP10 = 1 =0 OPTION (w) : P6.0 is output pin. P6.0 is input pin. Pin "P1.7" is CMOS Output. Pin "P1.7" is 8051 standard I/O. Pin "P1.6" is CMOS Output. Pin "P1.6" is 8051 standard I/O. Pin "P1.5" is CMOS Output. Pin "P1.5" is 8051 standard I/O. Pin "P1.4" is CMOS Output. Pin "P1.4" is 8051 standard I/O. Pin "P1.3" is CMOS Output. Pin "P1.3" is 8051 standard I/O. Pin "P1.2" is CMOS Output. Pin "P1.2" is 8051 standard I/O. Pin "P1.1" is CMOS Output. Pin "P1.1" is 8051 standard I/O. Pin "P1.0" is CMOS Output. Pin "P1.0" is 8051 standard I/O.
Chip option configuration (All are "0" in Chip Reset). Selects 94KHz PWM frequency. Selects 47KHz PWM frequency. PWM pulse width is 253-step resolution. PWM pulse width is 256-step resolution. CPU is running at double rate CPU is running at normal rate Enable slave IIC block to hold HSCL pin low while MTV312M64 is unable to catch-up with the external master's speed. Master IIC block connect to HSCL/HSDA pins. Master IIC block connect to ISCL/ISDA pins. Selects 400KHz Master IIC frequency. Selects 200KHz Master IIC frequency. Selects 50KHz Master IIC frequency. Selects 100KHz Master IIC frequency. =0
PWMF = 1 DIV253 = 1 =0 FclkE =1 =0 ENSCL = 1 Msel =1 =0 = 1,0 = 0,1 = 0,0 I/O Ports i) Port1
MIICF1,MIICF0 = 1,1
Port1 is a group of pseudo open drain pins or CMOS output pins. It can be used as general purpose I/O. Behavior of Port1 is the same as standard 8051. ii) P3.0-2, P3.4-5 If these pins are not set as IIC pins, Port3 can be used as general purpose I/O, interrupt, UART and Timer pins. Behavior of Port3 is the same as standard 8051.
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MTV312M64
iii) Port4, Port5 and Port6 Port5 and Port6 are used as general purpose I/O. S/W needs to set the corresponding P5(n)oe and P6(n)oe to define whether these pins are input or output. Port4 is pure output.
Reg name PORT5 PORT5 PORT5 PORT5 PORT5 PORT5 PORT5 PORT6 PORT6 PORT6 PORT6 PORT6 PORT6 PORT6 PORT6 PORT4 PORT4 PORT4 addr F30h(r/w) F31h(r/w) F32h(r/w) F33h(r/w) F34h(r/w) F35h(r/w) F36h(r/w) F38h(r/w) F39h(r/w) F3Ah(r/w) F3Bh(r/w) F3Ch(r/w) F3Dh(r/w) F3Eh(r/w) F3Fh(r/w) F58h(w) F59h(w) F5Ah(w) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P50 P51 P52 P53 P54 P55 P56 P60 P61 P62 P63 P64 P65 P66 P67 P40 P41 P42
PORT5 (r/w) : PORT6 (r/w) : PORT4 (w) : PWM DAC
Port 5 data input/output value. Port 6 data input/output value. Port 4 data output value.
Each output pulse width of PWM DAC converter is controlled by an 8-bit register in XFR. The frequency of PWM clock is 47KHz or 94KHz, selected by PWMF. And the total duty cycle step of these DAC outputs is 253 or 256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to DAC register generates stable high output. If DIV253=0, the output pulses low at least once even if the DAC register's content is FFH. Writing 00H to DAC register generates stable low output.
Reg name DA0 DA1 DA2 DA3 DA4 DA5 DA6 addr F20h(r/w) F21h(r/w) F22h(r/w) F23h(r/w) F24h(r/w) F25h(r/w) F26h(r/w) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Pulse width of PWM DAC 0 Pulse width of PWM DAC 1 Pulse width of PWM DAC 2 Pulse width of PWM DAC 3 Pulse width of PWM DAC 4 Pulse width of PWM DAC 5 Pulse width of PWM DAC 6
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MTV312M64
DA7 DA8 DA9 DA10 DA11 DA12 DA13 F27h(r/w) F28h(r/w) F29h(r/w) F2Ah(r/w) F2Bh(r/w) F2Ch(r/w) F2Dh(r/w) Pulse width of PWM DAC 7 Pulse width of PWM DAC 8 Pulse width of PWM DAC 9 Pulse width of PWM DAC 10 Pulse width of PWM DAC 11 Pulse width of PWM DAC 12 Pulse width of PWM DAC 13
DA0-13 (r/w) : The output pulse width control for DA0-13. * All of PWM DAC converters are centered with value 80h after power on. H/V SYNC Processing The H/V SYNC processing block performs the functions of composite signal separation/insertion. SYNC inputs presence check, frequency counting, polarity detection and control, as well as the protection of VBLANK output while VSYNC speeds up in high DDC communication clock rate. Based on the digital filter, the HSYNC present and frequency function block treat any pulse longer than the specified time period as pulse, and the specified time period is controlled by (DF1,DF0) bits. The VSYNC digital filter has no control bit. It works as (DF1,DF0) = (0, 0) of HSYNC.
Digital Filter
Present Check
Vpre
Polarity Check & Freq. Count VSYNC CVSYNC
Vfreq Vpol Vbpl
XOR Vself Present Check CVpre XOR VBLANK
Digital Filter
Polarity Check & Sync Seperator Present Check & Freq. Count
Hpol Hpre Hfreq Hbpl XOR Hself XOR HBLANK
Composite Pulse Insert HSYNC
H/V SYNC Processor Block Diagram
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MTV312M64
i) Composite SYNC separation/insertion The MTV312M continuously monitors the input HSYNC. If the vertical SYNC pulse can be extracted from the input, a CVpre flag is set and users can select the extracted "CVSYNC" for the source of polarity check, frequency count, and VBLANK output. The CVSYNC then has 8us delay compared to the original signal. The MTV312M can also insert pulse to HBLANK output during composite VSYNC's active time. The width of insert pulse is 1/8 HSYNC period and the insertion frequency can adapt to original HSYNC. The insert pulse of HBLANK can be disabled or enabled by setting "NoHins" control bit. If "NoHins" bit is set to "1", HBLANK output will be same as HSYNC input (of course, polarity can be controlled by HBpl bit). ii) H/V Frequency Counter MTV312M can discriminate HSYNC/VSYNC frequency and save the information in XFRs. The 14-bit Hcounter counts the time of 64xHSYNC period, then loads the result into the HCNTH/HCNTL latch. The output value is then [(128000000/H-Freq) - 1], updated once per VSYNC/CVSYNC period when VSYNC/CVSYNC is present or continuously updated when VSYNC/CVSYNC is non-present. The 12-bit Vcounter counts the time between two VSYNC pulses, then loads the result into the VCNTH/VCNTL latch. The output value is then (62500/V-Freq), updated every VSYNC/CVSYNC period. An extra overflow bit indicates the condition of H/V counter overflow. The VFchg/HFchg interrupt is set when VCNT/HCNT value changes or overflows. Table 6.2.1 and Table 6.2.2 show the HCNT/VCNT value under the operations of 12MHz.
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MTV312M64
HSYNC VSYNC H+V
Insert HSYNC pulse
EXTRHS
8us 1/8 HSYNC period
EXTRVS
8us
HSYNC VSYNC H XOR V
Insert HSYNC pulse
EXTRHS
8us 1/8 HSYNC period
EXTRVS
8us
HSYNC VSYNC SERR
Insert HSYNC pulse
EXTRHS
8us 1/8 HSYNC period
EXTRVS
8us
Timing Relationship of Composite SYNC signal Separation/Insertion when "NoHins" = 0
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MTV312M64
H-Freq(KHZ) 1 2 3 4 5 6 7 8 9 10 11 12 31.5 37.5 43.3 46.9 53.7 60.0 68.7 75.0 80.0 85.9 93.8 106.3 0FDEh / 4062 0D54h / 3412 0B8Bh / 2955 0AA8h / 2728 094Fh / 2383 0854h / 2132 0746h / 1862 06AAh / 1706 063Fh / 1599 05D1h / 1489 0554h / 1364 04B3h / 1203 Output Value (14 bits) 12MHz OSC (hex / dec)
Table-1
V-Freq(Hz) 1 2 3 4 5 6 56 60 70 72 75 85 45Ch / 1116 411h / 1041 37Ch / 892 364h / 868 341h / 833 2DFh / 735
H-Freq Table
Output value (12bits) 12MHz OSC (hex / dec)
Table-2 iii) H/V Present Check
V-Freq Table
The Hpresent function checks the input HSYNC pulse, and the Hpre flag is set when HSYNC is over 10KHz or cleared when HSYNC is under 10Hz. The Vpresent function checks the input VSYNC pulse, and the Vpre flag is set when VSYNC is over 40Hz or cleared when VSYNC is under 10Hz. The HPRchg interrupt is set when the Hpre value changes. The VPRchg interrupt is set when the Vpre/CVpre value change. iv) H/V Polarity Detect
The polarity functions detect the input HSYNC/VSYNC high and low pulse duty cycle. If the high pulse duration is longer than that of the low pulse, the negative polarity is asserted; otherwise, positive polarity is asserted. The HPLchg interrupt is set when the Hpol value changes. The VPLchg interrupt is set when the Vpol value changes. v) Output HBLANK/VBLANK Control and Polarity Adjust
The HBLANK is the mux output of HSYNC, composite Hpulse and self-test horizontal pattern. The VBLANK is the mux output of VSYNC, CVSYNC and self-test vertical pattern. The mux selection and output polarity are S/W controllable. The VBLANK output is cut off when VSYNC frequency is over 250Hz.The HBLANK/VBLANK shares the output pin with P4.1/ P4.0.
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vi) Self Test Pattern Generator For testing purposes, this generator is able to generate 4 display patterns, namely positive cross-hatch, negative cross-hatch, full white, and full black (shown as figures below). The HBLANK output frequency of the pattern can be chosen to 95.2KHz, 63.5KHz, 47.6KHz and 31.75KHz or 86.95KHz, 80.0KHz, 74.0KHz and 68.96KHz. The VBLANK output frequency of the pattern is 72Hz and 60Hz or 82.2Hz, 75.6Hz, 70Hz and 65.2Hz. It is originally designed to support monitor manufacturer to do burn-in test, or offer end-user a reference to check the monitor. The output STOUT of the generator shares the output pin with P4.2.
Display Region
Positive cross-hatch
Negative cross-hatch
Full white
Full black
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MTV312M Self-Test Pattern Timing
63.5KHz, 60Hz Time Hor. Total time (A) Hor. Active time (D) Hor. F. P. (E) SYNC pulse width (B) Hor. B. P. (C) 15.75us 12.05us 0.2us 1.5us 2us Time Vert. Total time (O) Vert. Active time (R) Vert. F. P. (S) SYNC pulse width (P) Vert. B. P. (Q) 16.66ms 15.65ms 0.063ms 0.063ms 0.882ms H dots 1280 979.3 16.25 122 162.54 V lines 1024 962 3.87 3.87 54.2 47.6KHz, 60Hz Time 21.0us 16.07us 0.28us 2us 2.67us Time 16.66ms 15.65ms 0.063ms 0.063ms 0.882ms H dots 1024 783.2 12 90 110 V lines 768 721.5 2.9 2.9 40.5 31.7KHz, 60Hz Time 31.5us 24.05us 0.45us 3us 4us Time 16.66ms 15.65ms 0.063ms 0.063ms 0.882ms H dots 640 488.6 9 61 81.27 V lines 480 451 1.82 1.82 25.4 95.2KHz, 72Hz Time 10.5us 8.03us 0.14us 1.0us 1.33us Time 13.89ms 13.03ms 0.052ms 0.052ms 0.756ms H dots 1600 1224 21 152 203 V lines 1200 1126 4.5 4.5 65
MTV312M Self-Test Pattern Timing (Continue)
68.96KHz, 65.2Hz Time Hor. Total time (A) Hor. Active time (D) Hor. F. P. (E) SYNC pulse width (B) Hor. B. P. (C) 14.50us 10.71us 0.46us 1.33us 2us H dots 1280 945 41 117 177 74.0KHz, 70Hz Time 13.50us 10.04us 0.46us 1.17us 1.83us H dots 1280 952 44 111 173 80.0KHz, 75.6Hz Time 12.50us 9.37us 0.29us 1.17us 1.83us H dots 1600 1199 37 150 214 86.95KHz, 82.2Hz Time 11.50us 8.71us 0.29us 1.00us 1.50us H dots 1600 1212 40 139 209
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Time Vert. Total time (O) Vert. Active time (R) Vert. F. P. (S) SYNC pulse width (P) Vert. B. P. (Q) 15.34ms 14.41ms 0.058ms 0.058ms 0.812ms V lines 1024 962 3.87 3.87 54.2 Time 14.28ms 13.42ms 0.054ms 0.054ms 0.756ms V lines 1024 962 3.87 3.87 54.2 Time 13.23ms 12.43ms 0.050ms 0.050ms 0.700ms V lines 1200 1127 4.5 4.5 65 Time 12.17ms 11.43ms 0.048ms 0.048ms 0.644ms V lines 1200 1127 4.5 4.5 65
* 8 x 8 blocks of cross hatch pattern in display region. vii) HSYNC Clamp Pulse Output The HCLAMP output is activated by setting "HCLPE" control bit. The leading edge position, pulse width and polarity of HCLAMP are S/W controllable. viii) VSYNC Interrupt The MTV312M checks the VSYNC input pulse and generates an interrupt at its leading edge. The VSYNC flag is set each time when MTV312M detects a VSYNC pulse. The flag is cleared by S/W writing a "0". i) H/V SYNC Processor Register
Reg name HVSTUS HCNTH HCNTL VCNTH VCNTL HVCTR0 HVCTR2 HVCTR3 HVCTR4 INTFLG INTEN addr F40h(r) F41h(r) F42h(r) F43h(r) F44h(r) F40h(w) F42h(w) F43h(w) F44h(w) F48h(r/w) F49h(w) HPRchg EHPR VPRchg EVPR HPLchg EHPL VPLchg EVPL HFchg EHF VFchg EVF bit7 CVpre Hovf HF7 Vovf VF7 C1 VF6 C0 STF2 CLPEG VF5 NoHins Selft CLPPO VF4 SelExH STF1 CLPW2 HF6 bit6 bit5 Hpol HF13 HF5 bit4 Vpol HF12 HF4 bit3 Hpre HF11 HF3 VF11 VF3 IVHlfH STF0 CLPW1 bit2 Vpre HF10 HF2 VF10 VF2 HlfHE Rt1 CLPW0 DF1 DF0 Vsync EVsync bit1 Hoff HF9 HF1 VF9 VF1 HBpl Rt0 bit0 Voff HF8 HF0 VF8 VF0 VBpl
HVSTUS (r) :
The status of polarity, present and static level for HSYNC and VSYNC. The extracted CVSYNC is present. The extracted CVSYNC is not present. HSYNC input is positive polarity. HSYNC input is negative polarity. VSYNC (CVSYNC) is positive polarity. VSYNC (CVSYNC) is negative polarity. HSYNC input is present. HSYNC input is not present. VSYNC input is present. VSYNC input is not present. Off level of HSYNC input is high. Off level of HSYNC input is low.
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CVpre = 1 =0 Hpol Vpol Hpre Vpre Hoff* =1 =0 =1 =0 =1 =0 =1 =0 =1 =0
MTV312M64
Voff* =1 Off level of VSYNC input is high. =0 Off level of VSYNC input is low. *Hoff and Voff are valid when Hpre=0 or Vpre=0. HCNTH (r) : H-Freq counter's high bits. H-Freq counter is overflowed, this bit is cleared by H/W when condition removed. 6 high bits of H-Freq counter.
Hovf =1 HF13 - HF8 : HCNTL (r) : VCNTH (r) :
H-Freq counter's low byte. V-Freq counter's high bits. V-Freq counter is overflowed, this bit is cleared by H/W when condition removed. 4 high bits of V-Freq counter.
Vovf =1 VF11 - 8 : VCNTL (r) :
V-Freq counter's low byte.
HVCTR0 (w) : H/V SYNC processor control register 0. C1, C0 = 1,1 = 1,0 = 0,0 = 0,1 NoHins = 1 =0 SelExH = 1 =0 IVHlfH = 1 =0 HlfHE = 1 =0 HBpl VBpl =1 =0 =1 =0 Selects CVSYNC as the polarity, freq and VBLANK source. Selects VSYNC as the polarity, freq and VBLANK source. Disables composite function. H/W automatically switches to CVSYNC when CVpre=1 and VSpre=0. HBLANK has no insert pulse in composite mode. HBLANK has insert pulse in composite mode. Input source of HLFHO is HLFHI. Input source of HLFHO is HSYNC. HLFHO is inverted. HLFHO is not inverted. HLFHO is half freq. of HSYNC/HLFHI. HLFHO is same freq. of HSYNC/HLFHI. Negative polarity HBLANK output. Positive polarity HBLANK output. Negative polarity VBLANK output. Positive polarity VBLANK output.
HVCTR2 (w) : Self-test pattern generator control. Selft =1 =0 Enables generator. Disables generator. 95.2KHz (horizontal) / 72Hz (vertical) output selected.
STF2, STF1, STF0 = 0,1,1
= 0,1,0 63.5KHz (horizontal) / 60Hz (vertical) output selected. = 0,0,1 47.6KHz (horizontal) / 60Hz (vertical) output selected. = 0,0,0 31.75KHz (horizontal) / 60Hz (vertical) output selected. = 1,1,1 86.95KHz (horizontal) / 82.2Hz (vertical) output selected. = 1,1,0 80.0KHz (horizontal) / 75.6Hz (vertical) output selected. = 1,0,1 74.0KHz (horizontal) / 70Hz (vertical) output selected.
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= 1,0,0 68.96KHz (horizontal) / 65.2Hz (vertical) output selected. Rt1,Rt0 = 0,0 = 0,1 = 1,0 = 1,1 Positive cross-hatch pattern output. Negative cross-hatch pattern output. Full white pattern output. Full black pattern output.
HVCTR3 (w) : HSYNC clamp pulse control register. CLPEG = 1 =0 CLPPO = 1 Clamp pulse follows HSYNC leading edge. Clamp pulse follows HSYNC trailing edge. Positive polarity clamp pulse output.
=0 Negative polarity clamp pulse output. CLPW2 : CLPW0 : Pulse width of clamp pulse is [(CLPW2:CLPW0) + 1] x 0.167 s for 12MHz X'tal selection. HVCTR4 (w) : HSYNC digital filter control register. DF1, DF0 : = 0,0 The digital filter will treat any HSYNC pulse shorter than one OSC period (83.33ns) as noise, between one and two OSC period (83.33ns to 166.67ns) as unknown region, and longer than two OSC period (166.67ns) as pulse. = 0,1 The digital filter will treat any HSYNC pulse shorter than half OSC period (41.66ns) as noise, between half and one OSC period (41.66ns to 83.33ns) as unknown region, and longer than one OSC period (83.33ns) as pulse. = 1,x Disable the digital filter for HSYNC.
INTFLG (w) : Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt enable bit is set, the INT1 source of 8051 core will be driven by a zero level. Software MUST clear this register while serving the interrupt routine. HPRchg= 1 =0 VPRchg= 1 =0 HPLchg = 1 =0 VPLchg = 1 =0 HFchg = 1 =0 VFchg = 1 =0 Vsync = 1 =0 No action. Clears HSYNC presence change flag. No action. Clears VSYNC presence change flag. No action. Clears HSYNC polarity change flag. No action. Clears VSYNC polarity change flag. No action. Clears HSYNC frequency change flag. No action. Clears VSYNC frequency change flag. No action. Clears VSYNC interrupt flag.
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INTFLG (r) : Interrupt flag. Indicates a HSYNC presence change. Indicates a VSYNC presence change. Indicates a HSYNC polarity change. Indicates a VSYNC polarity change. Indicates a HSYNC frequency change or counter overflow. Indicates a VSYNC frequency change or counter overflow. Indicates a VSYNC interrupt. HPRchg= 1 VPRchg= 1 HPLchg = 1 VPLchg = 1 HFchg = 1 VFchg = 1 Vsync = 1 INTEN (w) :
Interrupt enable. Enables HSYNC presence change interrupt. Enables VSYNC presence change interrupt. Enables HSYNC polarity change interrupt. Enables VSYNC polarity change interrupt. Enables HSYNC frequency change / counter overflow interrupt. Enables VSYNC frequency change / counter overflow interrupt. Enables VSYNC interrupt.
EHPR = 1 EVPR = 1 EHPL = 1 EVPL EHF EVF =1 =1 =1
EVsync = 1
DDC & IIC Interface i) DDC1/DDC2x Mode, DDCRAM and SlaveA block The MTV312M enters DDC1 mode after Reset. In this mode, VSYNC is used as data clock. The HSCL pin should remain at high. The data output to the HSDA pin is taken from a shift register in MTV312M. The shift register automatically fetches EDID data from the lower 128 bytes of the Dual Port RAM (DDCRAM), then sends it in 9-bit packet formats inclusive of a null bit (=1) as packet separator. S/W may enable/disable the DDC1 function by setting/clearing the DDC1en control bit. The MTV312M switches to DDC2x mode when it detects a high to low transition on the HSCL pin. In this mode, the SlaveA IIC block automatically transmits/receives data to/from the IIC Master. The transmitted/received data is taken-from/saved-to the DDCRAM. In simple words, MTV312M can behaves as 24LC02 EEPROM. The only thing S/W needs to do is to write the EDID data to DDCRAM. The slave address of SlaveA block can be chosen by S/W as 5-bit, 6-bit or 7-bit. For example, if S/W chooses 5-bit slave address as 10100b, the SlaveA IIC block then responds to slave address 10100xxb. The SlaveA can be enabled/disabled by setting/clearing the EnslvA bit. The lower/upper DDCRAM can/cannot be written by the IIC Master by setting/clearing the EN128w/En256w bit. Besides, if the Only128 control bit is set, the SlaveA only accesses the lower 128 bytes of the DDCRAM. The MTV312M returns to DDC1 mode if HSCL is kept high for 128 VSYNC clock period. However, it locks in DDC2B mode if a valid IIC address (1010xxxb) has been detected on HSCL/HSDA bus. The DDC2 flag reflects the current DDC status, S/W may clear it by writing a "0" to it. ii) SlaveB Block The SlaveB IIC block is connected to HSDA and HSCL pins. This block can receive/transmit data using IIC protocols. S/W may write the SLVBADR register to determine the slave addresses. In receive mode, the block first detects IIC slave address matching the condition then issues a SlvBMI interrupt. The data from HSDA is shifted into shift register then written to RCBBUF register when a data byte is received. The first byte loaded is word address (slave address is dropped). This block also generates a RCBI (receives buffer full interrupt) every time when the RCBBUF is loaded. If S/W is not able to read out the RCBBUF in time, the next byte in shift register is not written to RCBBUF and the slave block returns NACK to the master. This feature guarantees the data integrity of communication. The WadrB flag can tell S/W whether the data in RCBBUF is a word address or not.
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In transmit mode, the block first detects IIC slave address matching the condition, then issues a SlvBMI interrupt. In the meantime, the data pre-stored in the TXBBUF is loaded into shift register, resulting in TXBBUF emptying and generates a TXBI (transmit buffer empty interrupt). S/W should write the TXBBUF a new byte for the next transfer before shift register empties. A failure of this process causes data corrupt. The TXBI occurs every time when shift register reads out the data from TXBBUF. The SlvBMI is cleared by writing "0" to corresponding bit in INTFLG register. The RCBI is cleared by reading out RCBBUF. The TXBI is cleared by writing TXBBUF. *Please refer to the attachments about "Slave IIC Block Timing". iii) Master Mode IIC Function Block The master mode IIC block can be connected to the ISDA /ISCL pins or the HSDA/HSCL pins, selected by Msel control bit. Its speed can be selected within the range of 50KHz-400KHz by S/W setting the MIICF1/MIICF0 control bit. The software program can access the external IIC device through this interface. A summary of master IIC access is illustrated as follows. To write IIC Device 1. Write MBUF the Slave Address. 2. Set S bit to Start. 3. After the MTV312M transmits this byte, a MbufI interrupt is triggered. 4. Programs can write MBUF to transfer next byte or set P bit to stop. * Please refer to the attachments about "Master IIC Transmit Timing". To read IIC Device 1. Write MBUF the Slave Address. 2. Set S bit to Start. 3. After the MTV312M transmits this byte, a MbufI interrupt is triggered. 4. Set or reset the MAckO flag according to the IIC protocol. 5. Read out MBUF the useless byte to continue the data transfer. 6. After the MTV312M receives a new byte, the MbufI interrupt is triggered again. 7. Read MBUF also trigger the next receive operation, but set P bit before read can terminate the operation. * Please refer to the attachments about "Master IIC Receive Timing".
Reg name IICCTR IICSTUS INTFLG INTFLG INTEN MBUF DDCCTR SLVAADR RCBBUF TXBBUF SLVBADR addr F00h (r/w) F01h (r) F03h (r) F03h (w) F04h (w) F05h (r/w) F06h (w) F07h (w) F08h (r) F08h (w) F09h (w) ETXBI ERCBI bit7 DDC2 WadrB TXBI RCBI SlvRWB SlvBMI SlvBMI ESlvBMI SAckIn STOPI STOPI ESTOPI SLVS ReStaI ReStaI EReStaI WSlvAI WSlvAI EWSlvA I SlvAbs1 bit6 bit5 bit4 bit3 bit2 MAckO P bit1 S MAckIn MbufI MbufI EMbufI bit0
Master IIC receive/transmit data buffer DDC1en ENSlvA En128W En256W Only128 SlvAbs0 Slave A IIC address
Slave B IIC receive buffer Slave B IIC transmit buffer ENSlvB Slave B IIC address
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IICCTR (r/w) : IIC interface status/control register. DDC2 is active. MTV312M remains in DDC1 mode. In master receive mode, NACK is returned by MTV312M. In master receive mode, ACK is returned by MTV312M. Start condition when Master IIC is not during transfer. =0 MAckO = 1 =0 S, P = , 0 DDC2 = 1
= X, Stop condition when Master IIC is not during transfer. = 1, X Resume transfer after a read/write MBUF operation. IICSTUS (r) : IIC interface status register. The data in RCBBUF is word address. Current transfer is slave transmit Current transfer is slave receive The external IIC host respond NACK. The slave block has detected a START, cleared when STOP detected. Master IIC bus error, no ACK received from the slave IIC device. ACK received from the slave IIC device.
WadrB = 1 SlvRWB = 1 =0 SAckIn = 1 SLVS =1 =0 MAckIn = 1
INTFLG (w) : Interrupt flag. A interrupt event will set its individual flag, and, if the corresponding interrupt enable bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear this register while serving the interrupt routine. SlvBMI = 1 =0 STOPI = 1 =0 ReStaI = 1 =0 WSlvAI = 1 =0 MbufI =1 =0 INTFLG (r) : TXBI RCBI No action. Clears SlvBMI flag. No action. Clears STOPI flag. No action. Clears ReStaI flag. No action. Clears WSlvAI flag. No action. Clears Master IIC bus interrupt flag (MbufI).
Interrupt flag. =1 =1 Indicates the TXBBUF need a new data byte, cleared by writing TXBBUF. Indicates the RCBBUF has received a new data byte, cleared by reading RCBBUF. Indicates the slave IIC address B match condition. Indicates the slave IIC has detected a STOP condition. Indicates the slave IIC has detected a repeat START condition. Indicates the slave A IIC has detected a STOP condition of write mode. Indicates a byte is sent/received to/from the master IIC bus.
SlvBMI = 1 STOPI = 1 ReStaI = 1 WSlvAI = 1 MbufI INTEN (w) : =1
Interrupt enable. Enables TXBBUF interrupt. Enables RCBBUF interrupt.
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ETXBI = 1 ERCBI = 1
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ESlvBMI = 1 ESTOPI = 1 EReStaI = 1 EWSlvAI = 1 EMbufI = 1 Enables slave address B match interrupt. Enables IIC bus STOP interrupt. Enables IIC bus repeat START interrupt. Enables slave A IIC bus STOP of write mode interrupt. Enables Master IIC bus interrupt.
Mbuf (w) : Master IIC data shift register, after START and before STOP condition, write this register resumes MTV312M's transmission to the IIC bus. Mbuf (r) : Master IIC data shift register, after START and before STOP condition, read this register resumes MTV312M's reception from the IIC bus. DDCCTR (w) : DDC interface control register. DDC1en = 1 =0 En128W = 1 =0 En256W = 1 =0 Only128 = 1 Enables DDC1 data transfer in DDC1 mode. Disables DDC1 data transfer in DDC1 mode. The lower 128 bytes (00-7F) of DDCRAM can be written by IIC master. The lower 128 bytes (00-7F) of DDCRAM cannot be written by IIC master. The higher 128 bytes (80-FF) of DDCRAM can be written by IIC master. The higher 128 bytes (80-FF) of DDCRAM cannot be written by IIC master. The SlaveA always accesses EDID data from the lower 128 bytes of DDCRAM.
=0 The SlaveA accesses EDID data from the whole 256 bytes DDCRAM. SlvAbs1,SlvAbs0 : Slave IIC block A's slave address length. = 1,0 = 0,1 = 0,0 5-bit slave address. 6-bit slave address. 7-bit slave address.
SLVAADR (w) : Slave IIC block A's enable and address. ENslvA = 1 =0 bit6-0 : RCBBUF (r) : Enables slave IIC block A. Disables slave IIC block A. Slave IIC address A to which the slave block should respond.
Slave IIC block B receives data buffer.
TXBBUF (w) : Slave IIC block B transmits data buffer. SLVBADR (w) : Slave IIC block B's enable and address. ENslvB = 1 =0 bit6-0 : Enables slave IIC block B. Disables slave IIC block B. Slave IIC address B to which the slave block should respond.
Low Power Reset (LVR) & Watchdog Timer When the voltage level of power supply is below 3.8V(+/-0.4V) / 2.5V(+/-0.3V) in 5V / 3.3V applications for a specific period of time, the LVR generates a chip reset signal. After the power supply is above 3.8V(+/-0.4V) / 2.5V(+/-0.3V) in 5V / 3.3V applications, LVR maintains in reset state for 144 X'tal cycle to guarantee the chip exit reset condition with a stable X'tal oscillation.
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The Watchdog Timer automatically generates a device reset when it is overflowed. The interval of overflow is 0.25 sec x N, where N is a number from 1 to 8, and can be programmed via register WDT(2:0). The timer function is disabled after power on reset, users can activate this function by setting WEN, and clear the timer by setting WCLR. A/D converter The MTV312M is equipped with four VDD range 6-bit A/D converters. So if the VDD = 5V/3.3V, and then the ADC conversion range is 5V/3.3V, S/W can select the current convert channel by setting the SADC1/SADC0 bit. The refresh rate for the ADC is OSC freq./1536 (128us for 12MHz X'tal). The ADC compares the input pin voltage with internal VDD*N/64 voltage (where N = 0 - 63). The ADC output value is N when pin voltage is greater than VDD*N/64 and smaller than VDD*(N+1)/64.
Reg name ADC ADC WDT addr F10h (w) F10h (r) F18h (w) WEN WCLR bit7 ENADC ADC convert result WDT2 WDT1 WDT0 bit6 bit5 bit4 bit3 SADC3 bit2 SADC2 bit1 SADC1 bit0 SADC0
WDT (w) : WEN WCLR
Watchdog Timer control register. =1 =1 =1 =2 =3 =4 =5 =6 =7 Enables Watchdog Timer. Clears Watchdog Timer. Overflow interval = 8 x 0.25 sec. Overflow interval = 1 x 0.25 sec. Overflow interval = 2 x 0.25 sec. Overflow interval = 3 x 0.25 sec. Overflow interval = 4 x 0.25 sec. Overflow interval = 5 x 0.25 sec. Overflow interval = 6 x 0.25 sec. Overflow interval = 7 x 0.25 sec.
WDT2: WDT0 = 0
ADC (w) : ENADC SADC0 SADC1 SADC2 SADC3 ADC (r) :
ADC control. =1 =1 =1 =1 =1 Enables ADC. Selects ADC0 pin input. Selects ADC1 pin input. Selects ADC2 pin input. Selects ADC3 pin input.
ADC convert result.
In System Programming function (ISP) The Flash memory can be programmed by a specific WRITER in parallel mode, or by IIC Host in serial mode while the system is working. The features of ISP are outlined as below: 1. Single 3.3V power supply for Program/Erase/Verify. 2. Block Erase: 512 Byte, 10mS time 3. Whole Flash erase (Blank): 10mS 4. Byte/Word programming Cycle time: 60uS per byte 5. Read access time: 40ns
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6. 7. 8. 9. Only one two-pin IIC bus (shared with DDC2) is needed for ISP in user/factory mode. IIC Bus clock rates up to 140KHz. Whole 64K-byte Flash programming within 6 Sec. CRC check provides 100% coverage for all single/double bit errors.
After Power On/Reset, The MTV312M runs the original Program Code. Once the S/W detects an ISP request (by key or IIC), S/W can accept the request following the steps below: 1. Clear watchdog to prevent reset during ISP period. 2. Disable all interrupt to prevent CPU wake-up. 3. Write IIC address of ISP slave to ISPSLV for communication. 4. Write 93h to ISP enable register (ISPEN) to enable ISP. 5. Enter 8051 idle mode. When ISP is enabled, the MTV312M disables Watchdog reset and switches the Flash interface to ISP host in 15-22.5uS. So S/W MUST enter idle mode immediately after enabling ISP. In the 8051 idle mode, PWM DACs and I/O pins keep running at their former status. There are 4 types of IIC bus transfer protocols in ISP mode. Command Write S-tttttt10k-cccccxxxk-AAAAAAAAk-P Command Read S-tttttt11k-cccccXXXK-AAAAAAAAK-aaaaaaaaK-RRRRRRRRK-rrrrrrrrK-P Data Write S-tttttt00k-aaaaaaaak-ddddddddk-ddddddddk- ... -P Data Read S-tttttt00k-aaaaaaaak-(P)S-tttttt01k-ddddddddK-ddddddddK- ... -P where S = start or re-start P = stop K = ack by host (0 or 1) k = ack by slave tttttt = ISP slave address ccccc = command x = don't care X = not defined AAAAAAAA = address[15:8] aaaaaaaa = address[7:0] RRRRRRRR = CRC_register[15:8] rrrrrrrr = CRC_register[7:0] dddddddd = data ccccc = 10100 Program ccccc = 00110 Page Erase 512 bytes (Erase) ccccc = 01101 Erase entire Flash (Blank) ccccc = 11010 Clear CRC_register (Clr_CRC) ccccc = 01001 Reset MTV312M (Reset_CPU) i) ISP Command Write The 2nd byte of "Command Write" can define the operating mode of MTV312M in its "Data Write" stage, clear CRC register, or reset MTV312M. The 3rd byte of Command Write defines the page address. A Command Write may consist of 1,2 or 3 bytes. ii) ISP Command Read The 2nd byte echoes the current command in ISP slave. The 3rd and 4th bytes reflect the current Flash address. The 5th and 6th bytes report the CRC result. A Command Read may consist of 2,3,4,5 or 6 bytes.
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MTV312M64
iii) ISP Data Write The 2nd byte defines the low address of Flash. After receiving the 3rd byte, the MTV312M executes a Program/Erase/Blank command depending on the preceding "Command Write". The low address of Flash increases every time when ISP slave acknowledges the data byte. The Blank/Erase command needs one data byte (content is "don't care"). The execution time is 10mS. During the 10mS period, the ISP slave does not accept any command/data and returns non-ack to any IIC bus activity. The Program command may have 1-256 data bytes. The program cycle time is 60us. If the ISP slave is not able to complete the program cycle in time, it returns non-ack to the following data byte. In the meantime, the low address does not increase and the CRC does not count the non-acked data byte. A Data Write may consist of 1,2 or more bytes. Data Write (Blank/Erase) S-tttttt00k-aaaaaaaak-ddddddddk-P ... S-ttttttxxk|----Min. 10mS----| Data Write (Program) S-tttttt00k-aaaaaaaak-ddddddddk-ddddddddk- ... |Min. 60uS| iv) ISP Data Read The 1st and 2nd bytes are the same as "Data Write" to define the low address of Flash. Between 2nd and 3rd bytes, the ISP host may issue Stop-Start or only Re-Start. From the 4th byte, the ISP slave sends the data byte of Flash to ISP Host. The low address automatically increases every time when data byte is transferred. v) Cyclic Redundancy Check (CRC)
To shorten the verify time, the ISP slave provides a simple way to check whether data error occurs during the program data transfer. After the ISP Host sends a lot of data byte to ISP slave, Host can use Command Read to check result of CRC register instead of reading every byte in Flash. The CRC register counts every data byte which ISP slave acknowledges during "Data Write" period. However, the low address byte and the data byte of Erase/Blank are not counted. The Clear CRC command will write all "1" to the 16-bit CRC register. For CRC generation, the 16-bit CRC register is seeded with all "1" pattern (by device reset or Clear CRC command). The data byte shifted into the CRC register is Msb first. The actual implementation is described as follows: CRCin = CRC[15]^DATAin; CRC[15:0] = {CRC[14]^CRCin, CRC[13:2], CRC[1]^CRCin, CRC[0], CRCin}; Where ^ = XOR example: data_byte CRC_register_remainder FFFFH F6H FF36H 28H 34F2H C3H 7031H vi) Reset Device
After the Flash been program completed and verified OK, the ISP Host can use "Command Write" with Reset_CPU command to wake up MTV312M.
Reg name ISPSLV ISPEN addr F0Bh(w) F0Ch(w) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
ISP Slave address Write 93h to enable ISP Mode
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MTV312M64
Memory Map of XFR
Reg name IICCTR IICSTUS INTFLG INTFLG INTEN MBUF DDCCTR SLVAADR RCBBUF TXBBUF SLVBADR ISPSLV ISPEN ADC ADC WDT DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 PORT5 PORT5 PORT5 PORT5 PORT5 PORT5 PORT5 PORT6 addr F00h (r/w) F01h (r) F03h (r) F03h (w) F04h (w) F05h (r/w) F06h (w) F07h (w) F08h (r) F08h (w) F09h (w) F0Bh(w) F0Ch(w) F10h (w) F10h (r) F18h (w) F20h(r/w) F21h(r/w) F22h(r/w) F23h(r/w) F24h(r/w) F25h(r/w) F26h(r/w) F27h(r/w) F28h(r/w) F29h(r/w) F2Ah(r/w) F2Bh(r/w) F2Ch(r/w) F2Dh(r/w) F30h(r/w) F31h(r/w) F32h(r/w) F33h(r/w) F34h(r/w) F35h(r/w) F36h(r/w) F38h(r/w) WEN WCLR ETXBI ERCBI bit7 DDC2 WadrB TXBI RCBI SlvRWB SlvBMI SlvBMI ESlvBMI SAckIn STOPI STOPI ESTOPI SLVS ReStaI ReStaI EReStaI WSlvAI WSlvAI EWSlvA I SlvAbs1 bit6 bit5 bit4 bit3 bit2 MAckO P bit1 S MAckIn MbufI MbufI EMbufI bit0
Master IIC receives/transmits data buffer DDC1en ENSlvA En128W En256W Only128 SlvAbs0 Slave A IIC address
Slave B IIC receives buffer Slave B IIC transmits buffer ENSlvB Slave B IIC address ISP Slave address Write 93h to enable ISP Mode ENADC ADC convert Result WDT2 WDT1 WDT0 Pulse width of PWM DAC 0 Pulse width of PWM DAC 1 Pulse width of PWM DAC 2 Pulse width of PWM DAC 3 Pulse width of PWM DAC 4 Pulse width of PWM DAC 5 Pulse width of PWM DAC 6 Pulse width of PWM DAC 7 Pulse width of PWM DAC 8 Pulse width of PWM DAC 9 Pulse width of PWM DAC 10 Pulse width of PWM DAC 11 Pulse width of PWM DAC 12 Pulse width of PWM DAC 13 P50 P51 P52 P53 P54 P55 P56 P60 SADC3 SADC2 SADC1 SADC0
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MTV312M64
PORT6 PORT6 PORT6 PORT6 PORT6 PORT6 PORT6 HVSTUS HCNTH HCNTL VCNTH VCNTL HVCTR0 HVCTR2 HVCTR3 HVCTR4 INTFLG INTEN PADMOD PADMOD PADMOD PADMOD PADMOD PADMOD OPTION PORT4 PORT4 PORT4 F39h(r/w) F3Ah(r/w) F3Bh(r/w) F3Ch(r/w) F3Dh(r/w) F3Eh(r/w) F3Fh(r/w) F40h(r) F41h(r) F42h(r) F43h(r) F44h(r) F40h(w) F42h(w) F43h(w) F44h(w) F48h(r/w) F49h(w) F50h(w) F51h(w) F52h(w) F53h(w) F54h(w) F55h(w) F56h(w) F58h(w) F59h(w) F5Ah(w) P67oe COP17 PWMF HIICE HPRchg EHPR DA13E VPRchg EVPR DA12E P56E IIICE P56oe P66oe COP16 DIV253 HPLchg EHPL DA11E P55E HLFVE P55oe P65oe COP15 FclkE VPLchg EVPL DA10E P54E HLFHE P54oe P64oe COP14 HFchg EHF AD3E P53E HCLPE P53oe P63oe COP13 ENSCL VFchg EVF AD2E P52E P42E P52oe P62oe COP12 Msel AD1E P51E P41E P51oe P61oe COP11 MIICF1 CVpre Hovf HF7 Vovf VF7 C1 VF6 C0 STF2 CLPEG VF5 NoHins Selft CLPPO VF4 HlfHE STF1 CLPW2 HF6 Hpol HF13 HF5 Vpol HF12 HF4 Hpre HF11 HF3 VF11 VF3 IVHlfH STF0 CLPW1 Rt1 CLPW0 DF1 DF0 Vsync EVsync AD0E P50E P40E P50oe P60oe COP10 MIICF0 P40 P41 P42 Vpre HF10 HF2 VF10 VF2 Hoff HF9 HF1 VF9 VF1 HBpl Rt0 P61 P62 P63 P64 P65 P66 P67 Voff HF8 HF0 VF8 VF0 VBpl
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MTV312M64
ELECTRICAL PARAMETERS Absolute Maximum Ratings at: Ta= 0 to 70 oC, VSS=0V
Name Maximum Supply Voltage Maximum Input Voltage (HSYNC, VSYNC & open-drain pins) Maximum Input Voltage (other pins) Maximum Output Voltage Maximum Operating Temperature Maximum Storage Temperature Symbol VDD Vin1 Vin2 Vout Topg Tstg -0.3 to +6.0 -0.3 to 5V+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 0 to +70 -25 to +125 Range Unit V V V V oC oC
Allowable Operating Conditions at: Ta= 0 to 70 oC, VSS=0V
Name Supply Voltage Input "H" Voltage Input "L" Voltage Operating Freq. Symbol VDD Vih1 Vih2 Vil1 Vil2 Fopg Condition 5V applications 3.3V applications 5V applications 3.3V applications 5V applications 3.3V applications Min. 4.5 3.0 0.4 x VDD 0.6 x VDD -0.3 -0.3 Max. 5.5 3.6 VDD +0.3 VDD +0.3 0.2 x VDD 0.3 x VDD 15 Unit V V V V V V MHz
DC Characteristics at: Ta=0 to 70 oC, VDD=5.0V/3.3V, VSS=0V
Name Output "H" Voltage, open drain pin Output "H" Voltage, 8051 I/O port pin Output "H" Voltage, CMOS output Output "L" Voltage Power Supply Current Symbol Voh1 Voh2 Voh3 Voh4 Voh5 Voh6 Vol Idd Condition VDD=5V, Ioh=0uA VDD=3.3V, Ioh=0uA VDD=5V, Ioh=-50uA VDD=3.3V, Ioh=-50uA VDD=5V, Ioh=-4mA VDD=3.3V, Ioh=-4mA Iol=5mA Active Idle Power-Down RST Pull-Down Resistor Pin Capacitance Rrst Cio VDD=5V 150 18 1.3 120 Min. 4 2.65 4 2.65 4 2.65 0.45 24 4.0 200 250 15 Typ. Max. Unit V V V V V V V mA mA uA Kohm pF
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MTV312M64
AC Characteristics at: Ta=0 to 70 oC, VDD=5.0V/3.3V, VSS=0V
Name Crystal Frequency PWM DAC Frequency HS input pulse Width VS input pulse Width HSYNC to Hblank output jitter H+V to Vblank output delay VS pulse width in H+V signal Symbol fXtal fDA tHIPW tVIPW tHHBJ tVVBD tVCPW fXtal=12MHz FXtal=12MHz 20 8 fXtal=12MHz fXtal=12MHz fXtal=12MHz 46.875 0.3 3 5 Condition Min. Typ. 12 94.86 7.5 Max. Unit MHz KHz uS uS nS uS uS
Test Mode Condition In normal application, users should avoid the MTV312M entering its test mode or writer mode, outlined as follows, adding pull-up resistor to DA8 and DA9 pins is recommended. Test Mode A: RESET=1 & DA9=1 & DA8=0 & STO=0 Test Mode B: RESET's falling edge & DA9=1 & DA8=0 & STO=1 Writer Mode: RESET=1 & DA9=0 & DA8=1
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MTV312M64
PACKAGE DIMENSION 40-pin PDIP 600 mil
Symbol A1 A2 b b1 c D E1 E2 E3 e L1 L2
Dimension in Millimeters Min 1.651 3.810 0.406 1.219 0.203 13.589 14.986 16.002 2.286 3.048 0.254 0 Nom 1.778 3.937 0.457 1.270 0.254 52.197 13.716 15.240 16.510 2.540 3.302 7.5 Max 1.905 4.064 0.559 1.371 0.355 52.578 13.843 15.494 17.018 2.794 3.556 15 Min 0.065 0.150 0.016 0.048 0.008 0.535 0.590 0.630 0.090 0.120 0.010 0
Dimension in Inches Nom 0.070 0.155 0.018 0.050 0.010 2.055 0.540 0.600 0.650 0.100 0.130 7.5 Max 0.075 0.160 0.022 0.054 0.014 2.070 0.545 0.610 0.670 0.110 0.140 15
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MTV312M64
42-pin SDIP
Symbol A A1 A2 D E E1 L eB e b b1
Dimension in Millimeters Min 0.38 3.05 36.60 15.20 12.70 2.55 0.36 0.76 0 Nom 3.80 36.80 13.70 3.30 1.78 (Typ) 0.46 1.02 7.5 0.56 1.14 15 0.014 0.030 0 Max 5.08 4.55 37.10 16.00 14.50 3.55 18.55 Min 0.015 0.120 1.44 0.600 0.500 0.100 -
Dimension in Inches Nom 0.150 1.45 0.540 0.130 0.070 (Typ) 0.018 0.040 7.5 0.022 0.045 15 Max 0.200 0.180 1.46 0.630 0.570 0.140 0.730
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MTV312M64
44-pin PLCC Unit:
Symbol A A1 A2 b b1 c D E e Gd Ge Hd He L
Dimension in Millimeters Min 0.51 3.70 0.41 0.65 0.18 16.46 16.46 15.00 15.00 17.30 17.30 2.29 0 Nom 3.80 0.46 0.70 0.25 16.60 16.60 1.27 (Typ) 15.50 15.50 17.50 17.50 2.54 16.00 16.00 17.80 17.80 2.80 10 0.590 0.590 0.680 0.680 0.090 0 Max 4.70 3.90 0.56 0.80 0.33 16.71 16.71 Min 0.020 0.145 0.016 0.026 0.007 0.648 0.648
Dimension in Inches Nom 0.150 0.018 0.028 0.010 0.653 0.653 0.050 (Typ) 0.610 0.610 0.690 0.690 0.100 0.630 0.630 0.700 0.700 0.110 10
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Max 0.185 0.155 0.022 0.032 0.013 0.658 0.658
MTV312M64
ORDERING INFORMATION Standard Configurations: Prefix MTV Part Type 312M Package Type N: PDIP S: SDIP V: PLCC ROM Size (K) 64
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