![]() |
|
If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
Datasheet File OCR Text: |
SSM9930M DUAL N- AND DUAL P-CHANNEL ENHANCEMENT-MODE POWER MOSFETS Simple drive requirement Low on-resistance Full-bridge applications, such as LCD monitor inverter SO-8 P1S/P2S P1G N2G N1S/N2S N1D/P1D N1G P2G N2D/P2D N-CH BV DSS R DS(ON) ID 30V 33m 6.3A -30V 55m -5.1A P-CH BV DSS RDS(ON) ID P1S P1G P2S Description Advanced Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SSM9930M is in the SO-8 package, which is widely preferred for commercial and industrial surface mount applications, and is well suited for applications such as low-voltage inverters and motor drives. N1G P2G P1N1D P2N2D N2G N1S N2S Absolute Maximum Ratings Symbol VDS VGS ID @ TA=25C ID @ TA=70C IDM PD @ TA=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1 3 3 Rating N-channel 30 25 6.3 4.2 20 2.0 0.016 -55 to 150 -55 to 150 P-channel -30 25 -5.1 -3.4 -20 Units V V A A A W W/C C C Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range Thermal Data Symbol Rthj-amb Parameter Thermal Resistance Junction-ambient 3 Value Max. 62.5 Unit C/W 10/21/2004 Rev.1.01 www.SiliconStandard.com 1 of 8 SSM9930M N-channel Electrical Characteristics @ Tj=25oC (unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage 2 Test Conditions VGS=0V, ID=250uA Min. 30 1 - Typ. Max. Units 0.037 33 60 3 1 25 100 - V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF BV DSS/ Tj RDS(ON) Breakdown Voltage Temperature Coefficient Reference to 25C, ID=1mA Static Drain-Source On-Resistance VGS=10V, ID=5A VGS=4.5V, ID=3A 5.2 7.1 2.3 3.8 7.2 10.4 18 7.8 600 230 94 VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70 C) o o VDS=VGS, ID=250uA VDS=10V, ID=5A VDS=30V, VGS=0V VDS=24V, VGS=0V VGS=25V ID=5A VDS=15V VGS=4.5V VDS=15V ID=1A RG=6 ,VGS =10V RD=15 VGS=0V VDS=25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 Source-Drain Diode Symbol VSD trr Qrr Parameter Forward On Voltage 2 Test Conditions IS=1.7A, VGS=0V IS=1.7A, VGS=0V dI/dt=100A/s Min. - Typ. Max. Units 21.4 16 1.2 V ns nC Reverse Recovery Time Reverse Recovery Charge 10/21/2004 Rev.1.01 www.SiliconStandard.com 2 of 8 SSM9930M P-channel Electrical Characteristics @ T j=25oC (unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage Static Drain-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70 C) o o Test Conditions VGS=0V, ID=250uA 2 Min. -30 -1 - Typ. -0.037 Max. Units 55 100 -3 -1 -25 100 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF BVDSS/ Tj RDS(ON) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Breakdown Voltage Temperature Coefficient Reference to 25C,ID=-1mA VGS=-10V, ID=-5A VGS=-4.5V, ID=-3A VDS=VGS, ID=-250uA VDS=-10V, ID=-5A VDS=-30V, VGS=0V V =-24V, VGS=0V DS VGS= 25V ID=-5A VDS=-15V VGS=-4.5V VDS=-15V ID=-1A RG=6 ,VGS =-10V RD=15 VGS=0V VDS=-25V f=1.0MHz 4.8 7.3 2.5 3.8 10.8 7.6 19.6 17.5 486 185.5 133.8 Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 Source-Drain Diode Symbol VSD trr Qrr Parameter Forward On Voltage2 Reverse Recovery Time Reverse Recovery Charge Test Conditions IS=-1.7A, VGS=0V IS=-1.7A, VGS=0V dI/dt=-100A/s Min. Typ. 21 15 Max. Units -1.2 V ns nC Notes: 1.Pulse width limited by max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in2 copper pad of FR4 board ; 135C/W when mounted on min. copper pad. 10/21/2004 Rev.1.01 www.SiliconStandard.com 3 of 8 SSM9930M N-channel 25 25 T A =25 o C 20 10V 8.0V 6.0V ID , Drain Current (A) 4.0V 20 T A =150 o C 10V 8.0V 6.0V ID , Drain Current (A) 15 15 4.0V 10 10 V G =3.0V 5 5 V G =3.0V 0 0 1 2 3 4 5 6 0 0 1 2 3 4 5 6 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 45 1.8 40 I D =5A T A =25C Normalized RDS(ON) I D =5A 1.6 V G =10V 1.4 RDS(ON) (m ) 35 1.2 30 1.0 25 0.8 20 0.6 3 4 5 6 7 8 9 10 11 -50 0 50 100 150 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 2 10.00 1.8 1.00 T j =150 o C T j =25 o C VGS(th) (V) 1.6 IS(A) 1.4 0.10 1.2 0.01 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1 -50 0 50 100 150 V SD , Source-to-Drain Voltage (V) T j ,Junction Temperature ( o C) Fig 5. Forward Characteristic of Fig 6. Gate Threshold Voltage vs. Reverse Diode 10/21/2004 Rev.1.01 Junction Temperature www.SiliconStandard.com 4 of 8 SSM9930M N-channel 12 1000 f=1.0MHz Ciss VGS , Gate to Source Voltage (V) 10 I D =4.5A V DS =15V Coss C (pF) 8 6 100 Crss 4 2 0 0 2 4 6 8 10 12 14 10 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 DUTY=0.5 Normalized Thermal Response (Rthja) 10 0.2 1ms ID (A) 10ms 100ms 0.1 0.1 0.1 0.05 1 0.02 0.01 PDM t T Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja = 135C/W 0.01 Single Pulse 1s T A =25 o C Single Pulse DC 1 10 100 0.01 0.001 0.1 0.0001 0.001 0.01 0.1 1 10 100 1000 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG 4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform Fig 12. Gate Charge Waveform 10/21/2004 Rev.1.01 www.SiliconStandard.com 5 of 8 SSM9930M P-channel 25 25 T A =25 o C 20 -10V -8.0V -ID , Drain Current (A) -6.0V 20 T A =150 o C -10V -8.0V -6.0V -ID , Drain Current (A) 15 15 -4.0V 10 10 -4.0V 5 5 V G =-3.0V 0 0 1 2 3 4 5 6 0 0 1 2 3 4 V G =-3.0V 5 6 -V DS , Drain-to-Source Voltage (V) -V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 100 1.8 90 I D =-5A T A =2\5C I D =-5A 1.6 V G = -10V 80 Normalized RDS(ON) 3 4 5 6 7 8 9 10 11 1.4 RDS(ON) (m ) 70 1.2 60 1 50 40 0.8 30 0.6 -50 0 50 100 150 -V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 3 10.00 2.5 1.00 T j =150 o C T j =25 o C -VGS(th) (V) -IS(A) 2 0.10 1.5 0.01 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1 -50 0 50 100 150 -V SD ,Source-to-Drain Voltage (V) T j ,Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode 10/21/2004 Rev.1.01 Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 6 of 8 SSM9930M P-channel 14 10000 f=1.0MHz 12 -VGS , Gate to Source Voltage (V) I D =-5A V DS =-15V 1000 10 8 C (pF) Ciss Coss Crss 100 6 4 2 0 10 0 2 4 6 8 10 12 14 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) -V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 DUTY=0.5 Normalized Thermal Response (Rthja) 0.2 10 1ms 10ms -ID (A) 1 0.1 0.1 0.05 100ms 1s 0.1 0.02 0.01 PDM t T Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja = 135C/W 0.01 Single Pulse T A =25 o C Single Pulse 0.01 0.1 1 10 DC 0.001 100 0.0001 0.001 0.01 0.1 1 10 100 1000 -V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG 4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform 10/21/2004 Rev.1.01 Fig 12. Gate Charge Waveform www.SiliconStandard.com 7 of 8 SSM9930M Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 10/21/2004 Rev.1.01 www.SiliconStandard.com 8 of 8 |
Price & Availability of SSM9930M
![]() |
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |