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DS1225Y
DS1225Y 64K Nonvolatile SRAM
FEATURES
PIN ASSIGNMENT
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3
* 10 years minimum data retention in the absence of
external power
* Data is automatically protected during power loss * Directly replaces 8K x 8 volatile static RAM or EEPROM
* Unlimited write cycles * Low-power CMOS * JEDEC standard 28-pin DIP package * Read and write access times as fast as 150 ns * Full 10% operating range * Optional
industrial temperature range of -40C to +85C, designated IND
28-PIN ENCAPSULATED PACKAGE 720 MIL EXTENDED
PIN DESCRIPTION
A0-A12 DQ0-DQ7 CE WE OE VCC GND NC - - - - - - - - Address Inputs Data In/Data Out Chip Enable Write Enable Output Enable Power (+5V) Ground No Connect
DESCRIPTION
The DS1225Y 64K Nonvolatile SRAM is a 65,536-bit, fully static, nonvolatile RAM organized as 8192 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. The NV SRAM can be used in place of existing 8K x 8 SRAMs directly conforming to the popular bytewide 28-pin DIP standard. The DS1225Y also matches the pinout of the 2764 EPROM or the 2864 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
021998 1/8
DS1225Y
READ MODE
The DS1225Y executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 13 address inputs (A0-A12) defines which of the 8192 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data access must be measured from the later occurring signal and the limiting parameter is either tCO for CE or tOE for OE rather than address access.
recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE active) then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS1225Y provides full functional capability for VCC greater than 4.5 volts and write protects at 4.25 nominal. Data is maintained in the absence of VCC without any additional support circuitry. The DS1225Y constantly monitors VCC. Should the supply voltage decay, the NV SRAM automatically write protects itself, all inputs become "don't care," and all outputs become high impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.5 volts.
WRITE MODE
The DS1225Y executes a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum
021998 2/8
DS1225Y
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -0.3V to +7.0V 0C to 70C; -40C to +85C for IND parts -40C to +70C; -40C to +85C for IND parts 260C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Power Supply Voltage Input Logic 1 Input Logic 0 SYM VCC VIH VIL MIN 4.5 2.2 0.0 TYP 5.0 MAX 5.5 VCC +0.8
(tA: See Note 10)
UNITS V V V NOTES
DC ELECTRICAL CHARACTERISTICS
PARAMETER Input Leakage Current I/O Leakage Current CE > VIH < VCC Output Current @ 2.4V Output Current @ 0.4V Standby Current CE = 2.2V Standby Current CE = VCC-0.5V Operating Current tCYC=200 ns (Commercial) Operating Current tCYC=200 ns (Industrial) Write Protection Voltage SYMBOL IIL IIO IOH IOL ICCS1 ICCS2 ICCO1 ICCO1 VTP 4.25 MIN -1.0 -1.0 -1.0 2.0 5 3 TYP
(tA: See Note 10; VCC = 5V 10%)
MAX +1.0 +1.0 UNITS A A mA mA 10 5 75 85 mA mA mA mA V 10 NOTES
021998 3/8
DS1225Y
AC ELECTRICAL CHARACTERISTICS
DS1225Y-150 PARAMETER Read Cycle Time Access Time OE to Output Valid CE to Output Valid OE or CE to Output Active Output High Z from Deselection Output Hold from Address Change Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Output High Z from WE Output Active from WE Data Setup Time Data Hold Time SYMBOL tRC tACC tOE tCO tCOE tOD tOH tWC tWP tAW tWR1 tWR2 tODW tOEW tDS tDH1 tDH2 5 60 0 10 5 150 100 0 0 10 35 5 70 0 10 5 35 5 170 120 0 0 10 35 MIN 150 150 70 150 5 35 MAX MIN 170
(tA: See Note 10; VCC=5.0V 10%)
DS1225Y-170 MAX DS1225Y-200 MIN 200 170 80 170 5 35 5 200 150 0 0 10 35 5 80 0 10 200 100 200 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 12 13 5 5 4 12 13 3 5 5 NOTES
CAPACITANCE
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN TYP MAX 10 10 UNITS pF pF
(tA = 25C)
NOTES
021998 4/8
DS1225Y
READ CYCLE
ADDRESSES VIH VIL tACC VIH CE VIH OE VIL tOE VIL tCOE tCOE tCO
tRC VIH VIL VIH VIH VIL tOH
VIH
tOD
SEE NOTE 1
DOUT
tOD VOH OUTPUT VOH VOL DATA VALID VOL
WRITE CYCLE 1
ADDRESSES VIH VIL tAW CE
tWC VIH VIL VIH VIL
VIL tWP
VIL tWR1 VIL VIH tOEW
WE
VIH tODW
VIL
HIGH IMPEDANCE tDS VIH
DOUT tDH1 VIH DATA IN STABLE VIL VIL
DIN
SEE NOTE 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
ADDRESSES VIH VIL tAW
tWC VIH VIL tWR2 tWP VIH VIL VIL VIL VIH VIH WE tCOE DOUT VIH DIN DATA IN STABLE VIL VIL VIL VIL VIH VIL
CE
tODW tDS tDH2 VIH
SEE NOTE 2, 3, 4, 6, 7, 8 AND 13
021998 5/8
DS1225Y
POWER-DOWN/POWER-UP CONDITION
VCC VTP
3.2V tF tPD tREC tR
CE LEAKAGE CURRENT IL SUPPLIED FROM LITHIUM CELL DATA RETENTION TIME tDR SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
PARAMETER CE at VIH before Power-Down VCC Slew from VTP to 0V VCC Slew from 0V to VTP CE at VIH after Power-Up SYM tPD tF tR tREC MIN 0 100 0 2 MAX UNITS s s s ms NOTES 11
(tA = 25C)
PARAMETER Expected Data Retention Time SYM tDR MIN 10 MAX UNITS years NOTES 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
NOTES:
1. WE is high for a read cycle. 2. OE = VIH or VIL. If OE = VIH during a write cycle, the output buffers remain in a high impedance state. 3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDS is measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5 pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output buffers remain in a high impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high impedance state during this period.
021998 6/8
DS1225Y
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state during this period. 9. Each DS1225Y is marked with a 4-digit date code AABB. AA designates the year of manufacture. BB designates the week of manufacture. The expected tDR is defined as starting at the date of manufacture. 10. All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial products, this range is 0C to 70C. For industrial products (IND), this range is -40C to +85C. 11. In a power down condition the voltage on any pin may not exceed the voltage on VCC. 12. tWR1, tDH1 are measured from WE going high. 13. tWR2, tDH2 are measured from CE going high. 14. DS1225Y modules are recognized by Underwriters Laboratory (U.L.(R)) under file E99151 (R).
DC TEST CONDITIONS
Outputs open. All voltages are referenced to ground.
AC TEST CONDITIONS
Output Load: 100pF + 1TTL Gate Input Pulse Levels: 0-3.0V Timing Measurement Reference Levels Input:1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
DS1225 TTP- SSS - III Operating Temperature Range Blank: 0C to 70C IND: -40C to +85C Access Speed 150: 150 ns 170: 170 ns 200: 200 ns Package Type Blank: 28-pin 600 mil DIP
VCC Tolerance Y: 10%
021998 7/8
DS1225Y
DS1225Y NONVOLATILE SRAM, 28-PIN 720 MIL EXTENDED MODULE
PKG DIM A IN. MM B IN. MM A C IN. MM D IN. MM E IN. MM F C IN. MM 28-PIN MIN 1.520 38.61 0.695 17.65 0.395 10.03 0.100 2.54 0.017 0.43 0.120 3.05 0.090 2.29 0.590 14.99 0.008 0.20 0.015 0.38 MAX 1.540 39.12 0.720 18.29 0.415 10.54 0.130 3.30 0.030 0.76 0.160 4.06 0.110 2.79 0.630 16.00 0.012 0.30 0.021 0.53
1
G IN. MM F D K G H IN. MM J IN. MM
K IN. MM
J E H B
021998 8/8

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