View HGTD8P50G1S_493513.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HGTD8P50G1, HGTD8P50G1S
March 1997
8A, 500V P-Channel IGBTs
Package
JEDEC TO-251AA
EMITTER COLLECTOR GATE
Features
* 8A, 500V * 3.7V VCE(SAT) * Typical Fall Time - 1800ns * High Input Impedance * TJ = +150oC
(FLANGE) COLLECTOR
Description
The HGTD8P50G1 and the HGTD8P50G1S are P-channel enhancement-mode insulated gate bipolar transistors (IGBTs) designed for high voltage, low on-dissipation applications such as switching regulators and motor drives. This P- channel IGBT can be paired with N-Channel IGBTs to form a complementary power switch and it is ideal for half bridge circuit configurations. These types can be operated directly from low power integrated circuits.
PACKAGING AVAILABILITY PART NUMBER HGTD8P50G1 HGTD8P50G1S PACKAGE TO-251AA TO-252AA BRAND G8P50G G8P50G
G
JEDEC TO-252AA
(FLANGE) COLLECTOR GATE EMITTER
Symbol
C
NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in the tape and reel, i.e., HGTD8P50G1S9A.
The development type number for these devices is TA49015.
E
Absolute Maximum Ratings
TC = +25oC, Unless Otherwise Specified HGTD8P50G1/G1S -500 10 -12 -8 -18 20 30 -3 -18 66 0.53 -40 to +150 +260 UNITS V V A A A V V A A W W/oC oC oC
Collector-Emitter Breakdown Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BVCES Emitter-Collector Breakdown Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BVECS Collector Current Continuous At TC = +25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC25 At TC = +90oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC90 Collector Current Pulsed (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICM Gate-Emitter Voltage Continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGES Gate-Emitter Voltage Pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGEM Switching SOA at TC = +25oC, VCL = -350V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SSOA No Snubber, Figure 17 - Circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . With 0.1F Capacitor, Figure 17 - Circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Dissipation Total at TC = +25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Power Dissipation Derating TC > +25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Lead Temperature for Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL (0.125" from case for 5s) NOTE: 1. TJ = 25oC, VCL = 350V, RGE = 25, Figure 17 - Circuit 2 (C1 = 0.1F)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
3649.3
1
Specifications HGTD8P50G1, HGTD8P50G1S
Electrical Specifications
PARAMETERS Collector-Emitter Breakdown Voltage TC = +25oC, Unless Otherwise Specified SYMBOL BVCES TEST CONDITIONS ICE = -250A VCL = -600V IEC = 1mA VCE = BVCES VCE = 0.8 BVCES Collector-Emitter Saturation Voltage VCE(SAT) ICE = -3.0A VGE = -15V VGE = 0V MIN -500 TYP MAX UNIT V
Emitter-Collector Breakdown Voltage Collector-Emitter Leakage Current
BVECS ICES
VGE = 0V TC = +25oC TC = +150oC TC = +25oC TC = +150oC TC = +25oC TC = +150oC VCE = VGE
10 -4.5 -
-2.5 -2.3 -3.0 -3.3 -6.0 -7.0 16 22 45 85 480 1800 0.8 100 3500 1.3
-250 -1.0 -2.9 -2.8 -3.7 -4.0 -7.5 100 25 30 680 2500 200 4000 -
V A mA V V V V V nA V nC nC ns ns ns ns mJ ns ns mJ
ICE = IC90 VGE = -15V
Gate-Emitter Threshold Voltage Gate-Emitter Leakage Current Gate-Emitter Plateau Voltage On-State Gate Charge
VGE(TH) IGES VGE(PL) QG(ON)
ICE = -1.0mA VGE = 20V IC = 3A IC = 3A, VCE = 0.5 BVCES
VCE = 0.5 BVCES VGE = -15V VGE = -20V
-
Current Turn-On Delay Time Current Rise Time Current Turn-off Delay Time Current Fall Time Turn-Off Energy (Note 1) Current Turn-Off Delay Time Current Fall Time Turn-Off Energy (Note 1)
tD(ON)I tRI tD(OFF)I tFI EOFF tD(OFF)I tFI EOFF
RL = 113
L = 100H
ICE = -3A, VGE = -15V VCE = -350V RG = 25 TJ = +150oC Fig. 17, Circuit 1
L = 100H
ICE = -8A, VGE = -15V VCE = -350V RG = 25 TJ = +150oC Fig. 17, Circuit 2 C1 = .022F VGE = -15V RG = 25 TJ = +25oC VCE = -350V Fig. 17, Circuit 1
-
Latching Current
IL
L = 100H
-3
-
-
A
Thermal Resistance NOTE:
RJC
-
1.75
1.90
oC/W
1. Turn-Off Energy Loss (EOFF) is defined as the integral of the instantaneous power loss starting at the trailing edge of the input pulse and ending at the point where the collector current equals zero (ICE = 0A). The HGTD8P50G1 and HGTD8P50G1S were tested per JEDEC standard No. 24-1 Method for Measurement of Power Device Turn-Off Switching Loss. This test method produces the true total Turn-Off Energy Loss. Turn-On losses include diode losses.
2
HGTD8P50G1, HGTD8P50G1S Typical Performance Curves
ICE , COLLECTOR-EMITTER CURRENT (A) ICE , COLLECTOR-EMITTER CURRENT (A) PULSE DURATION = 250s, DUTY CYCLE < 0.5%, VCE = -10V -20 PULSE DURATION = 250s, DUTY CYCLE < 0.5% -20 VGE = -15V -16 -9.0V -12 -8.0V -12V -10V
-16 TC = -40oC -12 TC = +150oC TC = +25 C
o
-8
-8
-4 0 -4
-4 -7.0V 0 0 -6.5V -4 -6 -8 -2 VCE , COLLECTOR-EMITTER VOLTAGE (V) -10
-12 -8 -10 -6 VGE , GATE-TO-EMITTER VOLTAGE (V)
-14
FIGURE 1. TRANSFER CHARACTERISTICS
FIGURE 2. SATURATION CHARACTERISTICS
PULSE DURATION = 250s, DUTY CYCLE < 0.5%, VGE = -15V -20 TC = +25oC -16 TC = -40oC -12 TC = +150oC -8
-12 -10 -8 -6 -4 -2 0 25 50 75 100 125 150 VGE = -15V
ICE , COLLECTOR-EMITTER CURRENT (A)
-14 ICE , DC COLLECTOR CURRENT (A)
-4
0
0
TC , CASE TEMPERATURE (oC)
-1 -3 -4 -5 -6 -2 VCE , COLLECTOR-EMITTER VOLTAGE (V)
-7
FIGURE 3. MAXIMUM DC COLLECTOR CURRENT AS A FUNCTION OF CASE TEMPERATURE
FIGURE 4. COLLECTOR-EMITTER SATURATION VOLTAGE
FREQUENCY = 1MHz 700 600 CIES C, CAPACITANCE (pF) 500 -400 VCE, COLLECTOR-EMITTER VOLTAGE (V)
TJ = +25oC, VGE = -15V, IG(REF) = -0.391mA -15
400 300
GATE-EMITTER VOLTAGE -7.5 VCE = -100V
-200
200 COES 100 0 0 CRES -5 -10 -15 -20 -25
COLLECTOR-EMITTER VOLTAGE 0 20 IG(REF) IG(ACT) TIME (s) 80 IG(REF) IG(ACT) 0
VCE , COLLECTOR-EMITTER VOLTAGE (V)
FIGURE 5. CAPACITANCE AS A FUNCTION OF COLLECTOREMITTER VOLTAGE
FIGURE 6. NORMALIZED SWITCHING WAVEFORMS AT CONSTANT GATE CURRENT. (REFER TO APPLICATION NOTES AN7254 AND AN7260)
3
VGE , GATE-EMITTER VOLTAGE (V)
VCE = -400V
VCE = -400V
HGTD8P50G1, HGTD8P50G1S Typical Performance Curves (Continued)
TJ = +150oC -10 VCE(SAT) , SATURATION VOLTAGE (V) WOFF , TURN-OFF SWITCHING LOSS (mJ) 10 FIG. 17, CIRCUIT 1 TJ = +150oC, RG = 25, L = 100H
-5
VGE = -10V VGE = -15V
VCE = -350V, VGE = -15V 1.0
VCE = -200V, VGE = -15V
-1 0 -2 -4 -6 -8 -10 -12 ICE , COLLECTOR-EMITTER CURRENT (A) -14
0.1 -1 -2 -3 -4 -5 ICE , PEAK COLLECTOR-EMITTER CURRENT (A)
FIGURE 7. SATURATION VOLTAGE AS A FUNCTION OF COLLECTOR-EMITTER CURRENT
FIGURE 8. TURN-OFF SWITCHING LOSS AS A FUNCTION OF COLLECTOR-EMITTER CURRENT
TJ = +150oC, VCE = -350V, VGE = -15V, L = 100H fMAX , OPERATING FREQUENCY (kHz) 1.0 tD(OFF)I , TURN-OFF DELAY TIME (s) RGE = 50 0.5 RGE = 25 100
TJ = +150oC, TC = +75oC, VGE = -15V, RGE = 25, L = 100H FIG. 17, CIRCUIT 1
50 VCE = -350V
fMAX1 = 0.05/tD(OFF)I fMAX2 = (PD - PC)/EOFF
PD = ALLOWABLE DISSIPATION PC = CONDUCTION DISSIPATION (DUTY FACTOR = 50%) RJC = 1.9oC/W 10 -1 -5 ICE , PEAK COLLECTOR-EMITTER CURRENT (A) -10
FIG. 17, CIRCUIT 1 0.1 -1 -2 -3 -4 ICE , PEAK COLLECTOR-EMITTER CURRENT (A) -5
FIGURE 9. TURN-OFF DELAY AS A FUNCTION OF COLLECTOREMITTER CURRENT
FIGURE 10. OPERATING FREQUENCY AS A FUNCTION OF COLLECTOR-EMITTER CURRENT AND VOLTAGE
ICE , PEAK COLLECTOR-EMITTER CURRENT (A)
TJ = +150oC, VGE = -15V, RG = 25, L = 100H 5 FIG. 17, CIRCUIT 1 4 tFI , FALL TIME (s)
TJ = 25oC, VGE = -15V, RG = 25, L = 100H -25 FIG. 17, CIRCUIT 2 -20
3 VCE = -200V 2 VCE = -350V
-15
-10 VCE = -350V -5
1 -1 -2 -3 -4 -5 ICE , COLLECTOR-EMITTER CURRENT (A)
0 10-5 10-4 10-3 10-2 C1, SNUBBER CAPACITANCE (F)
10-1
100
FIGURE 11. FALL TIME AS A FUNCTION OF COLLECTOREMITTER CURRENT
FIGURE 12. LATCHING CURRENT AS A FUNCTION OF SNUBBER CAPACITANCE
4
HGTD8P50G1, HGTD8P50G1S Typical Performance Curves (Continued)
VCE = -350V, VGE = -15V, RG = 25, L = 100H FIG. 17, CIRCUIT 1 -6 VTH , GATE THRESHOLD VOLTAGE (V) -7 ICE , PEAK COLLECTOR-EMITTER CURRENT (A) 6.5 VCE = VGE, ICE = 1.0mA
6.0
-5
5.5
-4
5.0
-3 -50 0 50 100 TC , CASE TEMPERATURE (oC) 150
4.5 -40 0 40 80 TC , CASE TEMPERATURE (oC) 120 160
FIGURE 13. LATCHING CURRENT AS A FUNCTION OF JUNCTION TEMPERATURE
FIGURE 14. GATE THRESHOLD VOLTAGE AS A FUNCTION OF JUNCTION TEMPERATURE
TC = 25oC, VGE = -15V, RG = 25, L = 100H 100 ZJC , NORMALIZED THERMAL 15 0.2 RESPONSE (oC/W) 0.1 10-1 0.05 0.02 0.01 SINGLE PULSE 10-3 10-5 10-4 10-3 10-2 10-1 100 101 PDS t2 NOTES: 1. DUTY FACTOR, D = t1/t2 2.PEAK TJ = (PDS x ZJC x RJC) + TA ICE , PEAK COLLECTOR-EMITTER CURRENT (A) 0.5
t1
12
9 FIG. 17, CIRCUIT 1 6
10-2
3
0 0 100 200 300 400 500 VCE , COLLECTOR-EMITTER (V)
t1 , RECTANGULAR PULSE DURATION (s) FIGURE 15. IGBT NORMALIZED TRANSIENT THERMAL IMPEDANCE, JUNCTION TO CASE
FIGURE 16. LATCHING CURRENT AS A FUNCTION OF COLLECTOR-EMITTER VOLTAGE
Test Circuits
CIRCUIT 1 CIRCUIT 2 L = 100H D1 = GSI TranZorb VCC = 350V + RG = 25 RG = 25 C1 L = 100H
D1
VCC = 350V +
FIGURE 17. INDUCTIVE SWITCHING TEST CIRCUITS
5
HGTD8P50G1, HGTD8P50G1S Operating Frequency Information
Operating frequency information for a typical device (Figure 10) is presented as a guide for estimating device performance for a specific application. Other typical frequency vs collector current (ICE) plots are possible using the information shown for a typical unit in Figure 7, Figure 8 and Figure 9. The operating frequency plot (Figure 10) of a typical device shows fMAX1 or fMAX2 whichever is smaller at each point. The information is based on measurements of a typical device and is bounded by the maximum rated junction temperature. fMAX1 is defined by fMAX1 = 0.05/tD(OFF)I. tD(OFF)I deadtime (the denominator) has been arbitrarily held to 10% of the onstate time for a 50% duty factor. Other definitions are possible. tD(OFF)I is defined as the time between the 90% point of the trailing edge of the input pulse and the point where the collector current falls to 90% of its maximum value. Device Turn-Off delay can establish an additional frequency limiting condition for an application other than TJMAX. tD(OFF)I is important when controlling output ripple under a lightly loaded condition. fMAX2 is defined by fMAX2 = (PD PC)/EOFF . The allowable dissipation (PD) is defined by PD = (TJMAX - TC)/RJC . The sum of device switching and conduction losses must not exceed Pd. A 50% duty factor was used (Figure 10) and the conduction losses (Pc) are approximated by Pc = (VCE * ICE)/2. EOFF is defined as the integral of the instantaneous power loss starting at the trailing edge of the input pulse and ending at the point where the collector current equals zero (ICE = 0A). The switching power loss (Figure 10) is defined as fMAX2 * EOFF . Turn-On switching losses are not included because they can be greatly influenced by external circuit conditions and components.
Handling Precautions for IGBTs
Insulated Gate Bipolar Transistors are susceptible to gateinsulation damage by the electrostatic discharge of energy through the devices. When handling these devices, care should be exercised to assure that the static charge built in the handler's body capacitance is not discharged through the device. With proper handling and application procedures, however, IGBTs are currently being extensively used in production by numerous equipment manufacturers in military, industrial and consumer applications, with virtually no damage problems due to electrostatic discharge. IGBTs can be handled safely if the following basic precautions are taken: 1. Prior to assembly into a circuit, all leads should be kept shorted together either by the use of metal shorting springs or by the insertion into conductive material such as "ECCOSORBD LD26" or equivalent. 2. When devices are removed by hand from their carriers, the hand being used should be grounded by any suitable means - for example, with a metallic wristband. 3. Tips of soldering irons should be grounded. 4. Devices should never be inserted into or removed from circuits with power on. 5. Gate Voltage Rating - Never exceed the gate-voltage rating of VGEM. Exceeding the rated VGE can result in permanent damage to the oxide layer in the gate region. 6. Gate Termination - The gates of these devices are essentially capacitors. Circuits that leave the gate opencircuited or floating should be avoided. These conditions can result in Turn-On of the device due to voltage buildup on the input capacitor due to leakage currents or pickup. 7. Gate Protection - These devices do not have an internal monolithic zener diode from gate to emitter. If gate protection is required an external zener is recommended. Trademark Emerson and Cumming, Inc.
INTERSILT CORPORATION PRODUCT IS COVERED BY ONE OR MORE OF THE FOLLOWING U.S. PATENTS: 4,364,073 4,587,713 4,641,162 4,794,432 4,860,080 4,969,027 4,417,385 4,598,461 4,644,637 4,801,986 4,883,767 4,430,792 4,605,948 4,682,195 4,803,533 4,888,627 4,443,931 4,618,872 4,684,413 4,809,045 4,890,143 4,466,176 4,620,211 4,694,313 4,809,047 4,901,127 4,516,143 4,631,564 4,717,679 4,810,665 4,904,609 4,532,534 4,639,754 4,743,952 4,823,176 4,933,740 4,567,641 4,639,762 4,783,690 4,837,606 4,963,951
6
HGTD8P50G1, HGTD8P50G1S TO-251AA
3 LEAD JEDEC TO-251AA PLASTIC PACKAGE
E H1 A A1 TERM. 4 SEATING PLANE
INCHES SYMBOL A A1 b b1 b2 MIN 0.086 0.018 0.028 0.033 0.205 0.018 0.270 0.250 MAX 0.094 0.022 0.032 0.040 0.215 0.022 0.290 0.265
MILLIMETERS MIN 2.19 0.46 0.72 0.84 5.21 0.46 6.86 6.35 MAX 2.38 0.55 0.81 1.01 5.46 0.55 7.36 6.73 NOTES 3, 4 3, 4 3 3, 4 3, 4 5 5 6 2
b2
D
b1
L1 L
c D E
b
1 2 3
c
e e1
0.090 TYP 0.180 BSC 0.035 0.040 0.355 0.075 0.045 0.045 0.375 0.090
2.28 TYP 4.57 BSC 0.89 1.02 9.02 1.91 1.14 1.14 9.52 2.28
e e1 Lead 1 Lead 2 Lead 3 Term. 4 Gate Collector Emitter Collector
J1
H1 J1 L L1
NOTES: 1. These dimensions are within allowable dimensions of Rev. C of JEDEC TO-251AA outline dated 9-88. 2. Solder finish uncontrolled in this area. 3. Dimension (without solder). 4. Add typically 0.002 inches (0.05mm) for solder plating. 5. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D. 6. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D. 7. Controlling dimension: Inch. 8. Revision 2 dated 10-95.
7
HGTD8P50G1, HGTD8P50G1S TO-252AA
SURFACE MOUNT JEDEC TO-252AA PLASTIC PACKAGE
E H1 A A1 SEATING PLANE D L2 1 3 L
INCHES SYMBOL A A1 b b1 b2 b3 c D E e e1 H1 J1 L
0.265 (6.7)
MILLIMETERS MIN 2.19 0.46 0.72 0.84 5.21 4.83 0.46 6.86 6.35 MAX 2.38 0.55 0.81 1.01 5.46 0.55 7.36 6.73 NOTES 4, 5 4, 5 4 4, 5 2 4, 5 7 7 4, 6 3 2
b2
MIN 0.086 0.018 0.028 0.033 0.205 0.190 0.018 0.270 0.250
MAX 0.094 0.022 0.032 0.040 0.215 0.022 0.290 0.265
b e e1
TERM. 4
b1
L1
c
J1 0.265 (6.7)
0.090 TYP 0.180 BSC 0.035 0.040 0.100 0.020 0.025 0.170 0.045 0.045 0.115 0.040 -
2.28 TYP 4.57 BSC 0.89 1.02 2.54 0.51 0.64 4.32 1.14 1.14 2.92 1.01 -
b3
L3
L1 L2 L3
0.070 (1.8) 0.118 (3.0) BACK VIEW 0.063 (1.6) 0.090 (2.3) 0.090 (2.3) MINIMUM PAD SIZE RECOMMENDED FOR SURFACE-MOUNTED APPLICATIONS 0.063 (1.6)
Lead 1 Lead 3 Term. 4
Gate Source Collector
NOTES: 1. These dimensions are within allowable dimensions of Rev. B of JEDEC TO-252AA outline dated 9-88. 2. L3 and b3 dimensions establish a minimum mounting surface for terminal 4. 3. Solder finish uncontrolled in this area. 4. Dimension (without solder). 5. Add typically 0.002 inches (0.05mm) for solder plating. 6. L1 is the terminal length for soldering. 7. Position of lead to be measured 0.090 inches (2.28mm) from bottom of dimension D. 8. Controlling dimension: Inch. 9. Revision 5 dated 10-95.
8
HGTD8P50G1, HGTD8P50G1S TO-252AA
16mm TAPE AND REEL
22.4mm 1.5mm DIA. HOLE 4.0mm 2.0mm 1.75mm C L 16mm 330mm 50mm 8.0mm
13mm
16.4mm
USER DIRECTION OF FEED
COVER TAPE
GENERAL INFORMATION 1. USE "9A" SUFFIX ON PART NUMBER. 2. 2500 PIECES PER REEL. 3. ORDER IN MULTIPLES OF FULL REELS ONLY. 4. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
Revision 5 dated 10-95
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
9

▲Up To Search▲

Price & Availability of HGTD8P50G1S

	To Download HGTD8P50G1S Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .