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SPC08A SP
6.5KB Sound Controller
SEP. 19, 2001 Version 1.7
SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
SPC08A
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3 2. BLOCK DIAGRAM ...................................................................................................................................................................................... 3 3. FEATURES.................................................................................................................................................................................................. 3 4. APPLICATION FIELD ................................................................................................................................................................................. 3 5. SIGNAL DESCRIPTIONS* .......................................................................................................................................................................... 4 6. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 5 6.1. CPU ..................................................................................................................................................................................................... 5 6.2. OSCILLATOR .......................................................................................................................................................................................... 5 6.3. BONDING OPTION .................................................................................................................................................................................. 5 6.4. ROM AREA ........................................................................................................................................................................................... 5 6.5. RAM AREA............................................................................................................................................................................................ 5 6.6. MAP OF MEMORY AND I/OS .................................................................................................................................................................... 5 6.7. I/O PORT CONFIGURATION*.................................................................................................................................................................... 5 6.8. TIMER/COUNTER ................................................................................................................................................................................... 6 6.9. SPEECH AND MELODY............................................................................................................................................................................ 7 6.10. POWER SAVING MODE ........................................................................................................................................................................ 7 7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................... 8 7.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................... 8 7.2. AC CHARACTERISTICS (TA = 25) ........................................................................................................................................................ 8 7.3. DC CHARACTERISTICS (VDD = 3.0V, TA = 25) ................................................................................................................................... 8 7.4. DC CHARACTERISTICS (VDD = 5.0V, TA = 25) ................................................................................................................................... 8 7.5. THE RELATIONSHIP BETWEEN THE ROSC AND THE FCPU ............................................................................................................................. 9 8. APPLICATION CIRCUITS......................................................................................................................................................................... 10 8.1. APPLICATION CIRCUIT .......................................................................................................................................................................... 10 8.2. CURRENT MODE DAC SPEAKER DRIVER ...............................................................................................................................................11 9. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 12 9.1. PAD ASSIGNMENT ............................................................................................................................................................................... 12 9.2. ORDERING INFORMATION ..................................................................................................................................................................... 12 9.3. PAD LOCATIONS.................................................................................................................................................................................. 13 10. DISCLAIMER............................................................................................................................................................................................. 14 11. REVISION HISTORY ................................................................................................................................................................................. 15
(c) Sunplus Technology Co., Ltd. Proprietary & Confidential
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SEP. 19, 2001 Version: 1.7
SPC08A
6.5KB SOUND CONTROLLER
1. GENERAL DESCRIPTION
The SPC08A is a CPU based one-channel speech/melody synthesizer including CMOS 8-bit microprocessor with 69 instructions, 6.5K-byte ROM for speech and melody data (Speech is compressed by a 4-bit ADPCM with approx. 2 sec speech duration @ 7KHz sampling rate) and 64-byte working SRAM. audio current output (D/A). It includes one Timer/Counter, 18 Software Selectable I/Os and one For audio processing, melody and It operates over a wide The power saving mode The Max. CPU clock In addition, the SPC08A has a speech can be mixed into one output. voltage range of 2.4V - 5.5V. Clock Stop mode for power saving.
3. FEATURES
! 8-bit microprocessor ! Provides 6.5K-byte ROM for program and audio data ! 64-byte working SRAM ! Software-based audio processing ! Wide operating voltage: 2.4V - 3.6V @ 1.5MHz 3.6V - 5.5V @ 3.0MHz ! Supports Crystal Resonator or Rosc (with Bonding option) ! Max. CPU clock: 1.5MHz @ 3.0V, 3.0MHz @ 5.0V ! Standby mode (Clock Stop mode) for power saving. Max. 2A @ 5.0V ! 500ns instruction cycle time @ 4.0MHz CPU clock ! Provides 18 general I/Os ! One 12-bit timer/counter ! 4 INT sources ! Key wake-up function ! Approx. 2 sec speech @ 7KHz sampling rate with ADPCM
saves the RAM contents, but freezes the oscillator, causing all other chip functions to be inoperative. frequency is 3.0MHz. cycles (min.) - 6 clock cycles (max.). technical support of Sunplus. It has an Instruction Cycle Rate of 2 clock The SPC08A includes, not
only the latest technology, but also the full commitment and
2. BLOCK DIAGRAM 4. APPLICATION FIELD
8-bit microprocessor 64-byte SRAM ONE 8-bit D/A (current) AUD2 XI Rosc XO CLK OSC 18 PINS GENERAL I/O PORT 6.5K-byte ROM One Timer TimeBase INT control
! Intelligent education toys Ex. Pattern to voice (animal, car, color, etc.) Spelling (English or Chinese)
AUD1
Math ! Toy controller ! Talking instrument controller ! General speech synthesizer ! Industrial controller
RESET
RESET
IOB5-0 (I/O)
IOC5-0 (I/O)
IOD5-0 (I/O)
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SPC08A
5. SIGNAL DESCRIPTIONS*
Mnemonic VDD VSS XI XO OPT*** RESET TEST AUD IOA0 IOA1 IOA2 IOA3 IOA4 IOA5 IOB0 IOB1 IOB2 IOB3 IOB4 IOB5 IOD0 IOD1 IOD2 IOD3 IOD4 IOD5 PIN No. 8 11 1 40 8A 39 35 3 34 33 32 31 30 29 28 24 23 22 21 20 19 18 13 12 10 9 Type I I I O I I I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O **See note 1 and 2 below. **See note 1 and 2 below. Port D is a 6-bit bi-directional programmable Input/Output port with Pull-low or Open-drain option. As inputs, Port D can be either Pure or Pull-low states. As outputs, Port D can be either Buffer or Open-drain PMOS type (source current). (Key change, Wake up I/O) **See note 1 and 2 below. Port B is a 6-bit bi-directional programmable Input / Output port with Pull-low or Open-drain option. IOC1: EXT INT IN IOC2: EXT COUNT IN As inputs, Port B can be in either the Pure or Pull-low states. As outputs, Port B can be either Buffer or Open-drain NMOS types (Sink current). POWER VDD POWER VSS CRYSTAL OSC IN or RESISTOR CRYSTAL OSC OUT Rosc OPTION connect to VDD RESET TEST MODE AUDIO OUTPUT Port A is a 6-bit bi-directional programmable Input / Output port with Pull-high or Open-drain option. As inputs, Port A can be in either the Pure or Pull-high states. As outputs, Port A can be either Buffer or Open-drain NMOS types (Sink current). Description
* Refer to SPC Programming Guide for complete information. **Note: 1.) Three input states can be specified; Pure Input, Pull-High or Pull Low. 2.) Three output states can be specified, Buffer output, Open Drain PMOS output (source), or Open Drain NMOS output (sink). ***OPT is the selection pin for ROSC or X'TAL using the bonding option. The shape looks like the figure at the right. When
VDD OPT
ROSC is selected, OPT is connected to VDD. If X'TAL is selected, OPT is floating. The reason OPT is near VDD is that when ROSC is selected, it is easy to make the connection between VDD and OPT.
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SPC08A
6. FUNCTIONAL DESCRIPTIONS
6.1. CPU
The 8-bit microprocessor in SPC08A is a high performance processor equipped with Accumulator, Program Counter, X Register, Stack pointer and Processor Status Register (this is the same as the 6502 instruction structure).
6.6. Map of Memory and I/Os
*I/O PORT: - PORT IOA IOB IOD *MEMORY MAP (From ROM view) $0002 $0003 $0005 $00000
HW register, I/Os
$000C0
USER RAM and STACK
- I/O CONFIG $0000 $0001 $00100
UNUSED
$00200
6.2. Oscillator
The SPC08A supports AT-cut parallel resonant oscillated Crystal / Resonator or RC Oscillator or external clock sources by using the bonding option (select one from those three types). recommendations. The design of application circuit should follow the vendors' specifications or The diagram below is typical of X'TAL/ROSC circuits for most applications:
*NMI SOURCE: - INTA (from TIMER A) $00600 *INT SOURCE: - INTA (from TIMER A) - CPU CLK / 1024 - CPU CLK / 8192 - CPU CLK / 65536 $01FFF
SUNPLUS TEST PROGRAM
USER'S PROGRAM & DATA AREA
SPC08A
XI/R XO
VDD Rosc 20 pf 20 pf
SPC08A
XI/R XO
6.7. I/O Port Configuration*
Input/Output IOA port : IOA3 - 0 logic_1 control output data VDD 60K
(a) Crystal or Ceramic Resonator Connections
(b) RC Oscillator Connections
buffer or OD-NMOS
6.3. Bonding Option
Crystal Resonator/Rosc can be selected by bonding option.
input data OD : Open Drain
6.4. ROM Area
The SPC08A provides a 6.5K-byte ROM that can be defined as the program area, audio data area, or both. To access ROM, users should program the BANK SELECT Register.
Input/Output IOA port : IOA5 - 4 logic_2 control output data VDD 60K
6.5. RAM Area
There are 64-byte RAM including stack at locations from $80 through $FF.
buffer or OD-NMOS
input data OD : Open Drain
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SPC08A
Input/Output IOB port : IOB3 - 0 input data OD-NMOS or buffer
Input/Output IOD port : IOD5 - 4 input data OD-PMOS or buffer
output data logic_3 control OD : Open Drain
output data
60K
logic_6 control OD : Open Drain
60K
Input/Output IOB port : IOB5 - 4 input data OD-NMOS or buffer
*Values shown are for VDD = 5.0V test conditions only.
6.8. Timer/Counter
SPC08A contains one 12-bit timer/counter, TMA respectively. TMA can be specified as a timer or a counter. the TMA is a re-loaded up-counter. In the timer mode, When timer overflows, the
output data logic_4 control OD : Open Drain
user's pre-set value will be reloaded automatically and the timer
60K
upcounts again.
At the same time, interrupt will be generated if If TMA is specified as a counter, users After the counter has
the interrupt is enabled.
can reset by loading #0 into the counter. counters at the same time.
been activated, the value of the counter can also be read from the
Input/Output IOD port : IOD3 - 0 input data OD-PMOS or buffer
Clock source of Timer/Counter can be selected as follows: Timer/Counter 12-BIT TIMER TMA 12-BIT COUNTER Clock Source CPU CLOCK (T) or T/4 T/64, T/8192, T/65536 or EXT CLK TMA only, select timer or counter Select T or T/4
output data logic_5 control OD : Open Drain
60K
MODE SELECT REGISTER TIMER CLOCK SELECTOR
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SPC08A
6.9. Speech and Melody
Since SPC08A provides 6.5K ROM (0.5K for Sunplus test program) only, it is a suitable IC for simple speech and melody synthesis. For speech synthesis, SPC08A can provide NMI for accurate sampling frequency. Users can record or synthesize the sound The sound data can be played back and digitize it into the ROM. program. ADPCM.
6.10. Power Saving Mode
The SPC08A provides a power saving mode (Standby mode) for those applications that require very low stand-by current. To enter standby mode, the Wake-Up Register should be enabled and then stop the CPU clock by writing the STOP CLOCK Register. awakened. The CPU will then go to the stand-by mode. In such a mode, RAM and I/Os will remain in their previous states until being Port IOD5 - 0 are the wake-up sources in SPC08A. After SPC08A is awakened, the internal CPU will go to the RESET State (Tw 65536 x T1) and then continue processing the program. Wakeup Reset will not affect the contents of RAM and
in the sequence of the control functions as designed by the user's Several algorithms are recommended for high fidelity and compression of sound including PCM, LOG PCM, and
I/Os (FIG.1).
Sleep T1
Wake-up
CPU CLK Reset
Tw
FIG. 1
T1 = 1 / (Fcpu), Tw 65536 x T1
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SPC08A
7. ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
Characteristics DC Supply Voltage Input Voltage Range Operating Temperature Storage Temperature
conditions see AC/DC Electrical Characteristics.
Symbol V+ VIN TA TSTO
Ratings < 7.0V -0.5V to V+ + 0.5V 0 to +60 -50 to +150
For normal operational
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device.
7.2. AC Characteristics (TA = 25)
Characteristics Symbol Limit Min. Typ. 1.0 2.0 Max. 1.5 3.0 Unit MHz MHz Test Condition VDD = 3.0V VDD = 5.0V
OSC Frequency
FOSC2
7.3. DC Characteristics (VDD = 3.0V, TA = 25)
Characteristics Operating Voltage Operating Current Standby Current Audio output current Input High Level Input Low Level Output High I (IOA, IOD) Output Sink I (IOA, IOD) Output Sink I (IOB) Input Resistor (IOD) Symbol VDD IOP ISTBY IAUD VIH VIL IOH IOL IOL RIN Limit Min. 2.4 2.0 Typ. 1.5 -1.5 -6.0 8.0 12 80 Max. 3.6 2.0 2.0 0.8 Unit V mA A mA V V mA mA mA Kohm Test Condition For 2-battery FCPU = 1.0MHz @ 3.0V, no load VDD = 3.0V VDD = 3.0V, one-channel VDD = 3.0V VDD = 3.0V VDD = 3.0V, VOH = 2.0V VDD = 3.0V, VOL = 0.8V VDD = 3.0V, VOL = 0.8V Pull Low, VDD = 3.0V
7.4. DC Characteristics (VDD = 5.0V, TA = 25)
Characteristics Operating Voltage Operating Current Standby Current Audio output current Input High Level Input Low Level Output High I (IOA, IOD) Output Sink I (IOA, IOD) Output Sink I (IOB) Input Resistor (IOD) Symbol VDD IOP ISTBY IAUD VIH VIL IOH IOL IOL RIN Limit Min. 3.6 3.0 Typ. 2.5 -3.0 -10 12 17 60 Max. 5.5 2.0 0.8 Unit V mA A mA V V mA mA mA Kohm Test Condition For 3-battery FCPU = 3.0MHz @ 5.0V, no load VDD = 5.0V VDD = 5.0V, one-channel VDD = 5.0V VDD = 5.0V VDD = 5.0V, VOH = 4.2V VDD = 5.0V, VOL = 0.8V VDD = 5.0V, VOL = 0.8V Pull Low, VDD = 5.0V
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SPC08A
7.5. The Relationship between the ROSC and the FCPU 7.5.1. VDD = 5.0V, TA = 25
7.5.3. Frequency vs. VDD
1.0 FCPU ( MHz ) 0.8 0.6 0.4 0.2 0.0 0 500 Rosc ( Kohms ) 1000
1.2 1.0 0.8 0.6 0.4 0.2 0.0 3.5
FCPU ( MHz )
Rosc = 200 Kohms
Rosc = 470 Kohms
4.5 VDD ( Volts )
5.5
7.5.2. Frequency vs. temperature
Frequency norm alized to 25
1.04 FCPU/FCPU (25 )
R osc=200K ohm s
1.02 1.00 0.98 0.96 0 10
V D D= 5.0V
20 30 40 50 T em perature ( )
60
70
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SEP. 19, 2001 Version: 1.7
SEP. 19, 2001
R2 150K
40 1 3
SPC08A
VDD
VDD
R1 50K 39 RESET C1 RESET 0.1 VDD 01 1N4148 29 K31 19 18 13 12 K3 K24 K8 K13 K18 K23 K33 10 K1 K2 K7 K12 K17 K22 K6 K11 K16 K21 02 1N4148 03 1N4148 05 1N4148 04 1N4148 VDD VDD VDD VDD XO XI AUD
Speaker
C2
VSS VSS TEST 2 11 35
Q1 8050 0.1
R3 680
IOA5 IOD0 IOD1 IOD2 IOD3 IOD4 IOB5 IOB0 IOB1
20 28 24 23 560
VDD 9012
K32
SPC08A
K34
IOB2 IOB3 IOB4
100 22 21 IOA0 IOA1 34 33 560 VDD 9012 100
100
100
100
100
K4
K9
K14
K19
100 K25 IOA2 32 VDD
100
100
100
K5
K10
K15
K20
IOA3 IOA4 9 IOD5
31 30
560
9012 100 VDD 100
100
100
100
VDD
8A OPT 8 VDD
560
9012 100 100
8. APPLICATION CIRCUITS
100
100
100
560
8.1. Application Circuit
220 F
9012 100 100
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9013
C3
C4 + 0.1
VDD
10
100
100
100
9013
9013
9013
9013
Proprietary & Confidential
Version: 1.7
SPC08A
8.2. Current Mode DAC Speaker Driver
C1: 0.1 F ~ 1 F RB1: 680 ~ 1.5K 4 ~ 8
VDD
RB1: 10K ~ 50K RB2: 820 ~ 1.5K C1: 0.1 F ~ 1 F
32 ~ 64
VDD
AUD C1 RB1
8050
AUD RB2
RB1 8050
C1
Figure 1
Figure 2
RB1: 2K~10K; C1: 1 F~10 F RB2: ~1K; C2: ~0.1 F 4 ~ 64
VDD
RB1: 2K~10K; C1: 1 F~10 F RB2: ~1K; C2: ~0.1 F
VDD
C2
Enable
RB1
4 ~ 8
C2
AUD
RB2
RB1 C1
8050
AUD
RB2
8050 C1
Figure 3
Figure 4
VDD
Power
RB1: ~ 360 (Vol) RB2: ~ 4.7 4 ~ 64
AUDP
3 2
6
220 F
LM386
7 4
5
AUD
1N4148
+
8050
RB1 20K
10
0.1 F
RE1
RB1
Figure 5 Figure 6
0.01 F
Figure 1: The simplest CKT uses a low impedance speaker. It has high operation current, but has lowest cost. Figure 2: It is the same as Figure 1 but a high impedance speaker is used. Figure 3: The CKT contains a low pass filter. Figure 4: Improved version of Figure 3. Figure 5: The current mirror mode. It is capable of providing higher speech quality, but it takes higher operation current. The standby current can be controlled by the enable pin.
It is able to control the volume. In addition, it has more stable and lower operation current than Figure 1-3.
Figure 6: High quality, low operation current CKT, but more expensive.
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SEP. 19, 2001 Version: 1.7
SPC08A
9. PACKAGE/PAD LOCATIONS
9.1. PAD Assignment
Chip Size: 1690m x 1840m This IC substrate should be connected to VSS
Note1: Chip size included scribe line. Note2: To ensure that the IC functions properly, bond all VDD and VSS pins. Note3: The 0.1F capacitor between VDD and VSS should be placed to IC as close as possible.
9.2. Ordering Information
Product Number SPC08A-nnnnV-C
Note1: Code number (nnnnV) is assigned for customer. Note2: Code number (nnnn = 0000 - 9999); version (A = A - Z).
Package Type Chip form
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SPC08A
9.3. PAD Locations
PAD No. 1 2 3 8A 8 9 10 11 12 13 18 19 20 21 22 23 24 28 29 30 31 32 33 34 35 39 40 PAD Name XI VSS AUD OPT VDD IOD5 IOD4 VSS IOD3 IOD2 IOD1 IOD0 IOB5 IOB4 IOB3 IOB2 IOB1 IOB0 IOA5 IOA4 IOA3 IOA2 IOA1 IOA0 TEST RESET XO X -633 -640 -625 -608 -513 -354 -187 -27 132 299 643 643 643 643 643 643 643 671 507 349 187 28 -134 -292 -452 -633 -633 Y 318 -164 -384 -660 -660 -691 -691 -690 -691 -691 -661 -500 -331 -169 0 161 330 694 694 694 694 694 694 694 682 641 475
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SEP. 19, 2001 Version: 1.7
SPC08A
10. DISCLAIMER
The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF SUNPLUS reserves the right to halt production or alter the specifications and regarding the freedom of the described chip(s) from patent infringement. MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. prices at any time without notice. publication are current before placing orders.
Accordingly, the reader is cautioned to verify that the data sheets and other information in this Products described herein are intended for use in normal commercial applications. Please note that application circuits
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. illustrated in this document are for reference purposes only.
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SEP. 19, 2001 Version: 1.7
SPC08A
11. REVISION HISTORY
Date SEP. 18, 1997 NOV. 06, 1997 MAR. 20, 1998 Revision # 0.1 0.2 1.0 Original Renew to a new document format VDD operation range 2.4V - 3.0V (frequency 0.1MHz - 1.5MHz) 3.6V - 5.5V (frequency 0.1MHz - 3.0MHz) MAY. 13, 1998 JUN. 01, 1998 1.1 1.2 Add "Note: To ensure that the IC functions properly, bond all VDD and VSS pins." 1. Revise the grammars and spelling in "GENERAL DESCRIPTION", "FEATURES", and "APPLICATION CIRCUITS" 2. Revise the pin naming in Pad Assignment RESB -> RESET, AUDA -> AUD JUN, 10, 1998 1.3 1. Add OPT pin description in the "SIGNAL DESCRIPTIONS" 2. Add "The Relationship between the ROSC and the FCPU" NOV. 14, 1999 1.4 1. Renew to a new document format 2. Add 3.0V description in the "ELECTRICAL SPECIFICATIONS" 3. Modify "APPLICATION CIRCUITS" SEP. 01, 2000 1.5 1. When VDD = 5.0V, VOH = 4.2V, add typical value (IOH = -10mA) 2. When VDD = 5.0V, VOL = 0.8V, add typical value (IOL = 12mA) for IOA, IOD 3. When VDD = 5.0V, VOL = 0.8V, add typical value (IOL = 17mA) for IOB 4. When VDD = 3.0V, VOH = 2.0V, add typical value (IOH = -6mA) 5. When VDD = 3.0V, VOL = 0.8V, add typical value (IOL = 8mA) for IOA, IOD 6. When VDD = 3.0V, VOL = 0.8V, add typical value (IOL = 12mA) for IOB SEP. 01, 2000 1.6 Modify: 1. FCPU = 3.0MHz @ 3.0V -> FCPU = 1.0MHz @ 3.0V 2. FCPU = 1.0MHz @ 5.0V -> FCPU = 3.0MHz @ 5.0V SEP. 19, 2001 1.7 1. Modify wide operating voltage: 2.4V - 3.4V -> 2.4V - 3.6V 2. Correct chip size 3. Add Note1 and Note3 in the "9.1 PAD Assignment" 4. Renew to a new document format 7 8 3, 8 12 12 Description Page
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