View FMS6501MSA28X_510188.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FMS6501 12 Input 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
May 2005
FMS6501 12 Input 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Features
12 x 9 Crosspoint Matrix Supports SD, PS, and HD 1080i/1080p Video Input Clamp / Bias Circuitry AC or DC-Coupled Inputs AC or DC-Coupled Outputs Dual Load(75) Output Drivers with High Impedance Disable One-to-One or One-to-Many Input to Output Switching Programmable Gain: +6, +7, +8 or +9dB I2CTM Compatible Digital Interface, Standard Mode 3.3V or 5V single supply operation Lead (Pb) Free SSOP-28 Package
Description
The FMS6501 provides 12 inputs which can be routed to any of 9 outputs. Each input can be routed to one or more outputs but only one input may be routed to any output. The input to output routing is controlled via an I2C compatible digital interface. Each input supports an integrated clamp option to set the output sync tip level of video with sync to ~300mV. Alternatively, the input may be internally biased to center signals without sync (Chroma, Pb, Pr) at ~1.25V. These DC output levels are for the 6dB gain setting. Higher gain settings will increase the DC output levels accordingly. The input clamp / bias mode is selected via I2C. Unused outputs may be powered down to reduce power dissipation.
Applications
Cable and Satellite set top boxes TV and HDTV Sets A/V Switchers Personal Video Recorders (PVR) Security / Surveillance Video Distribution Automotive (In-Cabin Entertainment)
Block Diagram
IN1 C/B
IN2
C/B
IN12
C/B
SDA SCL ADDR VCC (2) GND (2) OUT1 OUT2 OUT9 Programmable Gain 6, 7, 8 or 9dB Programmable Enable/Disable
(c)2004 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com
FMS6501 Rev. 1A
FMS6501 12 Input 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Pin Configuration
Pin Assignments
Pin#
1 2 3 4
Pin
IN1 IN2 IN3 IN4 IN5 IN6 VCC GND IN7 IN8 IN9 IN10 IN11 IN12 ADDR SCL SDA OUT9 OUT8 OUT7 GNDO VCCO OUT6 OUT5 OUT4 OUT3 OUT2 OUT1
Type
Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Output Output Input Input Output Output Output Output Output Output
Description
Input, channel 1 Input, channel 2 Input, channel 3 Input, channel 4 Input, channel 5 Input, channel 6 Positive power supply Must be tied to Ground Input, channel 7 Input, channel 8 Input, channel 9 Input, channel 10 Input, channel 11 Input, channel 12 Selects I2C address. "0" = 0x06 (0000 0110), `1" = 0x86 (1000 0110) Serial Clock for I2C Port Serial Data for I2C Port Output, channel 9 Output, channel 8 Output, channel 7 Must be tied to Ground Positive power supply for Output Drivers Output, channel 6 Output, channel 5 Output, channel 4 Output, channel 3 Output, channel 2 Output, channel 1
IN1 IN2 IN3 IN4 IN5 IN6 VCC GND IN7 IN8 IN9 IN10 IN11 IN12
1 2 3 4 5 6
28 27 26 25
OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 VCCO GNDO OUT7 OUT8 OUT9 SDA SCL ADDR
5 6 7 8 9 10
FAIRCHILD FMS6501
24 23
11 12 13
28L SSOP
7 8 9 10 11 12 13 14 22 21 20 19 18 17 16 15
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
2 FMS6501 Rev. 1A
www.fairchildsemi.com
FMS6501 12 Input 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Absolute Maximum Ratings
Parameter
DC Supply Voltage Analog and Digital I/O Output Current Any One Channel, Do Not Exceed
Min.
-0.3 -0.3
Max.
6 Vcc + 0.3 40
Unit
V V mA
Reliability Information
Parameter
Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Thermal Resistance (ThetaJA), JEDEC Standard Multi-Layer Test Boards, Still Air 50 -65
Min.
Typ.
Max.
150 150 300
Unit
C C C C/W
Recommended Operating Conditions
Parameter
Operating Temperature Range Supply Voltage Range
Min.
0 3.135
Typ.
5.0
Max.
85 5.25
Unit
C V
3 FMS6501 Rev. 1A
www.fairchildsemi.com
FMS6501 12 Input 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Digital Interface
The I2C compatible interface is used to program output enables, input to output routing, input clamp / bias and output gain. The I2C address of the FMS6501 is 0x06 (0000 0110) with the ability to offset it to 0x86 (1000 0110) by tying the ADDR pin high. Both data and address data of eight bits each are written to the FMS6501 I2C address to access all the control functions. There are separate internal addresses for each output. Each output's address includes bits to select an input channel, adjust the output gain, and enable or disable the output amplifier. More than one output can select the same input channel for one-to-many routing. When the outputs are disabled they are placed in a high-impedance state. This allows multiple FMS6501 devices to be paralleled to create a larger switch matrix. Typical output power-up times will be less than 500ns. The clamp / bias control bits are written to their own internal address since they should always remain the same regardless of signal routing. They are set based on the input signal connected to the FMS6501. All undefined addresses may be written without effect.
Output Control Register Contents and Defaults Control Name
Enable Gain In
Width
1 bit 2 bits 5 bits
Type
Write Write Write
Default
0 0 0
Bit(s)
7 6:5 4:0
Description
Channel Enable: 1=Enable, 0=Power Down1 Channel Gain: 00=6dB, 01=7dB, 10=8dB, 11=9dB Input selected to drive this output: 00000=OFF2, 00001=IN1, 00010=IN2,..., 01100=IN12
Output Control Register MAP Register Name Address Bit 7
OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 Enable Enable Enable Enable Enable Enable Enable Enable Enable
Bit 6
Gain1 Gain1 Gain1 Gain1 Gain1 Gain1 Gain1 Gain1 Gain1
Bit5
Gain0 Gain0 Gain0 Gain0 Gain0 Gain0 Gain0 Gain0 Gain0
Bit43
In4 In4 In4 In4 In4 In4 In4 In4 In4
Bit3
In3 In3 In3 In3 In3 In3 In3 In3 In3
Bit2
In2 In2 In2 In2 In2 In2 In2 In2 In2
Bit1
In1 In1 In1 In1 In1 In1 In1 In1 In1
Bit0
In0 In0 In0 In0 In0 In0 In0 In0 In0
Clamp Control Register Contents and Defaults Control Name
Clmp
Width
1 bit
Type
Write
Default
0
Bit(s)
7:0
Description
Clamp / Bias selection: 1 = Clamp, 0 = Bias
Clamp Control Register Map Register Name
CLAMP1 CLAMP2
Address
0x1D 0x1E
Bit 7
Clmp8 Resv'd
Bit 6
Clmp7 Resv'd
Bit5
Clmp6 Resv'd
Bit4
Clmp5 Resv'd
Bit3
Clmp4 Clmp12
Bit2
Clmp3 Clmp11
Bit1
Clmp2 Clmp10
Bit0
Clmp1 Clmp9
Notes: 1. Power Down places the output in a high impedance state so multiple FMS6501 devices may be paralleled. Power Down also de-selects any input routed to the specified output. 2. When all inputs are OFF, the amplifier input will be tied to approximately 150mV and the output will go to approximately 300mV with the 6dB gain setting. 3. In4 is provided for forward compatibility and should always be written as `0' in the FMS6501.
4 FMS6501 Rev. 1A
www.fairchildsemi.com
FMS6501 12 Input 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
DC Electrical Characteristics
Tc = 25C, Vcc = 5V, Vin = 1Vpp, input bias mode, one-to-one routing, 6dB gain, all inputs AC coupled with 0.1uF, unused inputs AC-terminated through 75 to GND, all outputs AC coupled with 220uF into 150 loads, referenced to 400kHz; unless otherwise noted. Symbol
ICC VOUT ROFF Vclamp Vbias PSRR
Parameter
Supply Current1 Video Output Range Off Channel Output Impedance DC Output Level
1
Conditions
No load, all outputs enabled
Min.
Typ.
80 2.8
Max
100
Units
mA Vpp k
Output disabled Clamp mode Bias mode All channels, DC 0.2 1.15
3.0 0.3 1.25 50 0.4 1.35
V V dB
DC Output Level1 Power Supply Rejection Ratio
AC Electrical Characteristics
Tc = 25C, Vcc = 5V, Vin = 1Vpp, input bias mode, one-to-one routing, 6dB gain, all inputs AC coupled with 0.1uF, unused inputs AC-terminated through 75 to GND, all outputs AC coupled with 220uF into 150 loads, referenced to 400kHz; unless otherwise noted. Symbol
AVSD AVSTEP f+1dB f-1dB fC dG dP THDSD THDHD XTALK1 XTALK2 XTALK3 XTALK4 XTALK5 SNRSD VNOISE AMPON Gain
Parameter
Channel Gain1 Error Step1
Conditions
All Channels, All Gain Settings, DC All Channels, DC VOUT = 1.4Vpp VOUT = 1.4Vpp VOUT = 1.4Vpp 3.58MHz 3.58MHz VOUT = 1.4Vpp, 5MHz VOUT = 1.4Vpp, 22MHz 1MHz, VOUT = 2Vpp2 15MHz, VOUT = 2Vpp2 1MHz, VOUT = 2Vpp
3
Min.
-0.2 0.9
Typ.
0 1 65 90 115 0.1 0.2 0.05 0.6 -72 -50 -68 -61
Max
+0.2 1.1
Units
dB dB MHz MHz MHz % deg % % dB dB dB dB dB dB nV/rtHz ns
1dB Peaking Bandwidth -1dB Bandwidth -3dB Bandwidth Differential Gain Differential Phase SD Output Distortion HD Output Distortion Input Crosstalk Input Crosstalk Output Crosstalk Output Crosstalk Multi-Channel Crosstalk Signal-to-Noise Ratio5 Channel Noise Amplifier Recovery Time
15MHz, VOUT = 2Vpp3 Standard Video, VOUT = 2Vpp
4
-45 73 20 300
NTC-7 weighting, 4.2MHz LP, 100kHz HP 400kHz to 100MHz, Input referred Post I2C programming
Notes: 1. 100% tested at 25C. 2. Adjacent input pair to adjacent output pair. Interfering input is through an open switch. 3. Adjacent input pair to adjacent output pair. Interfering input is through a closed switch. 4. Crosstalk of eight synchronous switching outputs onto single, asynchronous switching output. 5. SNR = 20 * log (714mV / rms noise)
5 FMS6501 Rev. 1A
www.fairchildsemi.com
FMS6501 12 Input 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
I2C BUS Characteristics
Tc = 25C, Vcc = 5V; unless otherwise noted. Symbol
Vil Vih fscl tr tf tlow thigh tSU,DAT tHD,DAT tSU,STO tBUF tHD,STA tSU,STA Digital Input Low1 Digital Input High1
Parameter
Conditions
SDA, SCL, ADDR SDA, SCL, ADDR SCK 1.5V to 3V 1.5V to 3V
Min.
0 3.0
Typ.
Max
1.5
Units
V V kHz nS nS uS uS nS nS uS uS uS uS
Vcc
100 1000 300 4.7 4.0 300 0 4 4.7 4 4.7
Clock Frequency Input Rise Time Input Fall Time Clock Low Period Clock High Period Data Set-up Time Data Hold Time Set-up Time from Clock High to Stop Start Set-up Time following a Stop Start Hold Time Start Set-up Time following Clock Low to High
Notes: 1. 100% tested at 25C
SDA
tBUF tLOW
tf
SCL
tr
tSU,DAT
tHD,STA
tHD,DAT
tHIGH
SDA
tSU,STA
tSU,STO
Figure 1: I2C Bus Timing
6 FMS6501 Rev. 1A
www.fairchildsemi.com
FMS6501 12 Input 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
I2C Interface
Operation
The I2C compatible interface conforms to the I2C spec for Standard Mode. Individual addresses may be written. There is no read capability. The interface consists of two lines. These are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply through an external resistor. Data transfer may be initiated only when the bus is not busy. Bit Transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse. Changes in the data line during this time will be interpreted as a control signal.
SCL
SDA
Data line stable; data valid
Change of data allowed
Figure 2: Bit Transfer
Start and Stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line, while the clock is HIGH is defined as the stop condition (P).
SCL
S
P
SDA START condition STOP condition
Figure 3: Definition of START and STOP conditions.
7 FMS6501 Rev. 1A
www.fairchildsemi.com
FMS6501 12 Input 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Acknowledge The number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
START condition
clock pulse for acknowledgement
SCL FROM MASTER
1
2
8
9
DATA OUTPUT BY TRANSMITTER
DATA OUTPUT BY RECEIVER
Figure 4: Acknowledgement on the I2C Bus
I2C Bus Protocol Before any data is transmitted on the I2C bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The I2C bus configuration for a data write to the FMS6501 is shown below in figure 5:
1 SCL 9 1 9
SDA
A6
A5
A4
A3
A2
A1
A0
R/W ACK. BY FMS6501
D7
D6
D5
D4
D3
D2
D1
START BY MASTER
FRAME1 SERIAL BUS ADDRESS BYTE
FRAME 2 ADDRESS POINTER REGISTER BYTE 9
D0 07 ACK. BY FMS6501
1 SCL(CONTINUED)
SDA(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY FMS6501 STOP BY MASTER
FRAME 3 DATA BYTE
Figure 5: Write a register address to the pointer register, then write data to the selected register
8 FMS6501 Rev. 1A
www.fairchildsemi.com
FMS6501 12 Input 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Applications Information
Input Clamp / Bias Circuitry
The FMS6501 can accommodate either AC or DC coupled inputs. Internal clamping and bias circuitry are provided to support AC coupled inputs. These are selectable through the CLMP bits via the I2C compatible interface. For DC coupled inputs, the device should be programmed to use the 'bias' input configuration. In this configuration, the input is internally biased to 625mV through a 100k resistor. Distortion is optimized with the output levels set between 250mV above ground and 500mV below the power supply. These constraints along with the desired channel gain need to be considered when configuring the input signal levels for input DC coupling. With AC coupled inputs, the FMS6501 uses a simple clamp rather than a full DC-restore circuit. For video signals with and without sync, (Y,CV,R,G,B) the lowest voltage at the output pins will be clamped to approximately 300mV above ground when the 6dB gain setting is selected. If symmetric AC coupled input signals are used, (chroma,Pb,Pr,Cb,Cr) the bias circuit mentioned above can be used to center them within the input common range. The average DC value at the output will be approximately 1.27V with a 6dB gain setting. This value will change, depending upon the selected gain setting.
The following diagram shows the bias mode input circuit and the internally controlled voltage at the input pin for AC coupled inputs.
Average voltage set to 625mV 0.1uF
Video source must be AC-coupled.
75
FMS6501 Input Bias
Figure 2. Bias Mode Input Circuit
Output Configuration
The FMS6501 outputs may be either AC or DC coupled. Resistive output loads can be as low as 75, representing a dual, doubly terminated video load. High impedance, capacitive loads up to 20pF can also be driven without loss of signal integrity. For standard 75 video loads, a 75 matching resistor should be placed in series to allow for a doubly terminated load. DC coupled outputs should be connected as follows:
75
Gain Setting
6dB 7dB 8dB 9dB
Clamp Voltage
300mV 330mV 370mV 420mV
Bias Voltage
1.27V 1.43V 1.60V 1.80V
FMS6501 Output Amplifier
75
Figure 3. DC-Coupled Load Connection The following diagram shows the clamp mode input circuit and the internally controlled voltage at the input pin for AC coupled inputs:
Lowest voltage set to 125mV 0.1uF
Video source must be AC-coupled.
75
FMS6501 Input Clamp
If multiple, low impedance loads are DC coupled, increased power and thermal issues will need to be addressed. In this case, the use of a multilayer board with a large ground plane to help dissipate heat is recommended. If a 2 layer board is used under these conditions, use of an extended ground plane directly under the device is recommended. This plane should extend at least 0.5" beyond the device. Other PC board layout issues are covered in the Layout Considerations section below. AC-coupled loads should be configured as follows:
75
220uF
FMS6501 Output Amplifier
Figure 1. Clamp Mode Input Circuit
75
Figure 4. AC-Coupled Load Connection Thermal issues are significantly reduced with AC coupled outputs, alleviating the need for special PC layout requirements.
9 FMS6501 Rev. 1A
www.fairchildsemi.com
FMS6501 12 Input 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Each of the FMS6501 outputs can be independently powered down and placed in a high impedance state with the ENABLE bit. This function can be used to mute video signals, to parallel multiple FMS6501 outputs, or to save power. When the output amplifier is disabled, the high impedance output presents a 3k load to ground. The output amplifier will typically enter and recover from the power down state in less than 300ns after being programmed. When an output channel is not connected to an input, the input to that particular channels amplifier is forced to approximately 150mV. The output amplifier is still active, unless specifically disabled by the I2C interface. Voltage output levels will depend on the programmed gain for that channel.
For input crosstalk, the switch is open. All inputs are in bias mode. Channel 1 input is driven with a 1Vpp signal, while all other inputs are AC terminated with 75 ohms. All outputs are enabled, and crosstalk is measured from IN1 to any output. For output crosstalk, the switch is closed. Crosstalk from OUT1 to any output is measured. Crosstalk from multiple sources into a given channel was measured with the setup shown in figure 6. Here, Input In1 is driven with a 1Vpp pulse source and is connected to outputs Out1 to Out8. Input In9 is driven with a secondary, asynchronous gray field video signal, and is connected to Out9. All other inputs are AC terminated with 75 ohms. Crosstalk effects on the gray field are then measured and calculated with respect to a standard 1Vpp output measured at the load. If all inputs and outputs are not needed, avoid using adjacent channels where possible to reduce crosstalk. Disable all unused channels to further reduce crosstalk as well as power dissipation.
Crosstalk
Crosstalk is an important consideration when using the FMS6501. Input and output crosstalk are defined to represent the two major coupling modes that may be present in a typical application. Input crosstalk is crosstalk in the input pins and switches when the interfering signal drives an open switch. It is dominated by inductive coupling in the package lead frame between adjacent leads. It decreases rapidly as the interfering signal moves farther away from the pin adjacent to the input signal selected. Output crosstalk is coupling from one driven output to another active output. It decreases with increasing load impedance as it is caused mainly by ground and power coupling between output amplifiers. So if a signal is driving an open switch, its crosstalk will be mainly input crosstalk. If it is driving a load through an active output, its crosstalk will be mainly output crosstalk. Input and output crosstalk measurements are performed with the test configuration shown below:
TERMINATION IN1 Bias
IN1 driven with SD video 1Vpp. IN9 driven with asynchronous SD video 1Vpp. IN2-8, 10-12 are AC-term to GND w/75 ohms.
IN9
Bias
TERMINATION Bias IN1
IN12 Bias
IN2 - IN12 are AC-Term to Ground w/75 ohms IN1 = 1Vpp
OUT1
Measure Crosstalk from channels 1-8 into channel 9 OUT9
Open switch for input crosstalk. Close switch for output crosstalk.
Figure 6: Test Configuration for Multi-Channel Crosstalk
IN12
Bias
Gain = 6dB Out1 = 2.0Vpp
Input Crosstalk from IN1 to OUTx OUT1 Output Crosstalk from OUT1 to OUTx OUT9
Figure 5: Test Configuration for Crosstalk
10 FMS6501 Rev. 1A
www.fairchildsemi.com
FMS6501 12 Input 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Layout Considerations
General layout and supply bypassing play major roles in high frequency performance and thermal characteristics. Fairchild offers a demonstration board, FMS6501DEMO, to use as a guide for layout and to aid in device testing and characterization. The FMS6501DEMO is a 4-layer board with a full power and ground plane. For optimum results, follow the steps below as a basis for high frequency layout: * Include 10F and 0.1F bypass capacitors * Place the 10F capacitor within 0.75 inches of the power pin * Place the 0.1F capacitor within 0.1 inches of the power pin * Connect all external ground pins as tightly as possible, preferably with a large ground plane under the package. * Layout channel connections to reduce mutual trace inductance * Minimize all trace lengths to reduce series inductances. If routing across a board, place device such that longer traces are at the inputs rather than the outputs. If using multiple, low impedance DC coupled outputs, special layout techniques may be employed to help dissipate heat. If a multilayer board is used, a large ground plane directly under the device will help reduce package case temperature. For dual layer boards, an extended plane can be used. Worse case additional die power due to DC loading can be estimated at (Vcc2/4Rload) per output channel. This assumes a constant DC output voltage of Vcc/2. For 5V Vcc with a dual DC video load, add 25/(4*75) = 83mW, per channel.
Applications for the FMS6501 Video Switch Matrix
The increased demand for consumer multimedia systems has created a large challenge for system designers to provide costeffective solutions to capitalize on the growth potential in graphics display technologies. These applications will require cost effective video switching and filtering solutions to deploy highquality display technologies rapidly and effectively to the target audience. Areas of specific interest include HDTV, Media Centers, and Automotive Infotainment(includes navigation, in cabin entertainment, and back up camera). In all cases, the advantages the integrated video switch matrix provides are high quality video switching specific to the application as well as video input clamps and on chip low impedance output cable drivers with switchable gain. Generally the largest application for a video switch is for the front end of an HDTV. This is used to take multiple inputs and route them to their appropriate signal paths (main picture and picture in picture - PiP). These are normally routed into ADCs that are followed by decoders. There are many different technologies for HDTV including: LCD,Plasma, and CRT that have similar analog switching circuitry. An example of a potential HDTV application is shown in figure 7 below. This system combines a video switch matrix and 2 three channel switchable anti-aliasing filters. This is done as there are two 3-channel signal paths in the system - One is for the main picture, and the other is the path for "Picture in Picture".
VIPDEMOTM Control Software
The FMS6501 is configured via an I2C compatible digital interface. In order to facilitate ease of demonstration, Fairchild Semiconductor had developed the VIPDEMOTM GUI based control software to write to the FMS6501 register map. This software is included when ordering an FMS6501DEMO kit. Also included is a Parallel port I2C adapter and an interface cable to connect to the demo board. Besides using the full FMS6501 interface, the VIPDEMOTM can also be used to control single register read and writes for I2C. Figures 8 and 9 below show the control panel for the VIPDEMOTM control software and the FMS6501 device evaluation board.
11 FMS6501 Rev. 1A
www.fairchildsemi.com
FMS6501 12 Input 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Antenna CATV / Satellite
RF/Tuner
CVBS Main Picture FMS6501 Video Switch Matrix FMS6407 AntiAliasing Filter
Video Decoder Controller Chip Scaling Engine PCI Interface
CVBS
3
3
ADC
LVDS (Tx)
LVDS (Rx)
S-Video 1
2 2
S-Video 2
LCD Display
YPrPb (SD)
3 3 3 FMS6407 AntiAliasing Filter 3
Picture in Picture ADC
Video Decoder
YPrPb (HD)
Figure 7: HDTV Application using the FMS6501 Video Switch Matrix
Figure 8: Control Panel for VIPDEMOTM Control Software
12 FMS6501 Rev. 1A
www.fairchildsemi.com
FMS6501 12 Input 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Figure 9: FMS6501 Evaluation Board for use with the VIPDEMOTM Control Software.
13 FMS6501 Rev. 1A
www.fairchildsemi.com
FMS6501 12 Input 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Mechanical Dimensions
14
www.fairchildsemi.com
FMS6501 Rev. 1A
FMS6501 12 Input 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Ordering Information
Model Part Number Lead Free Yes Yes Package SSOP-28 SSOP-28 Container Rail Reel Pack Qty 47 2000
FMS6501 FMS6501MSA28 FMS6501 FMS6501MSA28X
Temperature range for all parts: 0C to 85C.
15 FMS6501 Rev. 1A
www.fairchildsemi.com
FMS6501 12 Input 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM FACT Quiet SeriesTM ActiveArrayTM FAST(R) BottomlessTM FASTrTM CoolFETTM FPSTM CROSSVOLTTM FRFETTM DOMETM GlobalOptoisolatorTM EcoSPARKTM GTOTM E2CMOSTM HiSeCTM EnSignaTM I2CTM FACTTM ImpliedDisconnectTM Across the board. Around the world.TM The Power FranchiseTM Programmable Active DroopTM
DISCLAIMER
ISOPLANARTM LittleFETTM MICROCOUPLERTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC(R) OPTOPLANARTM PACMANTM
POPTM Power247TM PowerTrench(R) QFET(R) QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SILENT SWITCHER(R) SMART STARTTM SPMTM StealthTM
SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic(R) TINYOPTOTM TruTranslationTM UHCTM UltraFET(R) VCXTM
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. I7
20 FMS6501 Rev. 1A
www.fairchildsemi.com

▲Up To Search▲

Price & Availability of FMS6501MSA28X

	To Download FMS6501MSA28X Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .