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Instruction Set Manual
for the C16x Family of Siemens 16-Bit CMOS Single-Chip Microcontrollers
Instruction Set Manual Version 1.2, 12.97
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Version 1.2, 12.97 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
C166 Family Microcontroller Instruction Set Manual Revision History: Version 1.2, 12.97 Previous Releases: Page 8 35 38 43, 44 51 67 75 77 81 86, 87 95 104 108 Subjects BFLD* code size corrected ADDCB: spelling corrected ASHR: "operation" corrected BFLD*: Note improved, format corrected CALLI: "operation" corrected EINIT: Syntax corrected JBC: Condition flags corrected JMPI: "operation" corrected JNBS: Condition flags corrected MUL(U): Flag N corrected PRIOR: "Operation" corrected SCXT: Data Type added SRVWDT: Syntax corrected Version 1.1, 09.95 03.94
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C166 Family Instruction Set Table of Contents
Table of Contents 1 2 3 4 5 6 7
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Short Instruction Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Instruction Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Instruction State Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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C166 Family Instruction Set Introduction
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Introduction
The Siemens family of 16-bit microcontrollers offers devices that provide various levels of peripheral performance and programmability. This allows to equip each specific application with the microcontroller that fits best to the required functionality and performance. Still the Siemens family concept provides an easy path to upgrade existing applications or to climb the next level of performance in order to realize a subsequent more sophisticated design. Two major characteristics enable this upgrade path to save and reuse almost all of the engineering efforts that have been made for previous designs: * All family members are based on the same basic architecture * All family members execute the same instructions (except for upgrades for new members) The fact that all members execute the same instructions (almost) saves knowhow with respect to the understanding of the controller itself and also with respect to the used tools (assembler, disassembler, compiler, etc.). This instruction set manual provides an easy and direct access to the instructions of the Siemens 16-bit microcontrollers by listing them according to different criteria, and also unloads the technical manuals for the different devices from redundant information. This manual also describes the different addressing mechanisms and the relation between the logical addresses used in a program and the resulting physical addresses. There is also information provided to calculate the execution time for specific instructions depending on the used address locations and also specific exceptions to the standard rules. Description Levels In the following sections the instructions are compiled according to different criteria in order to provide different levels of precision: * Cross Reference Tables summarize all instructions in condensed tables * The Instruction Set Summary groups the individual instructions into functional groups * The Opcode Table references the instructions by their hexadecimal opcode * The Instruction Description describes each instruction in full detail
All instructions listed in this manual are executed by the following devices (new derivatives will be added to this list): C161V, C161K, C161O, C161RI, C161SI, C161CI, C163, C163F, C164CI, C165, C167, C167CR, C167SR, C167S, C167CS. A few instructions (ATOMIC and EXTended instructions) have been added for these devices and are not recognized by the following devices: SAB 80C166, SAB 80C166W, SAB 83C166, SAB 83C166W, SAB 88C166, SAB 88C166W. These differences are noted for each instruction, where applicable.
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C166 Family Instruction Set Short Instruction Summary
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Short Instruction Summary
The following compressed cross-reference tables quickly identify a specific instruction and provide basic information about it. Two ordering schemes are included: The first table (two pages) is a compressed cross-reference table that quickly identifies a specific hexadecimal opcode with the respective mnemonic. The second table lists the instructions by their mnemonic and identifies the addressing modes that may be used with a specific instruction and the instruction length depending on the selected addressing mode. This reference helps to optimize instruction sequences in terms of code size and/ or execution time.
* x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF
0x ADD ADDB ADD ADDB ADD ADDB ADD ADDB ADD ADDB BFLDL MUL ROL JMPR BCLR BSET
1x ADDC ADDCB ADDC ADDCB ADDC ADDCB ADDC ADDCB ADDC ADDCB BFLDH MULU ROL JMPR BCLR BSET
2x SUB SUBB SUB SUBB SUB SUBB SUB SUBB SUB SUBB BCMP PRIOR ROR JMPR BCLR BSET
3x SUBC SUBCB SUBC SUBCB SUBC SUBCB SUBC SUBCB SUBC SUBCB BMOVN ROR JMPR BCLR BSET
4x CMP CMPB CMP CMPB CMP CMPB CMP CMPB BMOV DIV SHL JMPR BCLR BSET
5x XOR XORB XOR XORB XOR XORB XOR XORB XOR XORB BOR DIVU SHL JMPR BCLR BSET
6x AND ANDB AND ANDB AND ANDB AND ANDB AND ANDB BAND DIVL SHR JMPR BCLR BSET
7x OR ORB OR ORB OR ORB OR ORB OR ORB BXOR DIVLU SHR JMPR BCLR BSET
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Note: Both ordering schemes (hexadecimal opcode and mnemonic) are provided in more detailled lists in the following sections of this manual.
Note: The ATOMIC and EXTended instructions are not available in the SAB 8XC166(W) devices. They are marked in the cross-reference table.
8x x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF CMPI1 NEG CMPI1 MOV CMPI1 IDLE MOV MOVB JB JMPR BCLR BSET
9x CMPI2 CPL CMPI2 MOV CMPI2 PWRDN MOV MOVB JNB TRAP JMPI JMPR BCLR BSET
Ax CMPD1 NEGB CMPD1 MOVB DISWDT CMPD1 SRVWDT MOV MOVB JBC CALLI ASHR JMPR BCLR BSET
Bx CMPD2 CPLB CMPD2 MOVB EINIT CMPD2 SRST MOV MOVB JNBS CALLR ASHR JMPR BCLR BSET
Cx MOVBZ MOVBZ MOV MOVBZ SCXT MOV MOVB CALLA RET NOP JMPR BCLR BSET
Dx MOVBS
Ex MOV MOVB PCALL MOVB MOV MOVB MOV MOVB JMPA RETP PUSH JMPR BCLR BSET
Fx MOV MOVB MOV MOVB MOVB MOV MOVB JMPS RETI POP JMPR BCLR BSET
AT/EXTR
MOVBS MOV MOVBS SCXT
EXTP/S/R
MOV MOVB CALLS RETS
EXTP/S/R
JMPR BCLR BSET
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C166 Family Instruction Set Short Instruction Summary
Mnemonic ADD[B] ADDC[B] AND[B] OR[B] SUB[B] SUBC[B] XOR[B] ASHR ROL / ROR SHL / SHR BAND BCMP BMOV BMOVN BOR / BXOR BCLR BSET BFLDH BFLDL MOV[B]
Addressing ModesBytes Rwn Rwm Rwn [Rwi] Rwn [Rwi+] Rwn #data3 reg reg mem Rwn Rwn bitaddrZ.z #data16 mem reg Rwm #data4 bitaddrQ.q
1) 1) 1) 1) 2)
2 2 2 2 4 4 4 2 2 4
Mnemonic CPL[B] NEG[B] DIV DIVL DIVLU DIVU MUL MULU CMPD1/2 CMPI1/2 CMP[B]
Addressing ModesBytes Rwn Rwn
1)
2 2
Rwn Rwn Rwn Rwn Rwn Rwn Rwn Rwn reg reg cc cc seg rel cc bitaddrQ.q
Rwm #data4 #data16 mem Rwm [Rwi] [Rwi+] #data3 #data16 mem caddr [Rwn] caddr
2 2 4 4 2 2 2 2 4 4 4 2 4 2 2 4
1) 1) 1) 1) 2)
bitaddrQ.q bitoffQ Rwn Rwn Rwn Rwn [Rwm] [-Rwm] [Rwn] [Rwn+] [Rwn] reg Rwn [Rwm+#d16] [Rwn] mem reg mem Rwn reg mem Rwm #seg -
2 #mask8 #data8 4 Rwm #data4 [Rwm] [Rwm+] Rwn Rwn [Rwm] [Rwm] [Rwm+] #data16 [Rwm+#d16] Rwn mem [Rwn] mem reg Rbm mem reg #irang2 #irang2
1) 1) 1) 1) 1) 1)
2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 2 4 4 2 4 2
2) 1) 1)
CALLA JMPA CALLI JMPI CALLS JMPS CALLR JMPR JB JBC JNB JNBS PCALL POP PUSH RETP SCXT PRIOR TRAP ATOMIC EXTR EXTP EXTPR SRST/IDLE PWRDN SRVWDT DISWDT EINIT
rel rel
reg reg reg reg Rwn #trap7 #irang2 Rwm #pag -
caddr
4 2 4 4 2
3)
#data16 mem Rwm
MOVBS MOVBZ EXTS EXTSR NOP RET RETI RETS
1) 2)
2 2 2 4 4
3)
#irang2 #irang2
3)
Byte oriented instructions (suffix `B') use Rb instead of Rw (not with [Rwn]!). Byte oriented instructions (suffix `B') use #data8 instead of #data16. 3) The ATOMIC and EXTended instructions are not available in the SAB 8XC166(W) devices.
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Instruction Set Summary
This chapter summarizes the instructions by listing them according to their functional class. This allows to identify the right instruction(s) for a specific required function.
The following notes apply to this summary:
Data Addressing Modes Rw: Rb: reg: mem: [...]: - Word GPR (R0, R1, ... , R15) - Byte GPR (RL0, RH0, ..., RL7, RH7) - SFR or GPR (in case of a byte operation on an SFR, only the low byte can be accessed via `reg') - Direct word or byte memory location - Indirect word or byte memory location (Any word GPR can be used as indirect address pointer, except for the arithmetic, logical and compare instructions, where only R0 to R3 are allowed) - Direct bit in the bit-addressable memory area - Direct word in the bit-addressable memory area - Immediate constant (The number of significant bits which can be specified by the user is represented by the respective appendix 'x') - Immediate 8-bit mask used for bit-field modifications
bitaddr: bitoff: #data:
#mask8:
Multiply and Divide Operations The MDL and MDH registers are implicit source and/or destination operands of the multiply and divide instructions. Branch Target Addressing Modes caddr: seg: rel: #trap7: - Direct 16-bit jump target address (Updates the Instruction Pointer) - Direct 2-bit segment address (Updates the Code Segment Pointer) - Signed 8-bit jump target word offset address relative to the Instruction Pointer of the following instruction - Immediate 7-bit trap or interrupt number.
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Extension Operations The EXT* instructions override the standard DPP addressing scheme: #pag10: #seg8: - Immediate 10-bit page address. - Immediate 8-bit segment address.
Note: The EXTended instructions are not available in the SAB 8XC166(W) devices.
Branch Condition Codes cc: Symbolically specifiable condition codes cc_UC cc_Z cc_NZ cc_V cc_NV cc_N cc_NN cc_C cc_NC cc_EQ cc_NE cc_ULT cc_ULE cc_UGE cc_UGT cc_SLE cc_SGE cc_SGT cc_NET - - - - - - - - - - - - - - - - - - - Unconditional Zero Not Zero Overflow No Overflow Negative Not Negative Carry No Carry Equal Not Equal Unsigned Less Than Unsigned Less Than or Equal Unsigned Greater Than or Equal Unsigned Greater Than Signed Less Than or Equal Signed Greater Than or Equal Signed Greater Than Not Equal and Not End-of-Table
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Instruction Set Summary Mnemonic Arithmetic Operations ADD ADD ADD ADD ADD ADD ADD ADDB ADDB ADDB ADDB ADDB ADDB ADDB ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDCB ADDCB ADDCB ADDCB ADDCB ADDCB Rw, Rw Rw, [Rw] Rw, [Rw +] Rw, #data3 reg, #data16 reg, mem mem, reg Rb, Rb Rb, [Rw] Rb, [Rw +] Rb, #data3 reg, #data8 reg, mem mem, reg Rw, Rw Rw, [Rw] Rw, [Rw +] Rw, #data3 reg, #data16 reg, mem mem, reg Rb, Rb Rb, [Rw] Rb, [Rw +] Rb, #data3 reg, #data8 reg, mem Add direct word GPR to direct GPR Add indirect word memory to direct GPR Add indirect word memory to direct GPR and postincrement source pointer by 2 Add immediate word data to direct GPR Add immediate word data to direct register Add direct word memory to direct register Add direct word register to direct memory Add direct byte GPR to direct GPR Add indirect byte memory to direct GPR Add indirect byte memory to direct GPR and post-increment source pointer by 1 Add immediate byte data to direct GPR Add immediate byte data to direct register Add direct byte memory to direct register Add direct byte register to direct memory Add direct word GPR to direct GPR with Carry Add indirect word memory to direct GPR with Carry Add indirect word memory to direct GPR with Carry and post-increment source pointer by 2 Add immediate word data to direct GPR with Carry Add immediate word data to direct register with Carry Add direct word memory to direct register with Carry Add direct word register to direct memory with Carry Add direct byte GPR to direct GPR with Carry Add indirect byte memory to direct GPR with Carry Add indirect byte memory to direct GPR with Carry and post-increment source pointer by 1 Add immediate byte data to direct GPR with Carry Add immediate byte data to direct register with Carry Add direct byte memory to direct register with Carry 2 2 2 2 4 4 4 2 2 2 2 4 4 4 2 2 2 2 4 4 4 2 2 2 2 4 4 Description Bytes
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Instruction Set Summary (cont'd)* Mnemonic Description Bytes
Arithmetic Operations (cont'd) ADDCB SUB SUB SUB SUB SUB SUB SUB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBC SUBC SUBC SUBC SUBC SUBC SUBC SUBCB SUBCB SUBCB SUBCB SUBCB mem, reg Rw, Rw Rw, [Rw] Rw, [Rw +] Rw, #data3 reg, #data16 reg, mem mem, reg Rb, Rb Rb, [Rw] Rb, [Rw +] Rb, #data3 reg, #data8 reg, mem mem, reg Rw, Rw Rw, [Rw] Rw, [Rw +] Rw, #data3 reg, #data16 reg, mem mem, reg Rb, Rb Rb, [Rw] Rb, [Rw +] Rb, #data3 reg, #data8 Add direct byte register to direct memory with Carry Subtract direct word GPR from direct GPR Subtract indirect word memory from direct GPR Subtract indirect word memory from direct GPR and post-increment source pointer by 2 Subtract immediate word data from direct GPR Subtract immediate word data from direct register Subtract direct word memory from direct register Subtract direct word register from direct memory Subtract direct byte GPR from direct GPR Subtract indirect byte memory from direct GPR Subtract indirect byte memory from direct GPR and post-increment source pointer by 1 Subtract immediate byte data from direct GPR Subtract immediate byte data from direct register Subtract direct byte memory from direct register Subtract direct byte register from direct memory Subtract direct word GPR from direct GPR with Carry Subtract indirect word memory from direct GPR with Carry Subtract indirect word memory from direct GPR with Carry and post-increment source pointer by 2 Subtract immediate word data from direct GPR with Carry Subtract immediate word data from direct register with Carry 4 2 2 2 2 4 4 4 2 2 2 2 4 4 4 2 2 2 2 4
Subtract direct word memory from direct register with Carry 4 Subtract direct word register from direct memory with Carry 4 Subtract direct byte GPR from direct GPR with Carry Subtract indirect byte memory from direct GPR with Carry Subtract indirect byte memory from direct GPR with Carry and post-increment source pointer by 1 Subtract immediate byte data from direct GPR with Carry 2 2 2 2
Subtract immediate byte data from direct register with Carry 4
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Instruction Set Summary (cont'd)* Mnemonic Description Bytes
Arithmetic Operations (cont'd) SUBCB SUBCB MUL MULU DIV DIVL DIVLU DIVU CPL CPLB NEG NEGB reg, mem mem, reg Rw, Rw Rw, Rw Rw Rw Rw Rw Rw Rb Rw Rb Subtract direct byte memory from direct register with Carry Subtract direct byte register from direct memory with Carry Signed multiply direct GPR by direct GPR (16-16-bit) Unsigned multiply direct GPR by direct GPR (16-16-bit) Signed divide register MDL by direct GPR (16-/16-bit) Signed long divide register MD by direct GPR (32-/16-bit) Unsigned long divide register MD by direct GPR (32-/16-bit) Unsigned divide register MDL by direct GPR (16-/16-bit) Complement direct word GPR Complement direct byte GPR Negate direct word GPR Negate direct byte GPR 4 4 2 2 2 2 2 2 2 2 2 2
Logical Instructions AND AND AND AND AND AND AND ANDB ANDB ANDB ANDB ANDB ANDB ANDB Rw, Rw Rw, [Rw] Rw, [Rw +] Rw, #data3 reg, #data16 reg, mem mem, reg Rb, Rb Rb, [Rw] Rb, [Rw +] Rb, #data3 reg, #data8 reg, mem mem, reg Bitwise AND direct word GPR with direct GPR Bitwise AND indirect word memory with direct GPR Bitwise AND indirect word memory with direct GPR and post-increment source pointer by 2 Bitwise AND immediate word data with direct GPR Bitwise AND immediate word data with direct register Bitwise AND direct word memory with direct register Bitwise AND direct word register with direct memory Bitwise AND direct byte GPR with direct GPR Bitwise AND indirect byte memory with direct GPR Bitwise AND indirect byte memory with direct GPR and post-increment source pointer by 1 Bitwise AND immediate byte data with direct GPR Bitwise AND immediate byte data with direct register Bitwise AND direct byte memory with direct register Bitwise AND direct byte register with direct memory 2 2 2 2 4 4 4 2 2 2 2 4 4 4
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Instruction Set Summary (cont'd)* Mnemonic Logical Instructions (cont'd) OR OR OR OR OR OR OR ORB ORB ORB ORB ORB ORB ORB XOR XOR XOR XOR XOR XOR XOR XORB XORB XORB XORB XORB XORB XORB Rw, Rw Rw, [Rw] Rw, [Rw +] Rw, #data3 reg, #data16 reg, mem mem, reg Rb, Rb Rb, [Rw] Rb, [Rw +] Rb, #data3 reg, #data8 reg, mem mem, reg Rw, Rw Rw, [Rw] Rw, [Rw +] Rw, #data3 reg, #data16 reg, mem mem, reg Rb, Rb Rb, [Rw] Rb, [Rw +] Rb, #data3 reg, #data8 reg, mem mem, reg Bitwise OR direct word GPR with direct GPR Bitwise OR indirect word memory with direct GPR Bitwise OR indirect word memory with direct GPR and post-increment source pointer by 2 Bitwise OR immediate word data with direct GPR Bitwise OR immediate word data with direct register Bitwise OR direct word memory with direct register Bitwise OR direct word register with direct memory Bitwise OR direct byte GPR with direct GPR Bitwise OR indirect byte memory with direct GPR Bitwise OR indirect byte memory with direct GPR and post-increment source pointer by 1 Bitwise OR immediate byte data with direct GPR Bitwise OR immediate byte data with direct register Bitwise OR direct byte memory with direct register Bitwise OR direct byte register with direct memory Bitwise XOR direct word GPR with direct GPR Bitwise XOR indirect word memory with direct GPR Bitwise XOR indirect word memory with direct GPR and post-increment source pointer by 2 Bitwise XOR immediate word data with direct GPR Bitwise XOR immediate word data with direct register Bitwise XOR direct word memory with direct register Bitwise XOR direct word register with direct memory Bitwise XOR direct byte GPR with direct GPR Bitwise XOR indirect byte memory with direct GPR Bitwise XOR indirect byte memory with direct GPR and post-increment source pointer by 1 Bitwise XOR immediate byte data with direct GPR Bitwise XOR immediate byte data with direct register Bitwise XOR direct byte memory with direct register Bitwise XOR direct byte register with direct memory 2 2 2 2 4 4 4 2 2 2 2 4 4 4 2 2 2 2 4 4 4 2 2 2 2 4 4 4 Description Bytes
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Instruction Set Summary (cont'd)* Mnemonic Description Bytes
Boolean Bit Manipulation Operations BCLR BSET BMOV BMOVN BAND BOR BXOR BCMP BFLDH BFLDL CMP CMP CMP CMP CMP CMP CMPB CMPB CMPB CMPB CMPB CMPB bitaddr bitaddr bitaddr, bitaddr bitaddr, bitaddr bitaddr, bitaddr bitaddr, bitaddr bitaddr, bitaddr bitaddr, bitaddr bitoff, #mask8, #data8 bitoff, #mask8, #data8 Rw, Rw Rw, [Rw] Rw, [Rw +] Rw, #data3 reg, #data16 reg, mem Rb, Rb Rb, [Rw] Rb, [Rw +] Rb, #data3 reg, #data8 reg, mem Clear direct bit Set direct bit Move direct bit to direct bit Move negated direct bit to direct bit AND direct bit with direct bit OR direct bit with direct bit XOR direct bit with direct bit Compare direct bit to direct bit Bitwise modify masked high byte of bit-addressable direct word memory with immediate data Bitwise modify masked low byte of bit-addressable direct word memory with immediate data Compare direct word GPR to direct GPR Compare indirect word memory to direct GPR Compare indirect word memory to direct GPR and post-increment source pointer by 2 Compare immediate word data to direct GPR Compare immediate word data to direct register Compare direct word memory to direct register Compare direct byte GPR to direct GPR Compare indirect byte memory to direct GPR Compare indirect byte memory to direct GPR and post-increment source pointer by 1 Compare immediate byte data to direct GPR Compare immediate byte data to direct register Compare direct byte memory to direct register 2 2 4 4 4 4 4 4 4 4 2 2 2 2 4 4 2 2 2 2 4 4
Compare and Loop Control Instructions CMPD1 CMPD1 Rw, #data4 Rw, #data16 Compare immediate word data to direct GPR and decrement GPR by 1 Compare immediate word data to direct GPR and decrement GPR by 1 2 4
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Instruction Set Summary (cont'd)* Mnemonic Description Bytes
Compare and Loop Control Instructions (cont'd) CMPD1 CMPD2 CMPD2 CMPD2 CMPI1 CMPI1 CMPI1 CMPI2 CMPI2 CMPI2 Rw, mem Rw, #data4 Rw, #data16 Rw, mem Rw, #data4 Rw, #data16 Rw, mem Rw, #data4 Rw, #data16 Rw, mem Compare direct word memory to direct GPR and decrement GPR by 1 Compare immediate word data to direct GPR and decrement GPR by 2 Compare immediate word data to direct GPR and decrement GPR by 2 Compare direct word memory to direct GPR and decrement GPR by 2 Compare immediate word data to direct GPR and increment GPR by 1 Compare immediate word data to direct GPR and increment GPR by 1 Compare direct word memory to direct GPR and increment GPR by 1 Compare immediate word data to direct GPR and increment GPR by 2 Compare immediate word data to direct GPR and increment GPR by 2 Compare direct word memory to direct GPR and increment GPR by 2 4 2 4 4 2 4 4 2 4 4
Prioritize Instruction PRIOR Rw, Rw Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR 2
Shift and Rotate Instructions SHL SHL SHR Rw, Rw Rw, #data4 Rw, Rw Shift left direct word GPR; number of shift cycles specified by direct GPR Shift left direct word GPR; number of shift cycles specified by immediate data Shift right direct word GPR; number of shift cycles specified by direct GPR 2 2 2
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Instruction Set Summary (cont'd)* Mnemonic Description Bytes
Shift and Rotate Instructions (cont'd) SHR ROL ROL ROR ROR ASHR ASHR Rw, #data4 Rw, Rw Rw, #data4 Rw, Rw Rw, #data4 Rw, Rw Rw, #data4 Shift right direct word GPR; number of shift cycles specified by immediate data Rotate left direct word GPR; number of shift cycles specified by direct GPR Rotate left direct word GPR; number of shift cycles specified by immediate data Rotate right direct word GPR; number of shift cycles specified by direct GPR Rotate right direct word GPR; number of shift cycles specified by immediate data Arithmetic (sign bit) shift right direct word GPR; number of shift cycles specified by direct GPR Arithmetic (sign bit) shift right direct word GPR; number of shift cycles specified by immediate data 2 2 2 2 2 2 2
Data Movement MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV Rw, Rw Rw, #data4 reg, #data16 Rw, [Rw] Rw, [Rw +] [Rw], Rw [-Rw], Rw [Rw], [Rw] [Rw +], [Rw] [Rw], [Rw +] Rw, [Rw + #data16] [Rw + #data16], Rw Move direct word GPR to direct GPR Move immediate word data to direct GPR Move immediate word data to direct register Move indirect word memory to direct GPR Move indirect word memory to direct GPR and post-increment source pointer by 2 Move direct word GPR to indirect memory Pre-decrement destination pointer by 2 and move direct word GPR to indirect memory Move indirect word memory to indirect memory Move indirect word memory to indirect memory and post-increment destination pointer by 2 Move indirect word memory to indirect memory and post-increment source pointer by 2 Move indirect word memory by base plus constant to direct GPR Move direct word GPR to indirect memory by base plus constant 2 2 4 2 2 2 2 2 2 2 4 4
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C166 Family Instruction Set Instruction Set Summary
Instruction Set Summary (cont'd)* Mnemonic Data Movement (cont'd) MOV MOV MOV MOV MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVBS MOVBS MOVBS [Rw], mem mem, [Rw] reg, mem mem, reg Rb, Rb Rb, #data4 reg, #data8 Rb, [Rw] Rb, [Rw +] [Rw], Rb [-Rw], Rb [Rw], [Rw] [Rw +], [Rw] [Rw], [Rw +] Rb, [Rw + #data16] [Rw + #data16], Rb [Rw], mem mem, [Rw] reg, mem mem, reg Rw, Rb reg, mem mem, reg Move direct word memory to indirect memory Move indirect word memory to direct memory Move direct word memory to direct register Move direct word register to direct memory Move direct byte GPR to direct GPR Move immediate byte data to direct GPR Move immediate byte data to direct register Move indirect byte memory to direct GPR Move indirect byte memory to direct GPR and post-increment source pointer by 1 Move direct byte GPR to indirect memory Pre-decrement destination pointer by 1 and move direct byte GPR to indirect memory Move indirect byte memory to indirect memory Move indirect byte memory to indirect memory and post-increment destination pointer by 1 Move indirect byte memory to indirect memory and post-increment source pointer by 1 Move indirect byte memory by base plus constant to direct GPR Move direct byte GPR to indirect memory by base plus constant Move direct byte memory to indirect memory Move indirect byte memory to direct memory Move direct byte memory to direct register Move direct byte register to direct memory Move direct byte GPR with sign extension to direct word GPR Move direct byte memory with sign extension to direct word register Move direct byte register with sign extension to direct word memory 4 4 4 4 2 2 4 2 2 2 2 2 2 2 4 4 4 4 4 4 2 4 4 Description Bytes
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Instruction Set Summary (cont'd)* Mnemonic Data Movement (cont'd) MOVBZ MOVBZ MOVBZ Rw, Rb reg, mem mem, reg Move direct byte GPR with zero extension to direct word GPR Move direct byte memory with zero extension to direct word register Move direct byte register with zero extension to direct word memory 2 4 4 Description Bytes
Jump and Call Operations JMPA JMPI JMPR JMPS JB JBC JNB JNBS CALLA CALLI CALLR CALLS PCALL TRAP cc, caddr cc, [Rw] cc, rel seg, caddr bitaddr, rel bitaddr, rel bitaddr, rel bitaddr, rel cc, caddr cc, [Rw] rel seg, caddr reg, caddr #trap7 Jump absolute if condition is met Jump indirect if condition is met Jump relative if condition is met Jump absolute to a code segment Jump relative if direct bit is set Jump relative and clear bit if direct bit is set Jump relative if direct bit is not set Jump relative and set bit if direct bit is not set Call absolute subroutine if condition is met Call indirect subroutine if condition is met Call relative subroutine Call absolute subroutine in any code segment Push direct word register onto system stack and call absolute subroutine Call interrupt service routine via immediate trap number 4 2 2 4 4 4 4 4 4 2 2 4 4 2
System Stack Operations POP PUSH SCXT SCXT reg reg reg, #data16 reg, mem Pop direct word register from system stack Push direct word register onto system stack Push direct word register onto system stack und update register with immediate data Push direct word register onto system stack und update register with direct memory 2 2 4 4
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Instruction Set Summary (cont'd)* Mnemonic Return Operations RET RETS RETP RETI System Control SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP EXTP EXTPR EXTPR EXTS EXTS EXTSR EXTSR #irang2 #irang2 Rw, #irang2 #pag10, #irang2 Rw, #irang2 #pag10, #irang2 Rw, #irang2 #seg8, #irang2 Rw, #irang2 #seg8, #irang2 Software Reset Enter Idle Mode Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page sequence Begin EXTended Page sequence Begin EXTended Page and Register sequence Begin EXTended Page and Register sequence Begin EXTended Segment sequence Begin EXTended Segment sequence Begin EXTended Segment and Register sequence Begin EXTended Segment and Register sequence
*) *) *) *) *) *) *) *) *) *)
Description
Bytes
Return from intra-segment subroutine Return from inter-segment subroutine reg Return from intra-segment subroutine and pop direct word register from system stack Return from interrupt service subroutine
2 2 2 2
4 4 4 4 4 4 2 2 2 4 2 4 2 4 2 4
Miscellaneous NOP Null operation 2
*)
The EXTended instructions are not available in the SAB 8XC166(W) devices.
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C166 Family Instruction Set Instruction Opcodes
4
Instruction Opcodes
The following pages list the instructions of the 16-bit microcontrollers ordered by their hexadecimal opcodes. This helps to identify specific instructions when reading executable code, ie. during the debugging phase.
Notes for Opcode Lists 1) These instructions are encoded by means of additional bits in the operand field of the instruction x0H - x7H: x8H - xBH: xCH - xFH: Rw, #data3 Rw, [Rw] Rw, [Rw +] or or or Rb, #data3 Rb, [Rw] Rb, [Rw +]
For these instructions only the lowest four GPRs, R0 to R3, can be used as indirect address pointers. 2) These instructions are encoded by means of additional bits in the operand field of the instruction 00xx.xxxxB: 01xx.xxxxB: 10xx.xxxxB: 11xx.xxxxB: EXTS EXTP EXTSR EXTPR or or ATOMIC EXTR
The ATOMIC and EXTended instructions are not available in the SAB 8XC166(W) devices. Notes on the JMPR Instructions The condition code to be tested for the JMPR instructions is specified by the opcode. Two mnemonic representation alternatives exist for some of the condition codes. Notes on the BCLR and BSET Instructions The position of the bit to be set or to be cleared is specified by the opcode. The operand `bitoff.n' (n = 0 to 15) refers to a particular bit within a bit-addressable word. Notes on the Undefined Opcodes A hardware trap occurs when one of the undefined opcodes signified by `----' is decoded by the CPU.
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Hexcode 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
Number of Bytes 2 2 4 4 4 4 4 4 2 2 4 2 2 2 2 2 2 2 4 4 4 4 4 4 2 2 4 2 2 2 2 2
Mnemonic
Operands
ADD ADDB ADD ADDB ADD ADDB ADD ADDB ADD ADDB BFLDL MUL ROL JMPR BCLR BSET ADDC ADDCB ADDC ADDCB ADDC ADDCB ADDC ADDCB ADDC ADDCB BFLDH MULU ROL JMPR BCLR BSET
Rw, Rw Rb, Rb reg, mem reg, mem mem, reg mem, reg reg, #data16 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitoff, #mask8, #data8 Rw, Rw Rw, Rw cc_UC, rel bitoff.0 bitoff.0 Rw, Rw Rb, Rb reg, mem reg, mem mem, reg mem, reg reg, #data16 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitoff, #mask8, #data8 Rw, Rw Rw, #data4 cc_NET, rel bitoff.1 bitoff.1
Hex- Numcode ber of Bytes 20 2 21 2 22 4 23 4 24 4 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 4 4 4 2 2 4 2 2 2 2 2 2 2 4 4 4 4 4 4 2 2 4 2 2 2 2
Mnemonic
Operands
SUB SUBB SUB SUBB SUB SUBB SUB SUBB SUB SUBB BCMP PRIOR ROR JMPR BCLR BSET SUBC SUBCB SUBC SUBCB SUBC SUBCB SUBC SUBCB SUBC SUBCB BMOVN ROR JMPR BCLR BSET
Rw, Rw Rb, Rb reg, mem reg, mem mem, reg mem, reg reg, #data16 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitaddr, bitaddr Rw, Rw Rw, Rw cc_EQ, rel or cc_Z, rel bitoff.2 bitoff.2 Rw, Rw Rb, Rb reg, mem reg, mem mem, reg mem, reg reg, #data16 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitaddr, bitaddr Rw, #data4 cc_NE, rel or cc_NZ, rel bitoff.3 bitoff.3
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Hexcode 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F
Number of Bytes 2 2 4 4 4 4 2 2 4 2 2 2 2 2 2 2 4 4 4 4 4 4 2 2 4 2 2 2 2 2
Mnemonic
Operands
CMP CMPB CMP CMPB CMP CMPB CMP CMPB BMOV DIV SHL JMPR BCLR BSET XOR XORB XOR XORB XOR XORB XOR XORB XOR XORB BOR DIVU SHL JMPR BCLR BSET
Rw, Rw Rb, Rb reg, mem reg, mem reg, #data16 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitaddr, bitaddr Rw Rw, Rw cc_V, rel bitoff.4 bitoff.4 Rw, Rw Rb, Rb reg, mem reg, mem mem, reg mem, reg reg, #data16 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitaddr, bitaddr Rw Rw, #data4 cc_NV, rel bitoff.5 bitoff.5
Hex- Numcode ber of Bytes 60 2 61 2 62 4 63 4 64 4 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 4 4 4 2 2 4 2 2 2 2 2 2 2 4 4 4 4 4 4 2 2 4 2 2 2 2 2
Mnemonic
Operands
AND ANDB AND ANDB AND ANDB AND ANDB AND ANDB BAND DIVL SHR JMPR BCLR BSET OR ORB OR ORB OR ORB OR ORB OR ORB BXOR DIVLU SHR JMPR BCLR BSET
Rw, Rw Rb, Rb reg, mem reg, mem mem, reg mem, reg reg, #data16 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitaddr, bitaddr Rw Rw, Rw cc_N, rel bitoff.6 bitoff.6 Rw, Rw Rb, Rb reg, mem reg, mem mem, reg mem, reg reg, #data16 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitaddr, bitaddr Rw Rw, #data4 cc_NN, rel bitoff.7 bitoff.7
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Hexcode 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F
Number of Bytes 2 2 4 4 4 4 2 2 4 2 2 2 2 2 4 4 4 4 2 2 4 2 2 2 2 2
Mnemonic
Operands
CMPI1 NEG CMPI1 MOV CMPI1 IDLE MOV MOVB JB JMPR BCLR BSET CMPI2 CPL CMPI2 MOV CMPI2 PWRDN MOV MOVB JNB TRAP JMPI JMPR BCLR BSET
Rw, #data4 Rw Rw, mem [Rw], mem Rw, #data16 [-Rw], Rw [-Rw], Rb bitaddr, rel cc_C, rel or cc_ULT, rel bitoff.8 bitoff.8 Rw, #data4 Rw Rw, mem mem, [Rw] Rw, #data16
Hex- Numcode ber of Bytes A0 2 A1 2 A2 4 A3 A4 4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF 4 4 4 2 2 4 2 2 2 2 2 2 2 4 4 4 4 4 2 2 4 2 2 2 2 2
Mnemonic
Operands
CMPD1 NEGB CMPD1 MOVB DISWDT CMPD1 SRVWDT MOV MOVB JBC CALLI ASHR JMPR BCLR BSET CMPD2 CPLB CMPD2 MOVB EINIT CMPD2 SRST MOV MOVB JNBS CALLR ASHR JMPR BCLR BSET
Rw, #data4 Rb Rw, mem [Rw], mem
Rw, #data16 Rw, [Rw] Rb, [Rw] bitaddr, rel cc, [Rw] Rw, Rw cc_SGT, rel bitoff.10 bitoff.10 Rw, #data4 Rb Rw, mem mem, [Rw]
Rw, #data16
Rw, [Rw+] Rb, [Rw+] bitaddr, rel #trap7 cc, [Rw] cc_NC, rel or cc_UGE, rel bitoff.9 bitoff.9
[Rw], Rw [Rw], Rb bitaddr, rel rel Rw, #data4 cc_SLE, rel bitoff.11 bitoff.11
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Hexcode C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
Number of Bytes 2 4 4 4 4 2 2 4 2 2 2 2 2 2 2 4 4 4 4 4 2 2 4 2 2 2 2 2
Mnemonic
Operands
MOVBZ MOVBZ MOV MOVBZ SCXT MOV MOVB CALLA RET NOP JMPR BCLR BSET MOVBS ATOMIC or EXTR MOVBS MOV MOVBS SCXT EXTP(R), EXTS(R) MOV MOVB CALLS RETS EXTP(R), EXTS(R) JMPR BCLR BSET
Rw, Rb reg, mem [Rw+#data16], Rw mem, reg reg, #data16 [Rw], [Rw] [Rw], [Rw] cc, addr
Hex- Numcode ber of Bytes E0 2 E1 2 E2 4 E3 E4 4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF 4 4 2 2 4 2 2 2 2 2 2 2 4 4 4 4 4 4 2 2 2 2 2
Mnemonic
Operands
MOV MOVB PCALL MOVB MOV MOVB MOV MOVB JMPA RETP PUSH JMPR BCLR BSET MOV MOVB MOV MOVB MOVB MOV MOVB JMPS RETI POP JMPR BCLR BSET
Rw, #data4 Rb, #data4 reg, caddr [Rw+#data16], Rb reg, #data16 reg, #data8 [Rw], [Rw+] [Rw], [Rw+] cc, caddr reg reg cc_UGT, rel bitoff.14 bitoff.14 Rw, Rw Rb, Rb reg, mem reg, mem Rb, [Rw + #data16] mem, reg mem, reg seg, caddr
cc_SLT, rel bitoff.12 bitoff.12 Rw, Rb #irang2 2) reg, mem Rw, [Rw + #data16] mem, reg reg, mem #pag10,#irang2 #seg8, #irang2
2)
[Rw+], [Rw] [Rw+], [Rw] seg, caddr
Rw, #irang2 2) cc_SGE, rel bitoff.13 bitoff.13
reg cc_ULE, rel bitoff.15 bitoff.15
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5
Instruction Description
This chapter describes each instruction in detail. The instructions are ordered alphabetically, and the description contains the following elements:
*Instruction Name* Specifies the mnemonic opcode of the instruction in oversized bold lettering for easy reference. The mnemonics have been chosen with regard to the particular operation which is performed by the specified instruction.
*Syntax* Specifies the mnemonic opcode and the required formal operands of the instruction as used in the following subsection 'Operation'. There are instructions with either none, one, two or three operands, which must be separated from each other by commas: MNEMONIC {op1 {,op2 {,op3 } } }
The syntax for the actual operands of an instruction depends on the selected addressing mode. All of the addressing modes available are summarized at the end of each single instruction description. In contrast to the syntax for the instructions described in the following, the assembler provides much more flexibility in writing C166 Family programs (e.g. by generic instructions and by automatically selecting appropriate addressing modes whenever possible), and thus it eases the use of the instruction set. For more information about this item please refer to the Assembler manual.
*Operation* This part presents a logical description of the operation performed by an instruction by means of a symbolic formula or a high level language construct. The following symbols are used to represent data movement, arithmetic or logical operators.
Diadic operations: (opX) + * / mod (opY) (opX) (opY) (opX) (opX) (opX) (opX) (opX) (opX) (opX) is is is is is is is is is is
operator (opY) MOVED into (opX) ADDED to (opY) SUBTRACTED from (opX) MULTIPLIED by (opY) DIVIDED by (opY) logically ANDed with (opY) logically ORed with (opY) logically EXCLUSIVELY ORed with (opY) COMPARED against (opY) divided MODULO (opY) operator (opX) logically COMPLEMENTED
Monadic operations: (opX)
is
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C166 Family Instruction Set Instruction Description
Missing or existing parentheses signify whether the used operand specifies an immediate constant value, an address or a pointer to an address as follows:
opX (opX) (opXn) ((opX))
Specifies the immediate constant value of opX Specifies the contents of opX Specifies the contents of bit n of opX Specifies the contents of the contents of opX (ie. opX is used as pointer to the actual operand)
The following operands will also be used in the operational description: CP CSP IP MD MDL, MDH PSW SP SYSCON C V SGTDIS count Context Pointer register Code Segment Pointer register Instruction Pointer Multiply/Divide register (32 bits wide, consists of MDH and MDL) Multiply/Divide Low and High registers (each 16 bit wide ) Program Status Word register System Stack Pointer register System Configuration register Carry condition flag in the PSW register Overflow condition flag in the PSW register Segmentation Disable bit in the SYSCON register Temporary variable for an intermediate storage of the number of shift or rotate cycles which remain to complete the shift or rotate operation Temporary variable for an intermediate result Constant values due to the data format of the specified operation
tmp 0, 1, 2,...
*Data Types* This part specifies the particular data type according to the instruction. Basically, the following data types are possible: BIT, BYTE, WORD, DOUBLEWORD Except for those instructions which extend byte data to word data, all instructions have only one particular data type. Note that the data types mentioned in this subsection do not consider accesses to indirect address pointers or to the system stack which are always performed with word data. Moreover, no data type is specified for System Control Instructions and for those of the branch instructions which do not access any explicitly addressed data.
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*Description* This part provides a brief verbal description of the action that is executed by the respective instruction.
*Condition Code* This notifies that the respective instruction contains a condition code, so it is executed, if the specified condition is true, and is skipped, if it is false. The table below summarizes the 16 possible condition codes that can be used within Call and Branch instructions. The table shows the mnemonic abbreviations, the test that is executed for a specific condition and the internal representation by a 4-bit number.
Condition Code Mnemonic cc cc_UC cc_Z cc_NZ cc_V cc_NV cc_N cc_NN cc_C cc_NC cc_EQ cc_NE cc_ULT cc_ULE cc_UGE cc_UGT cc_SLT cc_SLE cc_SGE cc_SGT cc_NET
Test 1=1 Z=1 Z=0 V=1 V=0 N=1 N=0 C=1 C=0 Z=1 Z=0 C=1 (ZC) = 1 C=0 (ZC) = 0 (NV) = 1 (Z(NV)) = 1 (NV) = 0 (Z(NV)) = 0 (ZE) = 0
Description Unconditional Zero Not zero Overflow No overflow Negative Not negative Carry No carry Equal Not equal Unsigned less than Unsigned less than or equal Unsigned greater than or equal Unsigned greater than Signed less than Signed less than or equal Signed greater than or equal Signed greater than Not equal AND not end of table
Condition Code Number c 0H 2H 3H 4H 5H 6H 7H 8H 9H 2H 3H 8H FH 9H EH CH BH DH AH 1H
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C166 Family Instruction Set Instruction Description
*Condition Flags* This part reflects the state of the N, C, V, Z and E flags in the PSW register which is the state after execution of the corresponding instruction, except if the PSW register itself was specified as the destination operand of that instruction (see Note). The resulting state of the flags is represented by symbols as follows: '*' The flag is set due to the following standard rules for the corresponding flag: N=1: N=0: C=1: C=0: V=1: V=0: Z=1: Z=0: E=1: E=0: 'S' '-' '0' 'NOR' 'AND' 'OR' 'XOR' 'B' 'B' MSB of the result is set MSB of the result is not set Carry occured during operation No Carry occured during operation Arithmetic Overflow occured during operation No Arithmetic Overflow occured during operation Result equals zero Result does not equal zero Source operand represents the lowest negative number (either 8000h for word data or 80h for byte data) Source operand does not represent the lowest negative number for the specified data type
The flag is set due to rules which deviate from the described standard. For more details see instruction pages (below) or the ALU status flags description. The flag is not affected by the operation. The flag is cleared by the operation. The flag contains the logical NORing of the two specified bit operands. The flag contains the logical ANDing of the two specified bit operands. The flag contains the logical ORing of the two specified bit operands. The flag contains the logical XORing of the two specified bit operands. The flag contains the original value of the specified bit operand. The flag contains the complemented value of the specified bit operand.
Note: If the PSW register was specified as the destination operand of an instruction, the condition flags can not be interpreted as just described, because the PSW register is modified depending on the data format of the instruction as follows: For word operations, the PSW register is overwritten with the word result. For byte operations, the non-addressed byte is cleared and the addressed byte is overwritten. For bit or bit-field operations on the PSW register, only the specified bits are modified. Supposed that the condition flags were not selected as destination bits, they stay unchanged. This means that they keep the state after execution of the previous instruction. In any case, if the PSW was the destination operand of an instruction, the PSW flags do NOT represent the condition flags of this instruction as usual.
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*Addressing Modes* This part specifies which combinations of different addressing modes are available for the required operands. Mostly, the selected addressing mode combination is specified by the opcode of the corresponding instruction. However, there are some arithmetic and logical instructions where the addressing mode combination is not specified by the (identical) opcodes but by particular bits within the operand field. The addressing mode entries are made up of three elements: Mnemonic Shows an example of what operands the respective instruction will accept. Format This part specifies the format of the instructions as it is represented in the assembler listing. The figure below shows the reference between the instruction format representation of the assembler and the corresponding internal organization of such an instruction format (N = nibble = 4 bits). The following symbols are used to describe the instruction formats: 00H through FFH : Instruction Opcodes 0, 1 :.... :..ii SS :..## :.### c n m q z # t:ttt0 QQ rr RR ZZ ## ## xx @@ MM MM ## ## : Constant Values : Each of the 4 characters immediately following a colon represents a single bit : 2-bit short GPR address (Rwi) : Code segment number (seg). 8-bit for C165/7, 2-bit (:..ss) for SAB8xC166 : 2-bit immediate constant (#irang2) : 3-bit immediate constant (#data3) : 4-bit condition code specification (cc) : 4-bit short GPR address (Rwn or Rbn) : 4-bit short GPR address (Rwm or Rbm) : 4-bit position of the source bit within the word specified by QQ : 4-bit position of the destination bit within the word specified by ZZ : 4-bit immediate constant (#data4) : 7-bit trap number (#trap7) : 8-bit word address of the source bit (bitoff) : 8-bit relative target address word offset (rel) : 8-bit word address reg : 8-bit word address of the destination bit (bitoff) : 8-bit immediate constant (#data8) : 8-bit immediate constant (represented by #data16, byte xx is not significant) : 8-bit immediate constant (#mask8) : 16-bit address (mem or caddr; low byte, high byte) : 16-bit immediate constant (#data16; low byte, high byte)
Number of Bytes Specifies the size of an instruction in bytes. All C166 Family instructions consist of either 2 or 4 bytes. Regarding the instruction size, all instructions can be classified as either single word or double word instructions.
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C166 Family Instruction Set Instruction Description
Representation in the Assembler Listing:
N2N1
N4N3
N6N5
N8N7 High Byte 2nd word
Low Byte 2nd word High Byte 1st word Low Byte 1st word
Internal Organization:
MSB N8 N7 N6 N5
Bits in ascending order LSB N4 N3 N2 N1
Figure 5-1: Instruction Format Representation
Notes on the ATOMIC and EXTended Instructions These instructions (ATOMIC, EXTR, EXTP, EXTS, EXTPR, EXTSR) disable standard and PEC interrupts and class A traps during a sequence of the following 1...4 instructions. The length of the sequence is determined by an operand (op1 or op2, depending on the instruction). The EXTended instruction additionally change the addressing mechanism during this sequence (see detailled instruction description). The ATOMIC and EXTended instructions become active immediately, so no additional NOPs are required. All instructions requiring multiple cycles or hold states to be executed are regarded as one instruction in this sense. Any instruction type can be used with the ATOMIC and EXTended instructions. CAUTION: When a Class B trap interupts an ATOMIC or EXTended sequence, this sequence is terminated, the interrupt lock is removed and the standard condition is restored, before the trap routine is executed! The remaining instructions of the terminated sequence that are executed after returning from the trap routine will run under standard conditions! CAUTION: Be careful, when using the ATOMIC and EXTended instructions with other system control or branch instructions. CAUTION: Be careful, when using nested ATOMIC and EXTended instructions. There is ONE counter to control the length of such a sequence, ie. issuing an ATOMIC or EXTended instruction within a sequence will reload the counter with value of the new instruction.
Note: The ATOMIC and EXTended instructions are not available in the SAB 8XC166(W) devices.
The following pages of this section contain a detailled description of each instruction of the C166 Family in alphabetical order.
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C166 Family Instruction Set Instruction Description
ADD
Syntax Operation Data Types Description ADD
Integer Addition
ADD
op1, op2
(op1) (op1) + (op2) WORD Performs a 2's complement binary addition of the source operand specified by op2 and the destination operand specified by op1. The sum is then stored in op1. E * Z * V * C * N *
Condition Flags
E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic overflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a carry is generated from the most significant bit of the specified data type. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic ADD ADD ADD ADD ADD ADD ADD Rwn, Rwm Rwn, [Rwi] Rwn, [Rwi+] Rwn, #data3 reg, #data16 reg, mem mem, reg Format 00 nm 08 n:10ii 08 n:11ii 08 n:0### 06 RR ## ## 02 RR MM MM 04 RR MM MM Bytes 2 2 2 2 4 4 4
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C166 Family Instruction Set Instruction Description
ADDB
Syntax Operation Data Types Description ADDB
Integer Addition
ADDB
op1, op2
(op1) (op1) + (op2) BYTE Performs a 2's complement binary addition of the source operand specified by op2 and the destination operand specified by op1. The sum is then stored in op1. E * Z * V * C * N *
Condition Flags
E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic overflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a carry is generated from the most significant bit of the specified data type. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic ADDB ADDB ADDB ADDB ADDB ADDB ADDB Rbn, Rbm Rbn, [Rwi] Rbn, [Rwi+] Rbn, #data3 reg, #data16 reg, mem mem, reg Format 01 nm 09 n:10ii 09 n:11ii 09 n:0### 07 RR ## xx 03 RR MM MM 05 RR MM MM Bytes 2 2 2 2 4 4 4
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C166 Family Instruction Set Instruction Description
ADDC
Syntax Operation Data Types Description ADDC
Integer Addition with Carry
ADDC
op1, op2
(op1) (op1) + (op2) + (C) WORD Performs a 2's complement binary addition of the source operand specified by op2, the destination operand specified by op1 and the previously generated carry bit. The sum is then stored in op1. This instruction can be used to perform multiple precision arithmetic. E * Z S V * C * N *
Condition Flags
E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero and previous Z flag was set. Cleared otherwise. V Set if an arithmetic overflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a carry is generated from the most significant bit of the specified data type. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic ADDC ADDC ADDC ADDC ADDC ADDC ADDC Rwn, Rwm Rwn, [Rwi] Rwn, [Rwi+] Rwn, #data3 reg, #data16 reg, mem mem, reg Format 10 nm 18 n:10ii 18 n:11ii 18 n:0### 16 RR ## ## 12 RR MM MM 14 RR MM MM Bytes 2 2 2 2 4 4 4
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C166 Family Instruction Set Instruction Description
ADDCB
Syntax Operation Data Types Description
Integer Addition with Carry
ADDCB
ADDCB
op1, op2
(op1) (op1) + (op2) + (C) BYTE Performs a 2's complement binary addition of the source operand specified by op2, the destination operand specified by op1 and the previously generated carry bit. The sum is then stored in op1. This instruction can be used to perform multiple precision arithmetic. E * Z S V * C * N *
Condition Flags
E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero and previous Z flag was set.. Cleared otherwise. V Set if an arithmetic overflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a carry is generated from the most significant bit of the specified data type. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic ADDCB ADDCB ADDCB ADDCB ADDCB ADDCB ADDCB Rbn, Rbm Rbn, [Rwi] Rbn, [Rwi+] Rbn, #data3 reg, #data16 reg, mem mem, reg Format 11 nm 19 n:10ii 19 n:11ii 19 n:0### 17 RR ## xx 13 RR MM MM 15 RR MM MM Bytes 2 2 2 2 4 4 4
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C166 Family Instruction Set Instruction Description
AND
Syntax Operation Data Types Description AND
Logical AND
AND
op1, op2
(op1) (op1) (op2) WORD Performs a bitwise logical AND of the source operand specified by op2 and the destination operand specified by op1. The result is then stored in op1. E * Z * V 0 C 0 N *
Condition Flags
E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Always cleared. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic AND AND AND AND AND AND AND Rwn, Rwm Rwn, [Rwi] Rwn, [Rwi+] Rwn, #data3 reg, #data16 reg, mem mem, reg Format 60 nm 68 n:10ii 68 n:11ii 68 n:0### 66 RR ## ## 62 RR MM MM 64 RR MM MM Bytes 2 2 2 2 4 4 4
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C166 Family Instruction Set Instruction Description
ANDB
Syntax Operation Data Types Description ANDB
Logical AND
ANDB
op1, op2
(op1) (op1) (op2) BYTE Performs a bitwise logical AND of the source operand specified by op2 and the destination operand specified by op1. The result is then stored in op1. E * Z * V 0 C 0 N *
Condition Flags
E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Always cleared. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic ANDB ANDB ANDB ANDB ANDB ANDB ANDB Rbn, Rbm Rbn, [Rwi] Rbn, [Rwi+] Rbn, #data3 reg, #data16 reg, mem mem, reg Format 61 nm 69 n:10ii 69 n:11ii 69 n:0### 67 RR ## xx 63 RR MM MM 65 RR MM MM Bytes 2 2 2 2 4 4 4
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C166 Family Instruction Set Instruction Description
ASHR
Syntax Operation ASHR
Arithmetic Shift Right
ASHR
op1, op2
(count) (op2) (V) 0 (C) 0 DO WHILE (count) 0 (V) (C) (V) (C) (op10) (op1n) (op1n+1) [n=0...14] (count) (count) - 1 END WHILE WORD Arithmetically shifts the destination word operand op1 right by as many times as specified in the source operand op2. To preserve the sign of the original operand op1, the most significant bits of the result are filled with zeros if the original MSB was a 0 or with ones if the original MSB was a 1. The Overflow flag is used as a Rounding flag. The LSB is shifted into the Carry. Only shift values between 0 and 15 are allowed. When using a GPR as the count control, only the least significant 4 bits are used. E 0 Z * V S C S N *
Data Types Description
Condition Flags
E Always cleared. Z Set if result equals zero. Cleared otherwise. V Set if in any cycle of the shift operation a 1 is shifted out of the carry flag. Cleared for a shift count of zero. C The carry flag is set according to the last LSB shifted out of op1. Cleared for a shift count of zero. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic ASHR ASHR Rwn, Rwm Rwn, #data4 Format AC nm BC #n Bytes 2 2
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C166 Family Instruction Set Instruction Description
ATOMIC
Syntax Operation
Begin ATOMIC Sequence
ATOMIC
ATOMIC
op1
(count) (op1) [1 op1 4] Disable interrupts and Class A traps DO WHILE ((count) 0 AND Class_B_trap_condition TRUE) Next Instruction (count) (count) - 1 END WHILE (count) = 0 Enable interrupts and traps Causes standard and PEC interrupts and class A hardware traps to be disabled for a specified number of instructions. The ATOMIC instruction becomes immediately active such that no additional NOPs are required. Depending on the value of op1, the period of validity of the ATOMIC sequence extends over the sequence of the next 1 to 4 instructions being executed after the ATOMIC instruction. All instructions requiring multiple cycles or hold states to be executed are regarded as one instruction in this sense. Any instruction type can be used with the ATOMIC instruction. The ATOMIC instruction must be used carefully (see introductory note). The ATOMIC instruction is not available in the SAB 8XC166(W) devices. E Z V C N -
Description
Note
Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic ATOMIC #irang2 Format D1 :00##-0 Bytes 2
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C166 Family Instruction Set Instruction Description
BAND
Syntax Operation Data Types Description BAND
Bit Logical AND
BAND
op1, op2
(op1) (op1) (op2) BIT Performs a single bit logical AND of the source bit specified by op2 and the destination bit specified by op1. The result is then stored in op1. E 0 Z NOR V OR C AND N XOR
Condition Flags
E Always cleared. Z Contains the logical NOR of the two specified bits. V Contains the logical OR of the two specified bits. C Contains the logical AND of the two specified bits. N Contains the logical XOR of the two specified bits. Addressing Modes Mnemonic BAND bitaddrZ.z, bitaddrQ.q Format 6A QQ ZZ qz Bytes 4
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C166 Family Instruction Set Instruction Description
BCLR
Syntax Operation Data Types Description BCLR (op1) 0 BIT op1
Bit Clear
BCLR
CLears the bit specified by op1. This instruction is primarily used for peripheral and system control. E 0 Z B V 0 C 0 N B
Condition Flags
E Always cleared. Z Contains the logical negation of the previous state of the specified bit. V Always cleared. C Always cleared. N Contains the previous state of the specified bit. Addressing Modes Mnemonic BCLR bitaddrQ.q Format qE QQ Bytes 2
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C166 Family Instruction Set Instruction Description
BCMP
Syntax Operation Data Types Description BCMP
Bit to Bit Compare
BCMP
op1, op2
(op1) (op2) BIT Performs a single bit comparison of the source bit specified by operand op1 to the source bit specified by operand op2. No result is written by this instruction. Only the condition codes are updated. The meaning of the condition flags for the BCMP instruction is different from the meaning of the flags for the other compare instructions. E 0 Z NOR V OR C AND N XOR
Note:
Condition Flags
E Always cleared. Z Contains the logical NOR of the two specified bits. V Contains the logical OR of the two specified bits. C Contains the logical AND of the two specified bits. N Contains the logical XOR of the two specified bits. Addressing Modes Mnemonic BCMP bitaddrZ.z, bitaddrQ.q Format 2A QQ ZZ qz Bytes 4
Semiconductor Group
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C166 Family Instruction Set Instruction Description
BFLDH
Syntax Operation BFLDH
Bit Field High Byte
BFLDH
op1, op2, op3
(tmp) (op1) (high byte (tmp)) ((high byte (tmp) op2) op3) (op1) (tmp)
Data Types Description
WORD Replaces those bits in the high byte of the destination word operand op1 which are selected by a '1' in the AND mask op2 with the bits at the corresponding positions in the OR mask specified by op3. op1 bits which shall remain unchanged must have a '0' in the respective bit of both the AND mask op2 and the OR mask op3. Otherwise a '1' in op3 will set the corresponding op1 bit (see Operation").
Note:
Condition Flags
E 0
Z *
V 0
C 0
N *
E Always cleared. Z Set if the word result equals zero. Cleared otherwise. V Always cleared. C Always cleared. N Set if the most significant bit of the word result is set. Cleared otherwise. Addressing Modes Mnemonic BFLDH Format bitoffQ, #mask8, #data8 1A QQ ## @@ Bytes 4
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C166 Family Instruction Set Instruction Description
BFLDL
Syntax Operation BFLDL
Bit Field Low Byte
BFLDL
op1, op2, op3
(tmp) (op1) (low byte (tmp)) ((low byte (tmp) op2) op3) (op1) (tmp)
Data Types Description
WORD Replaces those bits in the low byte of the destination word operand op1 which are selected by a '1' in the AND mask op2 with the bits at the corresponding positions in the OR mask specified by op3. op1 bits which shall remain unchanged must have a '0' in the respective bit of both the AND mask op2 and the OR mask op3. Otherwise a '1' in op3 will set the corresponding op1 bit (see Operation").
Note:
Condition Flags
E 0
Z *
V 0
C 0
N *
E Always cleared. Z Set if the word result equals zero. Cleared otherwise. V Always cleared. C Always cleared. N Set if the most significant bit of the word result is set. Cleared otherwise. Addressing Modes Mnemonic BFLDL Format bitoffQ, #mask8, #data8 0A QQ @@ ## Bytes 4
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C166 Family Instruction Set Instruction Description
BMOV
Syntax Operation Data Types Description BMOV
Bit to Bit Move
BMOV
op1, op2
(op1) (op2) BIT Moves a single bit from the source operand specified by op2 into the destination operand specified by op1. The source bit is examined and the flags are updated accordingly. E 0 Z B V 0 C 0 N B
Condition Flags
E Always cleared. Z Contains the logical negation of the previous state of the source bit. V Always cleared. C Always cleared. N Contains the previous state of the source bit. Addressing Modes Mnemonic BMOV bitaddrZ.z, bitaddrQ.q Format 4A QQ ZZ qz Bytes 4
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C166 Family Instruction Set Instruction Description
BMOVN
Syntax Operation Data Types Description
Bit to Bit Move and Negate
BMOVN
BMOVN
op1, op2
(op1) (op2) BIT Moves the complement of a single bit from the source operand specified by op2 into the destination operand specified by op1. The source bit is examined and the flags are updated accordingly. E 0 Z B V 0 C 0 N B
Condition Flags
E Always cleared. Z Contains the logical negation of the previous state of the source bit. V Always cleared. C Always cleared. N Contains the previous state of the source bit. Addressing Modes Mnemonic BMOVN bitaddrZ.z, bitaddrQ.q Format 3A QQ ZZ qz Bytes 4
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C166 Family Instruction Set Instruction Description
BOR
Syntax Operation Data Types Description BOR
Bit Logical OR
BOR
op1, op2
(op1) (op1) (op2) BIT Performs a single bit logical OR of the source bit specified by operand op2 with the destination bit specified by operand op1. The ORed result is then stored in op1. E 0 Z NOR V OR C AND N XOR
Condition Flags
E Always cleared. Z Contains the logical NOR of the two specified bits. V Contains the logical OR of the two specified bits. C Contains the logical AND of the two specified bits. N Contains the logical XOR of the two specified bits. Addressing Modes Mnemonic BOR bitaddrZ.z, bitaddrQ.q Format 5A QQ ZZ qz Bytes 4
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C166 Family Instruction Set Instruction Description
BSET
Syntax Operation Data Types Description BSET (op1) 1 BIT op1
Bit Set
BSET
Sets the bit specified by op1. This instruction is primarily used for peripheral and system control. E 0 Z B V 0 C 0 N B
Condition Flags
E Always cleared. Z Contains the logical negation of the previous state of the specified bit. V Always cleared. C Always cleared. N Contains the previous state of the specified bit. Addressing Modes Mnemonic BSET bitaddrQ.q Format qF QQ Bytes 2
Semiconductor Group
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C166 Family Instruction Set Instruction Description
BXOR
Syntax Operation Data Types Description BXOR
Bit Logical XOR
BXOR
op1, op2
(op1) (op1) (op2) BIT Performs a single bit logical EXCLUSIVE OR of the source bit specified by operand op2 with the destination bit specified by operand op1. The XORed result is then stored in op1. E 0 Z NOR V OR C AND N XOR
Condition Flags
E Always cleared. Z Contains the logical NOR of the two specified bits. V Contains the logical OR of the two specified bits. C Contains the logical AND of the two specified bits. N Contains the logical XOR of the two specified bits. Addressing Modes Mnemonic BXOR bitaddrZ.z, bitaddrQ.q Format 7A QQ ZZ qz Bytes 4
Semiconductor Group
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C166 Family Instruction Set Instruction Description
CALLA
Syntax Operation CALLA
Call Subroutine Absolute
CALLA
op1, op2
IF (op1) THEN (SP) (SP) - 2 ((SP)) (IP) (IP) op2 ELSE next instruction END IF
Description
If the condition specified by op1 is met, a branch to the absolute memory location specified by the second operand op2 is taken. The value of the instruction pointer, IP, is placed onto the system stack. Because the IP always points to the instruction following the branch instruction, the value stored on the system stack represents the return address of the calling routine. If the condition is not met, no action is taken and the next instruction is executed normally. See condition code table. E Z V C N -
Condition Codes Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic CALLA cc, caddr Format CA c0 MM MM Bytes 4
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C166 Family Instruction Set Instruction Description
CALLI
Syntax Operation CALLI
Call Subroutine Indirect
CALLI
op1, op2
IF (op1) THEN (SP) (SP) - 2 ((SP)) (IP) (IP) op2 ELSE next instruction END IF
Description
If the condition specified by op1 is met, a branch to the location specified indirectly by the second operand op2 is taken. The value of the instruction pointer, IP, is placed onto the system stack. Because the IP always points to the instruction following the branch instruction, the value stored on the system stack represents the return address of the calling routine. If the condition is not met, no action is taken and the next instruction is executed normally. See condition code table. E Z V C N -
Condition Codes Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic CALLI cc, [Rwn] Format AB cn Bytes 2
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C166 Family Instruction Set Instruction Description
CALLR
Syntax Operation CALLR
Call Subroutine Relative
CALLR
op1
(SP) (SP) - 2 ((SP)) (IP) (IP) (IP) + sign_extend (op1)
Description
A branch is taken to the location specified by the instruction pointer, IP, plus the relative displacement, op1. The displacement is a two's complement number which is sign extended and counts the relative distance in words. The value of the instruction pointer (IP) is placed onto the system stack. Because the IP always points to the instruction following the branch instruction, the value stored on the system stack represents the return address of the calling routine. The value of the IP used in the target address calculation is the address of the instruction following the CALLR instruction. See condition code table. E Z V C N -
Condition Codes Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic CALLR rel Format BB rr Bytes 2
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C166 Family Instruction Set Instruction Description
CALLS
Syntax Operation
Call Inter-Segment Subroutine
CALLS
CALLS
op1, op2
(SP) (SP) - 2 ((SP)) (CSP) (SP) (SP) - 2 ((SP)) (IP) (CSP) op1 (IP) op1
Description
A branch is taken to the absolute location specified by op2 within the segment specified by op1. The value of the instruction pointer (IP) is placed onto the system stack. Because the IP always points to the instruction following the branch instruction, the value stored on the system stack represents the return address to the calling routine. The previous value of the CSP is also placed on the system stack to insure correct return to the calling segment. See condition code table. E Z V C N -
Condition Codes Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic CALLS seg, caddr Format DA SS MM MM Bytes 4
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C166 Family Instruction Set Instruction Description
CMP
Syntax Operation Data Types Description CMP
Integer Compare
CMP
op1, op2
(op1) (op2) WORD The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2's complement binary subtraction of op2 from op1. The flags are set according to the rules of subtraction. The operands remain unchanged. E * Z * V * C S N *
Condition Flags
E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic CMP CMP CMP CMP CMP CMP Rwn, Rwm Rwn, [Rwi] Rwn, [Rwi+] Rwn, #data3 reg, #data16 reg, mem Format 40 nm 48 n:10ii 48 n:11ii 48 n:0### 46 RR ## ## 42 RR MM MM Bytes 2 2 2 2 4 4
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C166 Family Instruction Set Instruction Description
CMPB
Syntax Operation Data Types Description CMPB
Integer Compare
CMPB
op1, op2
(op1) (op2) BYTE The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2's complement binary subtraction of op2 from op1. The flags are set according to the rules of subtraction. The operands remain unchanged. E * Z * V * C S N *
Condition Flags
E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic CMPB CMPB CMPB CMPB CMPB CMPB Rbn, Rbm Rbn, [Rwi] Rbn, [Rwi+] Rbn, #data3 reg, #data16 reg, mem Format 41 nm 49 n:10ii 49 n:11ii 49 n:0### 47 RR ## xx 43 RR MM MM Bytes 2 2 2 2 4 4
Semiconductor Group
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C166 Family Instruction Set Instruction Description
CMPD1
Syntax Operation
Integer Compare and Decrement by 1
CMPD1
CMPD1
op1, op2
(op1) (op2) (op1) (op1) - 1
Data Types Description
WORD This instruction is used to enhance the performance and flexibility of loops. The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2's complement binary subtraction of op2 from op1. Operand op1 may specify ONLY GPR registers. Once the subtraction has completed, the operand op1 is decremented by one. Using the set flags, a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range. E * Z * V * C S N *
Condition Flags
E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic CMPD1 CMPD1 CMPD1 Rwn, #data4 Rwn, #data16 Rwn, mem Format A0 #n A6 Fn ## ## A2 Fn MM MM Bytes 2 4 4
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C166 Family Instruction Set Instruction Description
CMPD2
Syntax Operation
Integer Compare and Decrement by 2
CMPD2
CMPD2
op1, op2
(op1) (op2) (op1) (op1) - 2
Data Types Description
WORD This instruction is used to enhance the performance and flexibility of loops. The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2's complement binary subtraction of op2 from op1. Operand op1 may specify ONLY GPR registers. Once the subtraction has completed, the operand op1 is decremented by two. Using the set flags, a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range. E * Z * V * C S N *
Condition Flags
E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic CMPD2 CMPD2 CMPD2 Rwn, #data4 Rwn, #data16 Rwn, mem Format B0 #n B6 Fn ## ## B2 Fn MM MM Bytes 2 4 4
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C166 Family Instruction Set Instruction Description
CMPI1
Syntax Operation
Integer Compare and Increment by 1
CMPI1
CMPI1
op1, op2
(op1) (op2) (op1) (op1) + 1
Data Types Description
WORD This instruction is used to enhance the performance and flexibility of loops. The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2's complement binary subtraction of op2 from op1. Operand op1 may specify ONLY GPR registers. Once the subtraction has completed, the operand op1 is incremented by one. Using the set flags, a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range. E * Z * V * C S N *
Condition Flags
E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic CMPI1 CMPI1 CMPI1 Rwn, #data4 Rwn, #data16 Rwn, mem Format 80 #n 86 Fn ## ## 82 Fn MM MM Bytes 2 4 4
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C166 Family Instruction Set Instruction Description
CMPI2
Syntax Operation
Integer Compare and Increment by 2
CMPI2
CMPI2
op1, op2
(op1) (op2) (op1) (op1) + 2
Data Types Description
WORD This instruction is used to enhance the performance and flexibility of loops. The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2's complement binary subtraction of op2 from op1. Operand op1 may specify ONLY GPR registers. Once the subtraction has completed, the operand op1 is incremented by two. Using the set flags, a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range. E * Z * V * C S N *
Condition Flags
E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic CMPI2 CMPI2 CMPI2 Rwn, #data4 Rwn, #data16 Rwn, mem Format 90 #n 96 Fn ## ## 92 Fn MM MM Bytes 2 4 4
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C166 Family Instruction Set Instruction Description
CPL
Syntax Operation Data Types Description CPL
Integer One's Complement
CPL
op1
(op1) (op1) WORD Performs a 1's complement of the source operand specified by op1. The result is stored back into op1. E * Z * V 0 C 0 N *
Condition Flags
E Set if the value of op1 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Always cleared. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic CPL Rwn Format 91 n0 Bytes 2
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C166 Family Instruction Set Instruction Description
CPLB
Syntax Operation Data Types Description CPL
Integer One's Complement
CPLB
op1
(op1) (op1) BYTE Performs a 1's complement of the source operand specified by op1. The result is stored back into op1. E * Z * V 0 C 0 N *
Condition Flags
E Set if the value of op1 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Always cleared. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic CPLB Rbn Format B1 n0 Bytes 2
Semiconductor Group
61
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
DISWDT
Syntax Operation Description
Disable Watchdog Timer
DISWDT
DISWDT Disable the watchdog timer This instruction disables the watchdog timer. The watchdog timer is enabled by a reset. The DISWDT instruction allows the watchdog timer to be disabled for applications which do not require a watchdog function. Following a reset, this instruction can be executed at any time until either a Service Watchdog Timer instruction (SRVWDT) or an End of Initialization instruction (EINIT) are executed. Once one of these instructions has been executed, the DISWDT instruction will have no effect. To insure that this instruction is not accidentally executed, it is implemented as a protected instruction. E Z V C N -
Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic DISWDT Format A5 5A A5 A5 Bytes 4
Semiconductor Group
62
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
DIV
Syntax Operation DIV
16-by-16 Signed Division
DIV
op1
(MDL) (MDL) / (op1) (MDH) (MDL) mod (op1)
Data Types Description
WORD Performs a signed 16-bit by 16-bit division of the low order word stored in the MD register by the source word operand op1. The signed quotient is then stored in the low order word of the MD register (MDL) and the remainder is stored in the high order word of the MD register ( MDH). E 0 Z * V S C 0 N *
Condition Flags
E Always cleared. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic overflow occurred, ie. the result cannot be represented in a word data type, or if the divisor (op1) was zero. Cleared otherwise. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic DIV Rwn Format 4B nn Bytes 2
Semiconductor Group
63
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
DIVL
Syntax Operation DIVL
32-by-16 Signed Division
DIVL
op1
(MDL) (MD) / (op1) (MDH) (MD) mod (op1)
Data Types Description
WORD, DOUBLEWORD Performs an extended signed 32-bit by 16-bit division of the two words stored in the MD register by the source word operand op1. The signed quotient is then stored in the low order word of the MD register (MDL) and the remainder is stored in the high order word of the MD register ( MDH). E 0 Z * V S C 0 N *
Condition Flags
E Always cleared. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic overflow occurred, ie. the result cannot be represented in a word data type, or if the divisor (op1) was zero. Cleared otherwise. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic DIVL Rwn Format 6B nn Bytes 2
Semiconductor Group
64
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
DIVLU
Syntax Operation
32-by-16 Unsigned Division
DIVLU
DIVLU
op1
(MDL) (MD) / (op1) (MDH) (MD) mod (op1)
Data Types Description
WORD, DOUBLEWORD Performs an extended unsigned 32-bit by 16-bit division of the two words stored in the MD register by the source word operand op1. The unsigned quotient is then stored in the low order word of the MD register (MDL) and the remainder is stored in the high order word of the MD register ( MDH). E 0 Z * V S C 0 N *
Condition Flags
E Always cleared. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic overflow occurred, ie. the result cannot be represented in a word data type, or if the divisor (op1) was zero. Cleared otherwise. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic DIVLU Rwn Format 7B nn Bytes 2
Semiconductor Group
65
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
DIVU
Syntax Operation DIVU
16-by-16 Unsigned Division
DIVU
op1
(MDL) (MDL) / (op1) (MDH) (MDL) mod (op1)
Data Types Description
WORD Performs an unsigned 16-bit by 16-bit division of the low order word stored in the MD register by the source word operand op1. The signed quotient is then stored in the low order word of the MD register (MDL) and the remainder is stored in the high order word of the MD register ( MDH). E 0 Z * V S C 0 N *
Condition Flags
E Always cleared. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic overflow occurred, ie. the result cannot be represented in a word data type, or if the divisor (op1) was zero. Cleared otherwise. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic DIVU Rwn Format 5B nn Bytes 2
Semiconductor Group
66
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
EINIT
Syntax Operation Description EINIT
End of Initialization
EINIT
End of Initialization This instruction is used to signal the end of the initialization portion of a program. After a reset, the reset output pin RSTOUT is pulled low. It remains low until the EINIT instruction has been executed at which time it goes high. This enables the program to signal the external circuitry that it has successfully initialized the microcontroller. After the EINIT instruction has been executed, execution of the Disable Watchdog Timer instruction (DISWDT) has no effect. To insure that this instruction is not accidentally executed, it is implemented as a protected instruction. E Z V C N -
Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic EINIT Format B5 4A B5 B5 Bytes 4
Semiconductor Group
67
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
EXTR
Syntax Operation
Begin EXTended Register Sequence
EXTR
EXTR
op1
(count) (op1) [1 op1 4] Disable interrupts and Class A traps SFR_range = Extended DO WHILE ((count) 0 AND Class_B_trap_condition TRUE) Next Instruction (count) (count) - 1 END WHILE (count) = 0 SFR_range = Standard Enable interrupts and traps Causes all SFR or SFR bit accesses via the 'reg', 'bitoff' or 'bitaddr' addressing modes being made to the Extended SFR space for a specified number of instructions. During their execution, both standard and PEC interrupts and class A hardware traps are locked. The value of op1 defines the length of the effected instruction sequence. The EXTR instruction must be used carefully (see introductory note). The EXTR instruction is not available in the SAB 8XC166(W) devices. E Z V C N -
Description
Note
Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic EXTR #irang2 Format D1 :10##-0 Bytes 2
Semiconductor Group
68
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
EXTP
Syntax Operation
Begin EXTended Page Sequence
EXTP
EXTP
op1, op2
(count) (op2) [1 op2 4] Disable interrupts and Class A traps Data_Page = (op1) DO WHILE ((count) 0 AND Class_B_trap_condition TRUE) Next Instruction (count) (count) - 1 END WHILE (count) = 0 Data_Page = (DPPx) Enable interrupts and traps Overrides the standard DPP addressing scheme of the long and indirect addressing modes for a specified number of instructions. During their execution, both standard and PEC interrupts and class A hardware traps are locked. The EXTP instruction becomes immediately active such that no additional NOPs are required. For any long ('mem') or indirect ([...]) address in the EXTP instruction sequence, the 10-bit page number (address bits A23-A14) is not determined by the contents of a DPP register but by the value of op1 itself. The 14-bit page offset (address bits A13-A0) is derived from the long or indirect address as usual. The value of op2 defines the length of the effected instruction sequence. The EXTP instruction must be used carefully (see introductory note). The EXTP instruction is not available in the SAB 8XC166(W) devices. E Z V C N -
Description
Note
Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic EXTP EXTP Rwm, #irang2 #pag, #irang2 Format DC :01##-m D7 :01##-0 pp 0:00pp Bytes 2 4
Semiconductor Group
69
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
EXTPR
Syntax Operation
Begin EXTended Page and Register Sequence
EXTPR
EXTPR
op1, op2
(count) (op2) [1 op2 4] Disable interrupts and Class A traps Data_Page = (op1) AND SFR_range = Extended DO WHILE ((count) 0 AND Class_B_trap_condition TRUE) Next Instruction (count) (count) - 1 END WHILE (count) = 0 Data_Page = (DPPx) AND SFR_range = Standard Enable interrupts and traps Overrides the standard DPP addressing scheme of the long and indirect addressing modes and causes all SFR or SFR bit accesses via the 'reg', 'bitoff' or 'bitaddr' addressing modes being made to the Extended SFR space for a specified number of instructions. During their execution, both standard and PEC interrupts and class A hardware traps are locked. For any long ('mem') or indirect ([...]) address in the EXTP instruction sequence, the 10-bit page number (address bits A23-A14) is not determined by the contents of a DPP register but by the value of op1 itself. The 14-bit page offset (address bits A13-A0) is derived from the long or indirect address as usual. The value of op2 defines the length of the effected instruction sequence. The EXTPR instruction must be used carefully (see introductory note). The EXTPR instruction is not available in the SAB 8XC166(W) devices. E Z V C N -
Description
Note
Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic EXTPR EXTPR Rwm, #irang2 #pag, #irang2 Format DC :11##-m D7 :11##-0 pp 0:00pp Bytes 2 4
Semiconductor Group
70
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
EXTS
Syntax Operation
Begin EXTended Segment Sequence
EXTS
EXTS
op1, op2
(count) (op2) [1 op2 4] Disable interrupts and Class A traps Data_Segment = (op1) DO WHILE ((count) 0 AND Class_B_trap_condition TRUE) Next Instruction (count) (count) - 1 END WHILE (count) = 0 Data_Page = (DPPx) Enable interrupts and traps Overrides the standard DPP addressing scheme of the long and indirect addressing modes for a specified number of instructions. During their execution, both standard and PEC interrupts and class A hardware traps are locked. The EXTS instruction becomes immediately active such that no additional NOPs are required. For any long ('mem') or indirect ([...]) address in an EXTS instruction sequence, the value of op1 determines the 8-bit segment (address bits A23-A16) valid for the corresponding data access. The long or indirect address itself represents the 16-bit segment offset (address bits A15-A0). The value of op2 defines the length of the effected instruction sequence. The EXTS instruction must be used carefully (see introductory note). The EXTS instruction is not available in the SAB 8XC166(W) devices. E Z V C N -
Description
Note
Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic EXTS EXTS Rwm, #irang2 #seg, #irang2 Format DC :00##-m D7 :00##-0 ss 00 Bytes 2 4
Semiconductor Group
71
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C166 Family Instruction Set Instruction Description
EXTSRBegin EXTended Segment and Register SequenceEXTSR
Syntax Operation EXTSR op1, op2
(count) (op2) [1 op2 4] Disable interrupts and Class A traps Data_Segment = (op1) AND SFR_range = Extended DO WHILE ((count) 0 AND Class_B_trap_condition TRUE) Next Instruction (count) (count) - 1 END WHILE (count) = 0 Data_Page = (DPPx) AND SFR_range = Standard Enable interrupts and traps Overrides the standard DPP addressing scheme of the long and indirect addressing modes and causes all SFR or SFR bit accesses via the 'reg', 'bitoff' or 'bitaddr' addressing modes being made to the Extended SFR space for a specified number of instructions. During their execution, both standard and PEC interrupts and class A hardware traps are locked. The EXTSR instruction becomes immediately active such that no additional NOPs are required. For any long ('mem') or indirect ([...]) address in an EXTSR instruction sequence, the value of op1 determines the 8-bit segment (address bits A23-A16) valid for the corresponding data access. The long or indirect address itself represents the 16-bit segment offset (address bits A15-A0). The value of op2 defines the length of the effected instruction sequence. The EXTSR instruction must be used carefully (see introductory note). The EXTSR instruction is not available in the SAB 8XC166(W) devices. E Z V C N -
Description
Note
Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic EXTSR Rwm, #irang2 EXTSR #seg, #irang2 72 Format DC :10##-m D7 :10##-0 ss 00 Bytes 2 4 Version 1.2, 12.97
Semiconductor Group
30Mar98@15:00h
C166 Family Instruction Set Instruction Description
IDLE
Syntax Operation Description IDLE
Enter Idle Mode
IDLE
Enter Idle Mode This instruction causes the part to enter the idle mode. In this mode, the CPU is powered down while the peripherals remain running. It remains powered down until a peripheral interrupt or external interrupt occurs. To insure that this instruction is not accidentally executed, it is implemented as a protected instruction. E Z V C N -
Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic IDLE Format 87 78 87 87 Bytes 4
Semiconductor Group
73
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C166 Family Instruction Set Instruction Description
JB
Syntax Operation JB
Relative Jump if Bit Set
JB
op1, op2
IF (op1) = 1 THEN (IP) (IP) + sign_extend (op2) ELSE Next Instruction END IF
Data Types Description
BIT If the bit specified by op1 is set, program execution continues at the location of the instruction pointer, IP, plus the specified displacement, op2. The displacement is a two's complement number which is sign extended and counts the relative distance in words. The value of the IP used in the target address calculation is the address of the instruction following the JB instruction. If the specified bit is clear, the instruction following the JB instruction is executed. E Z V C N -
Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic JB bitaddrQ.q, rel Format 8A QQ rr q0 Bytes 4
Semiconductor Group
74
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
JBC
Syntax Operation
Relative Jump if Bit Set and Clear Bit
JBC
JBC
op1, op2
IF (op1) = 1 THEN (op1) = 0 (IP) (IP) + sign_extend (op2) ELSE Next Instruction END IF
Data Types Description
BIT If the bit specified by op1 is set, program execution continues at the location of the instruction pointer, IP, plus the specified displacement, op2. The bit specified by op1 is cleared, allowing implementation of semaphore operations. The displacement is a two's complement number which is sign extended and counts the relative distance in words. The value of the IP used in the target address calculation is the address of the instruction following the JBC instruction. If the specified bit was clear, the instruction following the JBC instruction is executed. E 0 Z B V 0 C 0 N B
Condition Flags
E Always cleared. Z Contains logical negation of the previous state of the specified bit. V Always cleared. C Always cleared. N Contains the previous state of the specified bit. Addressing Modes Mnemonic JBC bitaddrQ.q, rel Format AA QQ rr q0 Bytes 4
Semiconductor Group
75
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C166 Family Instruction Set Instruction Description
JMPA
Syntax Operation JMPA
Absolute Conditional Jump
JMPA
op1, op2
IF (op1) = 1 THEN (IP) op2 ELSE Next Instruction END IF
Description
If the condition specified by op1 is met, a branch to the absolute address specified by op2 is taken. If the condition is not met, no action is taken, and the instruction following the JMPA instruction is executed normally. See condition code table. E Z V C N -
Condition Codes Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic JMPA cc, caddr Format EA c0 MM MM Bytes 4
Semiconductor Group
76
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
JMPI
Syntax Operation JMPI
Indirect Conditional Jump
JMPI
op1, op2
IF (op1) = 1 THEN (IP) op2 ELSE Next Instruction END IF
Description
If the condition specified by op1 is met, a branch to the absolute address specified by op2 is taken. If the condition is not met, no action is taken, and the instruction following the JMPI instruction is executed normally. See condition code table. E Z V C N -
Condition Codes Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic JMPI cc, [Rwn] Format 9C cn Bytes 2
Semiconductor Group
77
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
JMPR
Syntax Operation JMPR
Relative Conditional Jump
JMPR
op1, op2
IF (op1) = 1 THEN (IP) (IP) + sign_extend (op2) ELSE Next Instruction END IF
Description
If the condition specified by op1 is met, program execution continues at the location of the instruction pointer, IP, plus the specified displacement, op2. The displacement is a two's complement number which is sign extended and counts the relative distance in words. The value of the IP used in the target address calculation is the address of the instruction following the JMPR instruction. If the specified condition is not met, program execution continues normally with the instruction following the JMPR instruction. See condition code table. E Z V C N -
Condition Codes Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic JMPR cc, rel Format cD rr Bytes 2
Semiconductor Group
78
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
JMPS
Syntax Operation
Absolute Inter-Segment Jump
JMPS
JMPS
op1, op2
(CSP) op1 (IP) op2
Description
Branches unconditionally to the absolute address specified by op2 within the segment specified by op1. E Z V C N -
Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic JMPS seg, caddr Format FA SS MM MM Bytes 4
Semiconductor Group
79
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
JNB
Syntax Operation JNB
Relative Jump if Bit Clear
JNB
op1, op2
IF (op1) = 0 THEN (IP) (IP) + sign_extend (op2) ELSE Next Instruction END IF
Data Types Description
BIT If the bit specified by op1 is clear, program execution continues at the location of the instruction pointer, IP, plus the specified displacement, op2. The displacement is a two's complement number which is sign extended and counts the relative distance in words. The value of the IP used in the target address calculation is the address of the instruction following the JNB instruction. If the specified bit is set, the instruction following the JNB instruction is executed. E Z V C N -
Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic JNB bitaddrQ.q, rel Format 9A QQ rr q0 Bytes 4
Semiconductor Group
80
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
JNBS
Syntax Operation
Relative Jump if Bit Clear and Set Bit
JNBS
JNBS
op1, op2
IF (op1) = 0 THEN (op1) = 1 (IP) (IP) + sign_extend (op2) ELSE Next Instruction END IF
Data Types Description
BIT If the bit specified by op1 is clear, program execution continues at the location of the instruction pointer, IP, plus the specified displacement, op2. The bit specified by op1 is set, allowing implementation of semaphore operations. The displacement is a two's complement number which is sign extended and counts the relative distance in words. The value of the IP used in the target address calculation is the address of the instruction following the JNBS instruction. If the specified bit was set, the instruction following the JNBS instruction is executed. E 0 Z B V 0 C 0 N B
Condition Flags
E Always cleared. Z Contains logical negation of the previous state of the specified bit. V Always cleared. C Always cleared. N Contains the previous state of the specified bit. Addressing Modes Mnemonic JNBS bitaddrQ.q, rel Format BA QQ rr q0 Bytes 4
Semiconductor Group
81
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
MOV
Syntax Operation Data Types Description MOV
Move Data
MOV
op1, op2
(op1) (op2) WORD Moves the contents of the source operand specified by op2 to the location specified by the destination operand op1. The contents of the moved data is examined, and the condition codes are updated accordingly. E * Z * V C N *
Condition Flags
E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if the value of the source operand op2 equals zero. Cleared otherwise. V Not affected. C Not affected. N Set if the most significant bit of the source operand op2 is set. Cleared otherwise. Addressing Modes Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV Rwn, Rwm Rwn, #data4 reg, #data16 Rwn, [Rwm] Rwn, [Rwm+] [Rwm], Rwn [-Rwm], Rwn [Rwn], [Rwm] [Rwn+], [Rwm] [Rwn], [Rwm+] Rwn, [Rwm+#data16] [Rwm+#data16], Rwn [Rwn], mem mem, [Rwn] reg, mem mem, reg Format F0 nm E0 #n E6 RR ## ## A8 nm 98 nm B8 nm 88 nm C8 nm D8 nm E8 nm D4 nm ## ## C4 nm ## ## 84 0n MM MM 94 0n MM MM F2 RR MM MM F6 RR MM MM Bytes 2 2 4 2 2 2 2 2 2 2 4 4 4 4 4 4
Semiconductor Group
82
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
MOVB
Syntax Operation Data Types Description MOVB
Move Data
MOVB
op1, op2
(op1) (op2) BYTE Moves the contents of the source operand specified by op2 to the location specified by the destination operand op1. The contents of the moved data is examined, and the condition codes are updated accordingly. E * Z * V C N *
Condition Flags
E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if the value of the source operand op2 equals zero. Cleared otherwise. V Not affected. C Not affected. N Set if the most significant bit of the source operand op2 is set. Cleared otherwise. Addressing Modes Mnemonic MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB Rbn, Rbm Rbn, #data4 reg, #data8 Rbn, [Rwm] Rbn, [Rwm+] [Rwm], Rbn [-Rwm], Rbn [Rwn], [Rwm] [Rwn+], [Rwm] [Rwn], [Rwm+] Rbn, [Rwm+#data16] [Rwm+#data16], Rbn [Rwn], mem mem, [Rwn] reg, mem mem, reg Format F1 nm E1 #n E7 RR ## xx A9 nm 99 nm B9 nm 89 nm C9 nm D9 nm E9 nm F4 nm ## ## E4 nm ## ## A4 0n MM MM B4 0n MM MM F3 RR MM MM F7 RR MM MM Bytes 2 2 4 2 2 2 2 2 2 2 4 4 4 4 4 4
Semiconductor Group
83
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
MOVBS
Syntax Operation MOVBS
Move Byte Sign Extend
MOVBS
op1, op2
(low byte op1) (op2) IF (op27) = 1 THEN (high byte op1) FFH ELSE (high byte op1) 00H END IF
Data Types Description
WORD, BYTE Moves and sign extends the contents of the source byte specified by op2 to the word location specified by the destination operand op1. The contents of the moved data is examined, and the condition codes are updated accordingly. E 0 Z * V C N *
Condition Flags
E Always cleared. Z Set if the value of the source operand op2 equals zero. Cleared otherwise. V Not affected. C Not affected. N Set if the most significant bit of the source operand op2 is set. Cleared otherwise. Addressing Modes Mnemonic MOVBS MOVBS MOVBS Rwn, Rbm reg, mem mem, reg Format D0 mn D2 RR MM MM D5 RR MM MM Bytes 2 4 4
Semiconductor Group
84
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
MOVBZ
Syntax Operation MOVBZ
Move Byte Zero Extend
MOVBZ
op1, op2
(low byte op1) (op2) (high byte op1) 00H
Data Types Description
WORD, BYTE Moves and zero extends the contents of the source byte specified by op2 to the word location specified by the destination operand op1. The contents of the moved data is examined, and the condition codes are updated accordingly. E 0 Z * V C N 0
Condition Flags
E Always cleared. Z Set if the value of the source operand op2 equals zero. Cleared otherwise. V Not affected. C Not affected. N Always cleared. Addressing Modes Mnemonic MOVBZ MOVBZ MOVBZ Rwn, Rbm reg, mem mem, reg Format C0 mn C2 RR MM MM C5 RR MM MM Bytes 2 4 4
Semiconductor Group
85
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
MUL
Syntax Operation Data Types Description MUL
Signed Multiplication
MUL
op1, op2
(MD) (op1) * (op2) WORD Performs a 16-bit by 16-bit signed multiplication using the two words specified by operands op1 and op2 respectively. The signed 32-bit result is placed in the MD register. E 0 Z * V S C 0 N *
Condition Flags
E Always cleared. Z Set if the result equals zero. Cleared otherwise. V This bit is set if the result cannot be represented in a word data type. Cleared otherwise. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic MUL Rwn, Rwm Format 0B nm Bytes 2
Semiconductor Group
86
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
MULU
Syntax Operation Data Types Description MULU
Unsigned Multiplication
MULU
op1, op2
(MD) (op1) * (op2) WORD Performs a 16-bit by 16-bit unsigned multiplication using the two words specified by operands op1 and op2 respectively. The unsigned 32-bit result is placed in the MD register. E 0 Z * V S C 0 N *
Condition Flags
E Always cleared. Z Set if the result equals zero. Cleared otherwise. V This bit is set if the result cannot be represented in a word data type. Cleared otherwise. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic MULU Rwn, Rwm Format 1B nm Bytes 2
Semiconductor Group
87
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
NEG
Syntax Operation Data Types Description NEG
Integer Two's Complement
NEG
op1
(op1) 0 - (op1) WORD Performs a binary 2's complement of the source operand specified by op1. The result is then stored in op1. E * Z * V * C S N *
Condition Flags
E Set if the value of op1 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic NEG Rwn Format 81 n0 Bytes 2
Semiconductor Group
88
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C166 Family Instruction Set Instruction Description
NEGB
Syntax Operation Data Types Description NEGB
Integer Two's Complement
NEGB
op1
(op1) 0 - (op1) BYTE Performs a binary 2's complement of the source operand specified by op1. The result is then stored in op1. E * Z * V * C S N *
Condition Flags
E Set if the value of op1 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic NEGB Rbn Format A1 n0 Bytes 2
Semiconductor Group
89
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C166 Family Instruction Set Instruction Description
NOP
Syntax Operation Description NOP No Operation
No Operation
NOP
This instruction causes a null operation to be performed. A null operation causes no change in the status of the flags. E Z V C N -
Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic NOP Format CC 00 Bytes 2
Semiconductor Group
90
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C166 Family Instruction Set Instruction Description
OR
Syntax Operation Data Types Description OR
Logical OR
OR
op1, op2
(op1) (op1) (op2) WORD Performs a bitwise logical OR of the source operand specified by op2 and the destination operand specified by op1. The result is then stored in op1.
Condition Flags
E *
Z *
V 0
C 0
N *
E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Always cleared. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic OR OR OR OR OR OR OR Rwn, Rwm Rwn, [Rwi] Rwn, [Rwi+] Rwn, #data3 reg, #data16 reg, mem mem, reg Format 70 nm 78 n:10ii 78 n:11ii 78 n:0### 76 RR ## ## 72 RR MM MM 74 RR MM MM Bytes 2 2 2 2 4 4 4
Semiconductor Group
91
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C166 Family Instruction Set Instruction Description
ORB
Syntax Operation Data Types Description ORB
Logical OR
ORB
op1, op2
(op1) (op1) (op2) BYTE Performs a bitwise logical OR of the source operand specified by op2 and the destination operand specified by op1. The result is then stored in op1.
Condition Flags
E *
Z *
V 0
C 0
N *
E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Always cleared. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic ORB ORB ORB ORB ORB ORB ORB Rbn, Rbm Rbn, [Rwi] Rbn, [Rwi+] Rbn, #data3 reg, #data16 reg, mem mem, reg Format 71 nm 79 n:10ii 79 n:11ii 79 n:0### 77 RR ## xx 73 RR MM MM 75 RR MM MM Bytes 2 2 2 2 4 4 4
Semiconductor Group
92
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
PCALL
Syntax Operation
Push Word and Call Subroutine Absolute
PCALL
PCALL
op1, op2
(tmp) (op1) (SP) (SP) - 2 ((SP)) (tmp) (SP) (SP) - 2 ((SP)) (IP) (IP) op2
Data Types Description
WORD Pushes the word specified by operand op1 and the value of the instruction pointer, IP, onto the system stack, and branches to the absolute memory location specified by the second operand op2. Because IP always points to the instruction following the branch instruction, the value stored on the system stack represents the return address of the calling routine. E * Z * V C N *
Condition Flags
E Set if the value of the pushed operand op1 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if the value of the pushed operand op1 equals zero. Cleared otherwise. V Not affected. C Not affected. N Set if the most significant bit of the pushed operand op1 is set. Cleared otherwise. Addressing Modes Mnemonic PCALL reg, caddr Format E2 RR MM MM Bytes 4
Semiconductor Group
93
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C166 Family Instruction Set Instruction Description
POP
Syntax Operation POP
Pop Word from System Stack
POP
op1
(tmp) ((SP)) (SP) (SP) + 2 (op1) (tmp)
Data Types Description
WORD Pops one word from the system stack specified by the Stack Pointer into the operand specified by op1. The Stack Pointer is then incremented by two. E * Z * V C N *
Condition Flags
E Set if the value of the popped word represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if the value of the popped word equals zero. Cleared otherwise. V Not affected. C Not affected. N Set if the most significant bit of the popped word is set. Cleared otherwise. Addressing Modes Mnemonic POP reg Format FC RR Bytes 2
Semiconductor Group
94
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
PRIOR
Syntax Operation PRIOR
Prioritize Register
PRIOR
op1, op2
(tmp) (op2) (count) 0 DO WHILE (tmp15) 1 AND (count) 15 AND (op2) 0 (tmpn) (tmpn-1) (count) (count) + 1 END WHILE (op1) (count)
Data Types Description
WORD This instruction stores a count value in the word operand specified by op1 indicating the number of single bit shifts required to normalize the operand op2 so that its MSB is equal to one. If the source operand op2 equals zero, a zero is written to operand op1 and the zero flag is set. Otherwise the zero flag is cleared. E 0 Z * V 0 C 0 N 0
Condition Flags
E Always cleared. Z Set if the source operand op2 equals zero. Cleared otherwise. V Always cleared. C Always cleared. N Always cleared. Addressing Modes Mnemonic PRIOR Rwn, Rwm Format 2B nm Bytes 2
Semiconductor Group
95
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C166 Family Instruction Set Instruction Description
PUSH
Syntax Operation
Push Word on System Stack
PUSH
PUSH
op1
(tmp) (op1) (SP) (SP) - 2 ((SP)) (tmp)
Data Types Description
WORD Moves the word specified by operand op1 to the location in the internal system stack specified by the Stack Pointer, after the Stack Pointer has been decremented by two. E * Z * V C N *
Condition Flags
E Set if the value of the pushed word represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if the value of the pushed word equals zero. Cleared otherwise. V Not affected. C Not affected. N Set if the most significant bit of the pushed word is set. Cleared otherwise. Addressing Modes Mnemonic PUSH reg Format EC RR Bytes 2
Semiconductor Group
96
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C166 Family Instruction Set Instruction Description
PWRDN
Syntax Operation Description
Enter Power Down Mode
PWRDN
PWRDN Enter Power Down Mode This instruction causes the part to enter the power down mode. In this mode, all peripherals and the CPU are powered down until the part is externally reset. To insure that this instruction is not accidentally executed, it is implemented as a protected instruction. To further control the action of this instruction, the PWRDN instruction is only enabled when the non-maskable interrupt pin (NMI) is in the low state. Otherwise, this instruction has no effect. E Z V C N -
Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic PWRDN Format 97 68 97 97 Bytes 4
Semiconductor Group
97
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C166 Family Instruction Set Instruction Description
RET
Syntax Operation RET
Return from Subroutine
RET
(IP) ((SP)) (SP) (SP) + 2
Description
Returns from a subroutine. The IP is popped from the system stack. Execution resumes at the instruction following the CALL instruction in the calling routine. E Z V C N -
Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic RET Format CB 00 Bytes 2
Semiconductor Group
98
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C166 Family Instruction Set Instruction Description
RETI
Syntax Operation
Return from Interrupt Routine
RETI
RETI (IP) ((SP)) (SP) (SP) + 2 IF (SYSCON.SGTDIS=0) THEN (CSP) ((SP)) (SP) (SP) + 2 END IF (PSW) ((SP)) (SP) (SP) + 2
Description
Returns from an interrupt routine. The PSW, IP, and CSP are popped off the system stack. Execution resumes at the instruction which had been interrupted. The previous system state is restored after the PSW has been popped. The CSP is only popped if segmentation is enabled. This is indicated by the SGTDIS bit in the SYSCON register. E S Z S V S C S N S
Condition Flags
E Restored from the PSW popped from stack. Z Restored from the PSW popped from stack. V Restored from the PSW popped from stack. C Restored from the PSW popped from stack. N Restored from the PSW popped from stack. Addressing Modes Mnemonic RETI Format FB 88 Bytes 2
Semiconductor Group
99
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C166 Family Instruction Set Instruction Description
RETP
Syntax Operation
Return from Subroutine and Pop Word
RETP
RETP
op1
(IP) ((SP)) (SP) (SP) + 2 (tmp) ((SP)) (SP) (SP) + 2 (op1) (tmp)
Data Types Description
WORD Returns from a subroutine. The IP is first popped from the system stack and then the next word is popped from the system stack into the operand specified by op1. Execution resumes at the instruction following the CALL instruction in the calling routine. E * Z * V C N *
Condition Flags
E Set if the value of the word popped into operand op1 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if the value of the word popped into operand op1 equals zero. Cleared otherwise. V Not affected. C Not affected. N Set if the most significant bit of the word popped into operand op1 is set. Cleared otherwise. Addressing Modes Mnemonic RETP reg Format EB RR Bytes 2
Semiconductor Group
100
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C166 Family Instruction Set Instruction Description
RETS
Syntax Operation
Return from Inter-Segment Subroutine
RETS
RETS (IP) ((SP)) (SP) (SP) + 2 (CSP) ((SP)) (SP) (SP) + 2
Description
Returns from an inter-segment subroutine. The IP and CSP are popped from the system stack. Execution resumes at the instruction following the CALLS instruction in the calling routine. E Z V C N -
Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic RETS Format DB 00 Bytes 2
Semiconductor Group
101
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C166 Family Instruction Set Instruction Description
ROL
Syntax Operation ROL
Rotate Left
ROL
op1, op2
(count) (op2) (C) 0 DO WHILE (count) 0 (C) (op115) (op1n) (op1n-1) [n=1...15] (op10) (C) (count) (count) - 1 END WHILE WORD Rotates the destination word operand op1 left by as many times as specified by the source operand op2. Bit 15 is rotated into Bit 0 and into the Carry. Only shift values between 0 and 15 are allowed. When using a GPR as the count control, only the least significant 4 bits are used. E 0 Z * V 0 C S N *
Data Types Description
Condition Flags
E Always cleared. Z Set if result equals zero. Cleared otherwise. V Always cleared. C The carry flag is set according to the last MSB shifted out of op1. Cleared for a rotate count of zero. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic ROL ROL Rwn, Rwm Rwn, #data4 Format 0C nm 1C #n Bytes 2 2
Semiconductor Group
102
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C166 Family Instruction Set Instruction Description
ROR
Syntax Operation ROR
Rotate Right
ROR
op1, op2
(count) (op2) (C) 0 (V) 0 DO WHILE (count) 0 (V) (V) (C) (C) (op10) (op1n) (op1n+1) [n=0...14] (op115) (C) (count) (count) - 1 END WHILE WORD Rotates the destination word operand op1 right by as many times as specified by the source operand op2. Bit 0 is rotated into Bit 15 and into the Carry. Only shift values between 0 and 15 are allowed. When using a GPR as the count control, only the least significant 4 bits are used. E 0 Z * V S C S N *
Data Types Description
Condition Flags
E Always cleared. Z Set if result equals zero. Cleared otherwise. V Set if in any cycle of the rotate operation a `1' is shifted out of the carry flag. Cleared for a rotate count of zero. C The carry flag is set according to the last LSB shifted out of op1. Cleared for a rotate count of zero. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic ROR ROR Rwn, Rwm Rwn, #data4 Format 2C nm 3C #n Bytes 2 2
Semiconductor Group
103
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C166 Family Instruction Set Instruction Description
SCXT
Syntax Operation SCXT
Switch Context
SCXT
op1, op2
(tmp1) (op1) (tmp2) (op2) (SP) (SP) - 2 ((SP)) (tmp1) (op1) (tmp2)
Data Types Description
WORD Used to switch contexts for any register. Switching context is a push and load operation. The contents of the register specified by the first operand, op1, are pushed onto the stack. That register is then loaded with the value specified by the second operand, op2. E Z V C N -
Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic SCXT SCXT reg, #data16 reg, mem Format C6 RR ## ## D6 RR MM MM Bytes 4 4
Semiconductor Group
104
Version 1.2, 12.97
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C166 Family Instruction Set Instruction Description
SHL
Syntax Operation SHL
Shift Left
SHL
op1, op2
(count) (op2) (C) 0 DO WHILE (count) 0 (C) (op115) (op1n) (op1n-1) [n=1...15] (op10) 0 (count) (count) - 1 END WHILE WORD Shifts the destination word operand op1 left by as many times as specified by the source operand op2. The least significant bits of the result are filled with zeros accordingly. The MSB is shifted into the Carry. Only shift values between 0 and 15 are allowed. When using a GPR as the count control, only the least significant 4 bits are used. E 0 Z * V 0 C S N *
Data Types Description
Condition Flags
E Always cleared. Z Set if result equals zero. Cleared otherwise. V Always cleared. C The carry flag is set according to the last MSB shifted out of op1. Cleared for a shift count of zero. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic SHL SHL Rwn, Rwm Rwn, #data4 Format 4C nm 5C #n Bytes 2 2
Semiconductor Group
105
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C166 Family Instruction Set Instruction Description
SHR
Syntax Operation SHR
Shift Right
SHR
op1, op2
(count) (op2) (C) 0 (V) 0 DO WHILE (count) 0 (V) (C) (V) (C) (op10) (op1n) (op1n+1) [n=0...14] (op115) 0 (count) (count) - 1 END WHILE WORD Shifts the destination word operand op1 right by as many times as specified by the source operand op2. The most significant bits of the result are filled with zeros accordingly. Since the bits shifted out effectively represent the remainder, the Overflow flag is used instead as a Rounding flag. This flag together with the Carry flag helps the user to determine whether the remainder bits lost were greater than, less than or equal to one half an LSB. Only shift values between 0 and 15 are allowed. When using a GPR as the count control, only the least significant 4 bits are used. E 0 Z * V S C S N *
Data Types Description
Condition Flags
E Always cleared. Z Set if result equals zero. Cleared otherwise. V Set if in any cycle of the shift operation a `1' is shifted out of the carry flag. Cleared for a shift count of zero. C The carry flag is set according to the last LSB shifted out of op1. Cleared for a shift count of zero. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic SHR SHR Rwn, Rwm Rwn, #data4 Format 6C nm 7C #n Bytes 2 2
Semiconductor Group
106
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C166 Family Instruction Set Instruction Description
SRST
Syntax Operation Description SRST
Software Reset
SRST
Software Reset This instruction is used to perform a software reset. A software reset has the same effect on the microcontroller as an externally applied hardware reset. To insure that this instruction is not accidentally executed, it is implemented as a protected instruction. E 0 Z 0 V 0 C 0 N 0
Condition Flags
E Always cleared. Z Always cleared. V Always cleared. C Always cleared. N Always cleared. Addressing Modes Mnemonic SRST Format B7 48 B7 B7 Bytes 4
Semiconductor Group
107
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C166 Family Instruction Set Instruction Description
SRVWDT
Syntax Operation Description
Service Watchdog Timer
SRVWDT
SRVWDT Service Watchdog Timer This instruction services the Watchdog Timer. It reloads the high order byte of the Watchdog Timer with a preset value and clears the low byte on every occurrence. Once this instruction has been executed, the watchdog timer cannot be disabled. To insure that this instruction is not accidentally executed, it is implemented as a protected instruction. E Z V C N -
Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic SRVWDT Format A7 58 A7 A7 Bytes 4
Semiconductor Group
108
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C166 Family Instruction Set Instruction Description
SUB
Syntax Operation Data Types Description SUB
Integer Subtraction
SUB
op1, op2
(op1) (op1) - (op2) WORD Performs a 2's complement binary subtraction of the source operand specified by op2 from the destination operand specified by op1. The result is then stored in op1. E * Z * V * C S N *
Condition Flags
E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic SUB SUB SUB SUB SUB SUB SUB Rwn, Rwm Rwn, [Rwi] Rwn, [Rwi+] Rwn, #data3 reg, #data16 reg, mem mem, reg Format 20 nm 28 n:10ii 28 n:11ii 28 n:0### 26 RR ## ## 22 RR MM MM 24 RR MM MM Bytes 2 2 2 2 4 4 4
Semiconductor Group
109
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C166 Family Instruction Set Instruction Description
SUBB
Syntax Operation Data Types Description SUBB
Integer Subtraction
SUBB
op1, op2
(op1) (op1) - (op2) BYTE Performs a 2's complement binary subtraction of the source operand specified by op2 from the destination operand specified by op1. The result is then stored in op1. E * Z * V * C S N *
Condition Flags
E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic SUBB SUBB SUBB SUBB SUBB SUBB SUBB Rbn, Rbm Rbn, [Rwi] Rbn, [Rwi+] Rbn, #data3 reg, #data16 reg, mem mem, reg Format 21 nm 29 n:10ii 29 n:11ii 29 n:0### 27 RR ## xx 23 RR MM MM 25 RR MM MM Bytes 2 2 2 2 4 4 4
Semiconductor Group
110
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C166 Family Instruction Set Instruction Description
SUBC
Syntax Operation Data Types Description
Integer Subtraction with Carry
SUBC
SUBC
op1, op2
(op1) (op1) - (op2) - (C) WORD Performs a 2's complement binary subtraction of the source operand specified by op2 and the previously generated carry bit from the destination operand specified by op1. The result is then stored in op1. This instruction can be used to perform multiple precision arithmetic. E * Z S V * C S N *
Condition Flags
E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero and the previous Z flag was set. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic SUBC SUBC SUBC SUBC SUBC SUBC SUBC Rwn, Rwm Rwn, [Rwi] Rwn, [Rwi+] Rwn, #data3 reg, #data16 reg, mem mem, reg Format 30 nm 38 n:10ii 38 n:11ii 38 n:0### 36 RR ## ## 32 RR MM MM 34 RR MM MM Bytes 2 2 2 2 4 4 4
Semiconductor Group
111
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C166 Family Instruction Set Instruction Description
SUBCB
Syntax Operation Data Types Description
Integer Subtraction with Carry
SUBCB
SUBCB
op1, op2
(op1) (op1) - (op2) - (C) BYTE Performs a 2's complement binary subtraction of the source operand specified by op2 and the previously generated carry bit from the destination operand specified by op1. The result is then stored in op1. This instruction can be used to perform multiple precision arithmetic. E * Z * V * C S N *
Condition Flags
E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic SUBCB SUBCB SUBCB SUBCB SUBCB SUBCB SUBCB Rbn, Rbm Rbn, [Rwi] Rbn, [Rwi+] Rbn, #data3 reg, #data16 reg, mem mem, reg Format 31 nm 39 n:10ii 39 n:11ii 39 n:0### 37 RR ## xx 33 RR MM MM 35 RR MM MM Bytes 2 2 2 2 4 4 4
Semiconductor Group
112
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C166 Family Instruction Set Instruction Description
TRAP
Syntax Operation TRAP
Software Trap
TRAP
op1
(SP) (SP) - 2 ((SP)) (PSW) IF (SYSCON.SGTDIS=0) THEN (SP) (SP) - 2 ((SP)) (CSP) (CSP) 0 END IF (SP) (SP) - 2 ((SP)) (IP) (IP) zero_extend (op1*4)
Description
Invokes a trap or interrupt routine based on the specified operand, op1. The invoked routine is determined by branching to the specified vector table entry point. This routine has no indication of whether it was called by software or hardware. System state is preserved identically to hardware interrupt entry except that the CPU priority level is not affected. The RETI, return from interrupt, instruction is used to resume execution after the trap or interrupt routine has completed. The CSP is pushed if segmentation is enabled. This is indicated by the SGTDIS bit in the SYSCON register. E Z V C N -
Condition Flags
E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic TRAP #trap7 Format 9B t:ttt0 Bytes 2
Semiconductor Group
113
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C166 Family Instruction Set Instruction Description
XOR
Syntax Operation Data Types Description XOR
Logical Exclusive OR
XOR
op1, op2
(op1) (op1) (op2) WORD Performs a bitwise logical EXCLUSIVE OR of the source operand specified by op2 and the destination operand specified by op1. The result is then stored in op1. E * Z * V 0 C 0 N *
Condition Flags
E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Always cleared. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic XOR XOR XOR XOR XOR XOR XOR Rwn, Rwm Rwn, [Rwi] Rwn, [Rwi+] Rwn, #data3 reg, #data16 reg, mem mem, reg Format 50 nm 58 n:10ii 58 n:11ii 58 n:0### 56 RR ## ## 52 RR MM MM 54 RR MM MM Bytes 2 2 2 2 4 4 4
Semiconductor Group
114
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C166 Family Instruction Set Instruction Description
XORB
Syntax Operation Data Types Description XORB
Logical Exclusive OR
XORB
op1, op2
(op1) (op1) (op2) BYTE Performs a bitwise logical EXCLUSIVE OR of the source operand specified by op2 and the destination operand specified by op1. The result is then stored in op1. E * Z * V 0 C 0 N *
Condition Flags
E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Always cleared. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic XORB XORB XORB XORB XORB XORB XORB Rbn, Rbm Rbn, [Rwi] Rbn, [Rwi+] Rbn, #data3 reg, #data16 reg, mem mem, reg Format 51 nm 59 n:10ii 59 n:11ii 59 n:0### 57 RR ## xx 53 RR MM MM 55 RR MM MM Bytes 2 2 2 2 4 4 4
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115
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C166 Family Instruction Set Addressing Modes
6
Addressing Modes
The Siemens 16-bit microcontrollers provide a lot of powerful addressing modes for access to word, byte and bit data (short, long, indirect), or to specify the target address of a branch instruction (absolute, relative, indirect). The different addressing modes use different formats and cover different scopes.
Short Addressing Modes All of these addressing modes use an implicit base offset address to specify an 18-bit or 24-bit physical address (SAB 80C166 group or C167/5 group, respectively). Short addressing modes allow to access the GPR, SFR or bit-addressable memory space: Physical Address = Base Address + * Short Address Note: is 1 for byte GPRs, is 2 for word GPRs.
Mnemonic Rw Rb reg
Physical Address (CP) (CP) 00'FE00H 00'F000H (CP) (CP) + 2*Rw + 1*Rb + 2*reg + 2*reg *) + 2*(reg0FH) + 1*(reg0FH)
Short Address Range Scope of Access Rw Rb reg reg reg reg bitoff bitoff bitoff bitoff bitpos = 0...15 = 0...15 = 00H...EFH = 00H...EFH = F0H...FFH = F0H...FFH = 00H...7FH = 80H...EFH = F0H...FFH = 00H...FFH = 0...15 GPRs GPRs SFRs ESFRs GPRs GPRs RAM SFR GPR (Word) (Byte) (Word, Low byte) (Word, Low byte)*) (Word) (Bytes) Bit word offset Bit word offset Bit word offset
bitoff
00'FD00H + 2*bitoff 00'FF00H + 2*(bitoffFFH) (CP) + 2*(bitoff0FH) Word offset as with bitoff. Immediate bit position.
bitaddr
Any single bit
*)
The Extended Special Function Register (ESFR) area is not available in the SAB 8XC166(W) devices.
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C166 Family Instruction Set Addressing Modes
Rw, Rb: Specifies direct access to any GPR in the currently active context (register bank). Both 'Rw' and 'Rb' require four bits in the instruction format. The base address of the current register bank is determined by the content of register CP. 'Rw' specifies a 4-bit word GPR address relative to the base address (CP), while 'Rb' specifies a 4 bit byte GPR address relative to the base address (CP). reg: Specifies direct access to any (E)SFR or GPR in the currently active context (register bank). 'reg' requires eight bits in the instruction format. Short 'reg' addresses from 00 H to EFH always specify (E)SFRs. In that case, the factor '' equates 2 and the base address is 00'FE00H for the standard SFR area or 00'F000H for the extended ESFR area. `reg' accesses to the ESFR area require a preceding EXT*R instruction to switch the base address (not available in the SAB 8XC166(W) devices). Depending on the opcode of an instruction, either the total word (for word operations) or the low byte (for byte operations) of an SFR can be addressed via 'reg'. Note that the high byte of an SFR cannot be accessed via the 'reg' addressing mode. Short 'reg' addresses from F0 H to FFH always specify GPRs. In that case, only the lower four bits of 'reg' are significant for physical address generation, and thus it can be regarded as being identical to the address generation described for the 'Rb' and 'Rw' addressing modes. Specifies direct access to any word in the bit-addressable memory space. 'bitoff' requires eight bits in the instruction format. Depending on the specified 'bitoff' range, different base addresses are used to generate physical addresses: Short 'bitoff' addresses from 00H to 7FH use 00'FD00H as a base address, and thus they specify the 128 highest internal RAM word locations (00'FD00Hh to 00'FDFEH). Short 'bitoff' addresses from 80H to EFH use 00'FF00H as a base address to specify the highest internal SFR word locations (00'FF00H to 00'FFDEH) or use 00'F100H as a base address to specify the highest internal ESFR word locations (00'F100H to 00'F1DEH). `bitoff' accesses to the ESFR area require a preceding EXT*R instruction to switch the base address (not available in the SAB 8XC166(W) devices). For short 'bitoff' addresses from F0H to FFH, only the lowest four bits and the contents of the CP register are used to generate the physical address of the selected word GPR.
bitoff:
bitaddr: Any bit address is specified by a word address within the bit-addressable memory space (see 'bitoff'), and by a bit position ('bitpos') within that word. Thus, 'bitaddr' requires twelve bits in the instruction format.
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Long Addressing Mode This addressing mode uses one of the four DPP registers to specify a physical 18-bit or 24-bit address. Any word or byte data within the entire address space can be accessed with this mode. The C167/5 devices also support an override mechanism for the DPP adressing scheme. Note: Word accesses on odd byte addresses are not executed, but rather trigger a hardware trap. After reset, the DPP registers are initialized in a way that all long addresses are directly mapped onto the identical physical addresses.
Any long 16-bit address consists of two portions, which are interpreted in different ways. Bits 13...0 specify a 14-bit data page offset, while bits 15...14 specify the Data Page Pointer (1 of 4), which is to be used to generate the physical 18-bit or 24-bit address (see figure below).
15 16-bit Long Address
14 13
0
DPP0 DPP1 DPP2 DPP3
14-bit page offset
18/24-bit Physical Address
Figure 6-1: Interpretation of a 16-bit Long Address The SAB 8XC166(W) devices support an address space of up to 256 KByte, while the C167/5 devices support an address space of up to 16 MByte, so only the lower two or ten bits (respectively) of the selected DPP register content are concatenated with the 14-bit data page offset to build the physical address.
The long addressing mode is referred to by the mnemonic `mem'. Mnemonic mem Physical Address (DPP0) (DPP1) (DPP2) (DPP3) pag seg || || || || mem3FFFH mem3FFFH mem3FFFH mem3FFFH Long Address Range Scope of Access 0000H...3FFFH 4000H...7FFFH 8000H...BFFFH C000H...FFFFH Any Word or Byte
mem mem
|| mem3FFFH || mem
0000H...FFFFH (14-bit) Any Word or Byte 0000H...FFFFH (16-bit) Any Word or Byte
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DPP Override Mechansim in the C167/5 Other than the older devices from the SAB 80C166 group the C167 and C165 devices provide an override mechanism that allows to bypass the DPP addressing scheme temporarily. The EXTP(R) and EXTS(R) instructions override this addressing mechanism. Instruction EXTP(R) replaces the content of the respective DPP register, while instruction EXTS(R) concatenates th complete 16-bit long address with the specified segment base address. The overriding page or segment may be specified directly as a constant (#pag, #seg) or via a word GPR (Rw).
EXTP(R):
15 16-bit Long Address #pag
14 13
0
14-bit page offset
24-bit Physical Address
EXTS(R):
15 16-bit Long Address #seg
0
16-bit segment offset
24-bit Physical Address
Figure 6-2: Overriding the DPP Mechanism
Indirect Addressing Modes These addressing modes can be regarded as a combination of short and long addressing modes. This means that long 16-bit addresses are specified indirectly by the contents of a word GPR, which is specified directly by a short 4-bit address ('Rw'=0 to 15). There are indirect addressing modes, which add a constant value to the GPR contents before the long 16-bit address is calculated. Other indirect addressing modes allow decrementing or incrementing the indirect address pointers (GPR content) by 2 or 1 (referring to words or bytes). In each case, one of the four DPP registers is used to specify physical 18-bit or 24-bit addresses. Any word or byte data within the entire memory space can be addressed indirectly. Note: The exceptions for instructions EXTP(R) and EXTS(R), ie. overriding the DPP mechanism, apply in the same way as described for the long addressing modes. Some instructions only use the lowest four word GPRs (R3...R0) as indirect address pointers, which are specified via short 2-bit addresses in that case.
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Note: Word accesses on odd byte addresses are not executed, but rather trigger a hardware trap. After reset, the DPP registers are initialized in a way that all indirect long addresses are directly mapped onto the identical physical addresses. Physical addresses are generated from indirect address pointers via the following algorithm: 1) Calculate the physical address of the word GPR, which is used as indirect address pointer, using the specified short address ('Rw') and the current register bank base address (CP). GPR Address = (CP) + 2 * Short Address 2) Pre-decremented indirect address pointers (`-Rw') are decremented by a data-typedependent value (=1 for byte operations, =2 for word operations), before the long 16-bit address is generated: (GPR Address) = (GPR Address) - ; [optional step!] 3) Calculate the long 16-bit address by adding a constant value (if selected) to the content of the indirect address pointer: Long Address = (GPR Pointer) + Constant 4) Calculate the physical 18-bit or 24-bit address using the resulting long address and the corresponding DPP register content (see long 'mem' addressing modes). Physical Address = (DPPi) + Page offset 5) Post-Incremented indirect address pointers (`Rw+') are incremented by a data-typedependent value (=1 for byte operations, =2 for word operations): (GPR Pointer) = (GPR Pointer) + ; [optional step!]
The following indirect addressing modes are provided: Mnemonic [Rw] [Rw+] [-Rw] Particularities Most instructions accept any GPR (R15...R0) as indirect address pointer. Some instructions, however, only accept the lower four GPRs (R3...R0). The specified indirect address pointer is automatically post-incremented by 2 or 1 (for word or byte data operations) after the access. The specified indirect address pointer is automatically pre-decremented by 2 or 1 (for word or byte data operations) before the access.
[Rw+#data16] The specified 16-bit constant is added to the indirect address pointer, before the long address is calculated.
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Constants The C166 Family instruction set also supports the use of wordwide or bytewide immediate constants. For an optimum utilization of the available code storage, these constants are represented in the instruction formats by either 3, 4, 8 or 16 bits. Thus, short constants are always zero-extended while long constants are truncated if necessary to match the data format required for the particular operation (see table below): Mnemonic #data3 #data4 #data8 #data16 #mask Word Operation 0000H + data3 0000H + data4 0000H + data8 data16 0000H + mask Byte Operation 00H + data3 00H + data4 data8 data16 FFH mask
Note: Immediate constants are always signified by a leading number sign '#'.
Instruction Range (#irang2) The effect of the ATOMIC and EXTended instructions can be defined for the following 1...4 instructions. This instruction range (1...4) is coded in the 2-bit constant #irang2 and is represented by the values 0...3.
Branch Target Addressing Modes Different addressing modes are provided to specify the target address and segment of jump or call instructions. Relative, absolute and indirect modes can be used to update the Instruction Pointer register (IP), while the Code Segment Pointer register (CSP) can only be updated with an absolute value. A special mode is provided to address the interrupt and trap jump vector table, which resides in the lowest portion of code segment 0. Mnemonic caddr rel [Rw] seg #trap7 Target Address (IP) = caddr (IP) = (IP) + 2*rel (IP) = (IP) + 2*(rel+1) (IP) = ((CP) + 2*Rw) (IP) = 0000H + 4*trap7 Target Segment (CSP) = seg (CSP) = 0000H Valid Address Range caddr rel rel Rw seg trap7 = 0000H...FFFEH = 00H...7FH = 80H...FFH = 0...15 = 0...255(3) = 00H...7FH
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caddr:
Specifies an absolute 16-bit code address within the current segment. Branches MAY NOT be taken to odd code addresses. Therefore, the least significant bit of 'caddr' must always contain a '0', otherwise a hardware trap would occur. This mnemonic represents an 8-bit signed word offset address relative to the current Instruction Pointer contents, which points to the instruction after the branch instruction. Depending on the offset address range, either forward ('rel'= 00H to 7FH) or backward ('rel'= 80H to FFH) branches are possible. The branch instruction itself is repeatedly executed, when 'rel' = '-1' (FFH) for a word-sized branch instruction, or 'rel' = '-2' (FEH) for a double-word-sized branch instruction. In this case, the 16-bit branch target instruction address is determined indirectly by the content of a word GPR. In contrast to indirect data addresses, indirectly specified code addresses are NOT calculated via additional pointer registers (eg. DPP registers). Branches MAY NOT be taken to odd code addresses. Therefore, the least significant bit of the address pointer GPR must always contain a '0', otherwise a hardware trap would occur. Specifies an absolute code segment number. The devices of the SAB 80C166 group support 4 different code segments, while the devices of the C167/5 group support 256 different code segments, so only the two or eight lower bits (respectively) of the 'seg' operand value are used for updating the CSP register. Specifies a particular interrupt or trap number for branching to the corresponding interrupt or trap service routine via a jump vector table. Trap numbers from 00H to 7FH can be specified, which allow to access any double word code location within the address range 00'0000H...00'01FCH in code segment 0 (ie. the interrupt jump vector table). For the association of trap numbers with the corresponding interrupt or trap sources please refer to chapter "Interrupt and Trap Functions".
rel:
[Rw]:
seg:
#trap7:
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C166 Family Instruction Set Instruction State Times
7
Instruction State Times
Basically, the time to execute an instruction depends on where the instruction is fetched from, and where possible operands are read from or written to. The fastest processing mode is to execute a program fetched from the internal ROM. In that case most of the instructions can be processed within just one machine cycle, which is also the general minimum execution time. All external memory accesses are performed by the on-chip External Bus Controller (EBC), which works in parallel with the CPU. Mostly, instructions from external memory cannot be processed as fast as instructions from the internal ROM, because some data transfers, which internally can be performed in parallel, have to be performed sequentially via the external interface. In contrast to internal ROM program execution, the time required to process an external program additionally depends on the length of the instructions and operands, on the selected bus mode, and on the duration of an external memory cycle, which is partly selectable by the user. Processing a program from the internal RAM space is not as fast as execution from the internal ROM area, but it offers a lot of flexibility (ie. for loading temporary programs into the internal RAM via the chip's serial interface, or end-of-line programming via the bootstrap loader). The following description allows evaluating the minimum and maximum program execution times. This will be sufficient for most requirements. For an exact determination of the instructions' state times it is recommended to use the facilities provided by simulators or emulators. This section defines the subsequently used time units, summarizes the minimum (standard) state times of the 16-bit microcontroller instructions, and describes the exceptions from that standard timing. Time Unit Definitions The following time units are used to describe the instructions' processing times: [fCPU]: CPU operating frequency (may vary from 1 MHz to 20 MHz).
[State]: One state time is specified by one CPU clock period. Henceforth, one State is used as the basic time unit, because it represents the shortest period of time which has to be considered for instruction timing evaluations. 1 [State] = 1/fCPU = 50 [s] ; for fCPU = variable [ns] ; for fCPU = 20 MHz
[ACT]: This ALE (Address Latch Enable) Cycle Time specifies the time required to perform one external memory access. One ALE Cycle Time consists of either two (for demultiplexed external bus modes) or three (for multiplexed external bus modes) state times plus a number of state times, which is determined by the number of waitstates programmed in the MCTC (Memory Cycle Time Control) and MTTC (Memory Tristate Time Control) bit fields of the SYSCON/BUSCONx registers. In case of demultiplexed external bus modes: = (2 + (15 - MCTC) + (1 - MTTC)) * States 1*ACT = 100 ns ... 900 ns ; for fCPU = 20 MHz In case of multiplexed external bus modes: = 3 + (15 - MCTC) + (1 - MTTC) * States 1*ACT = 150 ns ... 950 ns ; for fCPU = 20 MHz
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The total time (Ttot), which a particular part of a program takes to be processed, can be calculated by the sum of the single instruction processing times (TIn) of the considered instructions plus an offset value of 6 state times which considers the solitary filling of the pipeline, as follows: Ttot = TI1 + TI2 + ... + TIn + 6 * States
The time TIn, which a single instruction takes to be processed, consists of a minimum number (TImin) plus an additional number (TIadd) of instruction state times and/or ALE Cycle Times, as follows: TIn = TImin + TIadd
Minimum State Times The table below shows the minimum number of state times required to process an instruction fetched from the internal ROM (TImin (ROM)). The minimum number of state times for instructions fetched from the internal RAM (TImin (RAM)), or of ALE Cycle Times for instructions fetched from the external memory (TImin (ext)), can also be easily calculated by means of this table. Most of the 16-bit microcontroller instructions - except some of the branches, the multiplication, the division and a special move instruction - require a minimum of two state times. In case of internal ROM program execution there is no execution time dependency on the instruction length except for some special branch situations. The injected target instruction of a cache jump instruction can be considered for timing evaluations as if being executed from the internal ROM, regardless of which memory area the rest of the current program is really fetched from. For some of the branch instructions the table below represents both the standard number of state times (ie. the corresponding branch is taken) and an additional TImin value in parentheses, which refers to the case that either the branch condition is not met or a cache jump is taken.
Minimum Instruction State Times [Unit = ns] Instruction CALLI, CALLA CALLS, CALLR, PCALL JB, JBC, JNB, JNBS JMPS JMPA, JMPI, JMPR MUL, MULU DIV, DIVL, DIVU, DIVLU MOV[B] Rn, [Rm+#data16] RET, RETI, RETP, RETS TRAP All other instructions
TImin (ROM) [States]
4 4 4 4 4 10 20 4 4 4 2 (+2) (+2) (+2)
TImin (ROM) (@ 20 MHz CPU clock)
200 200 200 200 200 500 1000 200 200 200 100 (+100) (+100) (+100)
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Instructions executed from the internal RAM require the same minimum time as if being fetched from the internal ROM plus an instruction-length dependent number of state times, as follows: For 2-byte instructions: For 4-byte instructions:
TImin(RAM) = TImin(ROM) + 4 * States TImin(RAM) = TImin(ROM) + 6 * States
In contrast to the internal ROM program execution, the minimum time TImin(ext) to process an external instruction additionally depends on the instruction length. TImin(ext) is either 1 ALE Cycle Time for most of the 2-byte instructions, or 2 ALE Cycle Times for most of the 4-byte instructions. The following formula represents the minimum execution time of instructions fetched from an external memory via a 16-bit wide data bus: For 2-byte instructions: For 4-byte instructions:
TImin(ext) = 1*ACT + (TImin(ROM) - 2) * States TImin(ext) = 2*ACTs + (TImin(ROM) - 2) * States
Note: For instructions fetched from an external memory via an 8-bit wide data bus, the minimum number of required ALE Cycle Times is twice the number for a 16-bit wide bus.
Additional State Times Some operand accesses can extend the execution time of an instruction TIn. Since the additional time TIadd is mostly caused by internal instruction pipelining, it often will be possible to evade these timing effects in time-critical program modules by means of a suitable rearrangement of the corresponding instruction sequences. Simulators and emulators offer a lot of facilities, which support the user in optimizing his program whenever required.
* Internal ROM operand reads: TIadd = 2 * States Both byte and word operand reads always require 2 additional state times.
* Internal RAM operand reads via indirect addressing modes: TIadd = 0 or 1 * State Reading a GPR or any other directly addressed operand within the internal RAM space does NOT cause additional state times. However, reading an indirectly addressed internal RAM operand will extend the processing time by 1 state time, if the preceding instruction auto-increments or autodecrements a GPR as shown in the following example: ; auto-increment R0 ; if R2 points into the internal RAM space: ; TIadd = 1 * State In this case, the additional time can simply be avoided by putting another suitable instruction before the instruction In+1 indirectly reading the internal RAM. In In+1 : MOV R1 , [R0+] : MOV [R3], [R2]
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* Internal SFR operand reads: TIadd = 0, 1 * State or 2 * States Mostly, SFR read accesses do NOT require additional processing time. In some rare cases, however, either one or two additional state times will be caused by particular SFR operations, as follows: - Reading an SFR immediately after an instruction, which writes to the internal SFR space, as shown in the following example: In In+1 : MOV T0, #1000h : ADD R3, T1 ; write to Timer 0 ; read from Timer 1: TIadd = 1 * State
- Reading the PSW register immediately after an instruction, which implicitly updates the condition flags, as shown in the following example: In In+1 : ADD R0, #1000h : BAND C, Z ; implicit modification of PSW flags ; read from PSW: TIadd = 2 * States
- Implicitly incrementing or decrementing the SP register immediately after an instruction, which explicitly writes to the SP register, as shown in the following example: In In+1 ; explicit update of the stack pointer ; implicit decrement of the stack pointer: : TIadd = 2 * States In these cases, the extra state times can be avoided by putting other suitable instructions before the instruction In+1 reading the SFR. : MOV SP, #0FB00h : SCXT R1, #1000h
* External operand reads: TIadd = 1 * ACT Any external operand reading via a 16-bit wide data bus requires one additional ALE Cycle Time. Reading word operands via an 8-bit wide data bus takes twice as much time (2 ALE Cycle Times) as the reading of byte operands.
* External operand writes: TIadd = 0 * State ... 1 * ACT Writing an external operand via a 16-bit wide data bus takes one additional ALE Cycle Time. For timing calculations of external program parts, this extra time must always be considered. The value of TIadd which must be considered for timing evaluations of internal program parts, may fluctuate between 0 state times and 1 ALE Cycle Time. This is because external writes are normally performed in parallel to other CPU operations. Thus, TIadd could already have been considered in the standard processing time of another instruction. Writing a word operand via an 8-bit wide data bus requires twice as much time (2 ALE Cycle Times) as the writing of a byte operand.
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* Jumps into the internal ROM space: TIadd = 0 or 2 * States The minimum time of 4 state times for standard jumps into the internal ROM space will be extended by 2 additional state times, if the branch target instruction is a double word instruction at a nonaligned double word location (xxx2H, xxx6H, xxxAH, xxxEH), as shown in the following example: label .... In+1 : .... : .... : JMPA cc_UC, label ; any non-aligned double word instruction : (eg. at location 0FFEH) ; if a standard branch is taken: : TIadd = 2 * States (TIn = 6 * States)
A cache jump, which normally requires just 2 state times, will be extended by 2 additional state times, if both the cached jump target instruction and its successor instruction are non-aligned double word instructions, as shown in the following example: ; any non-aligned double word instruction : (eg. at location 12FAH) It+1 .... ; any non-aligned double word instruction : : (eg. at location 12FEH) ; provided that a cache jump is taken: In+1 :JMPR cc_UC, label : TIadd = 2 * States (TIn = 4 * States) If required, these extra state times can be avoided by allocating double word jump target instructions to aligned double word addresses (xxx0H, xxx4H, xxx8H, xxxCH). * Testing Branch Conditions: TIadd = 0 or 1 * States Mostly, NO extra time is required for conditional branch instructions to decide whether a branch condition is met or not. However, an additional state time is required, if the preceding instruction writes to the PSW register, as shown in the following example: In In+1 : BSET USR0 :JMPR cc_Z, label ; write to PSW ; test condition flag in PSW: TIadd = 1 * State label : ....
In this case, the extra state time can simply be intercepted by putting another suitable instruction before the conditional branch instruction.
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