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INTEGRATED CIRCUITS
DATA SHEET
TDA1388T Bitstream continuous calibration filter-DAC for CD-ROM audio applications
Objective specification File under Integrated Circuits, IC01 1995 Dec 08
Philips Semiconductors
Objective specification
Bitstream continuous calibration filter-DAC for CD-ROM audio
FEATURES Multiple format input interface * I2S-bus and LSB-justified input format compatible * 1fs input format data rate. Extensive channel manipulation features * Separate soft mute on left and right channel * Channel interchange function (left to right and right to left) * Monaural function (left to right or right to left) * True mono function (left plus right)/2. Digital sound processing * Separate digital volume control for left and right channels * Digital tone control, bass boost and treble * dB-linear volume and tone control (low microcontroller load) * Digital de-emphasis * Soft mute. Advanced audio output configuration * Stereo line output (under microcontroller volume control) * Stereo headphone output (under 5-tap potentiometer volume control) * Line output independent of headphone output volume * Power on/off click prevention circuitry * High linearity, dynamic range, low distortion. General * Integrated digital filter plus DAC plus headphone driver * No analog post filter required * Easy application * Functions controllable by static pins or by microcontroller interface * 5 V power supply * Low power consumption * Small package size (SO28 and SSOP28). GENERAL DESCRIPTION
TDA1388T
The TDA1388T CMOS digital-to-analog bitstream convertor incorporates an up-sampling digital filter and noise shaper, unique signal processing features and integrated line and headphone drivers. The digital processing features are of high sound quality due to the wide dynamic range of the bitstream conversion technique. The TDA1388T supports the I2S-bus data input mode with word lengths of up to 20 bits and the LSB justified serial data input format with word lengths of 16, 18 and 20 bits. Two cascaded half-band filters and a sample-and-hold function increase the oversampling rate from 1fs to 64fs. A 2nd-order noise shaper converts this oversampled data to a bitstream for the 5-bit continuous calibration digital-to-analog convertors (DACs). On board amplifiers convert the output current to a voltage signal capable of driving a line output. The signal is also used to feed the integrated headphone amplifiers. The volume of the headphone is controlled by an external potentiometer. The TDA1388T has special sound processing features for use in CD-ROM audio applications, which can be controlled by static pins or microcontroller interface. These functions are de-emphasis, volume, bass boost, treble, soft mute and the channel manipulation functions needed for ATAPI-compliant functionality in CD-ROM audio processing.
1995 Dec 08
2
Philips Semiconductors
Objective specification
Bitstream continuous calibration filter-DAC for CD-ROM audio applications
ORDERING INFORMATION TYPE NUMBER TDA1388T TDA1388TZ PACKAGE NAME SO28 SSOP28 DESCRIPTION plastic small outline package; 28 leads; body width 7.5 mm. plastic shrink small outline package; 28 leads; body width 5.3 mm.
TDA1388T
VERSION SOT136-1 SOT341-1
QUICK REFERENCE DATA SYMBOL Supply VDD IDD VFS(rms) (THD+N)/S supply voltage supply current full-scale output voltage (RMS value) total harmonic distortion plus noise as a function of signal for the line output note 1 note 2 VDD = 5 V 0 dB signal RL = 5 k -60 dB signal RL = 5 k total harmonic distortion plus noise as a function of signal for the headphone output 0 dB signal RL = 16 0 dB signal RL = 32 -60 dB signal RL = 16 or RL = 32 S/N BR fsys Tamb Notes 1. All VDD and VSS pins must be connected to the same supply or ground respectively. 2. Measured at input code 00000H and VDD = 5 V. signal-to-noise ratio input bit rate at data input system clock frequency operating ambient temperature A-weighted; at code 00000H fsys = 256fs fsys = 384fs 4.5 - 0.9 - - - - - - - - - - 90 - - 8.192 -20 5.0 22 1.0 -85 0.006 -35 1.8 -65 0.056 -70 0.032 -35 1.8 95 64fs 48fs - - 5.5 - 1.1 -80 0.013 -30 3.2 -60 0.1 - - -30 3.2 - - - 18.432 +70 V mA V dB % dBA % dB % dB % dBA % dBA bits bits MHz C PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
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Philips Semiconductors
Objective specification
Bitstream continuous calibration filter-DAC for CD-ROM audio applications
BLOCK DIAGRAM
TDA1388T
IF1 7
IF2 8
DATA 11
WS 10
BCK 9
ACP 19
SERIAL DATA INPUT 14 15 TIMING DE-EMPHASIS 18 APPL2
SYSCLK SYSSEL
CHANNEL INTERCHANGE
VOLUME CONTROL TC 20 BASS BOOST AND TREBLE FEATURE CONTROL UNIT 17
APPL1
SOFT MUTE VDDD 12 FILTER STAGE 1 + 2 4fs VSSD 13 SAMPLE-AND-HOLD 16 x OVERSAMPLING 2nd-ORDER NOISE SHAPER DATA ENCODER 16 (4-BIT) CALIBRATED CURRENT SOURCES 64fs 2nd-ORDER NOISE SHAPER DATA ENCODER 16 (4-BIT) CALIBRATED CURRENT SOURCES 22 VDDA 16
APPL0
TDA1388
23
VSSA
FILTCL
5 RCONV1
24 RCONV2
FILTCR
VDDA
16 (4-BIT) CALIBRATED CURRENT SINKS
REFERENCE SOURCE
16 (4-BIT) CALIBRATED CURRENT SINKS
Vref
6
+ HPINL 3 30 k 30 k 2 HPOUTL -
REFERENCE SOURCE
+ - 30 k 27 30 k
MGD015
HPOUTR
Fig.1 Block diagram.
1995 Dec 08
4
+ 28 1 21 26
+
VOL
4
-
LEFT OUTPUT SWITCHES
RIGHT OUTPUT SWITCHES
-
25
VOR
VDDO
VSSO1
VSSO2
HPINR
Philips Semiconductors
Objective specification
Bitstream continuous calibration filter-DAC for CD-ROM audio applications
PINNING SYMBOL VSSO HPOUTL HPINL VOL FILTCL PIN 1 2 3 4 5 DESCRIPTION operational amplifier ground left headphone output voltage left headphone input voltage left channel audio voltage output capacitor for left channel 1st-order filter function, should be connected between this pin and VOL (pin 4) internal reference voltage input format selection 1 input format selection 2 bit clock input word selection input data input digital supply voltage digital ground system clock 256fs or 384fs system clock selection application mode 0 input application mode 1 input application mode 2 input application control input test control not connected analog supply voltage analog ground capacitor for right channel 1st-order filter function, should be connected between this pin and VOR (pin 25) right channel audio voltage output right headphone input voltage right headphone output voltage operational amplifier supply voltage
DATA 11 VDDD 12 VSSD 13 SYSCLK 14
MGD014
TDA1388T
Vref IF1 IF2 BCK WS DATA VDDD VSSD SYSCLK SYSSEL APPL0 APPL1 APPL2 ACP TC n.c. VDDA VSSA FILTCR
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
handbook, halfpage
VSSO1 1 HPOUTL 2 HPINL 3 VOL 4 FILTCL 5 Vref 6 IF1 7
28 VDDO 27 HPOUTR 26 HPINR 25 VOR 24 FILTCR 23 VSSA
TDA1388
IF2 8 BCK 9 WS 10
22 VDDA 21 VSSO2 20 TC 19 ACP 18 APPL2 17 APPL1 16 APPL0 15 SYSSEL
VOR HPINR HPOUTR VDDO
25 26 27 28
Fig.2 Pin configuration.
1995 Dec 08
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Philips Semiconductors
Objective specification
Bitstream continuous calibration filter-DAC for CD-ROM audio applications
FUNCTIONAL DESCRIPTION The TDA1388T CMOS DAC incorporates an up-sampling digital filter, a sample-and-hold register, a noise shaper, continuously calibrated current sources, line amplifiers and headphone amplifiers. The 1fs input data is increased to an oversampled rate of 64fs. This high-rate oversampling, together with the 5-bit DAC, enables the filtering required for waveform smoothing and out-of-band noise reduction to be achieved by simple 1st-order analog post-filtering. System clock The TDA1388T accommodates slave mode only, this means that in all applications the system devices must provide the system clock. The system frequency is selectable. The options are 256fs and 384fs. The system clock must be locked in frequency to the I2S-bus input signals. Table 1 System clock selection SYSSEL 0 1 Multiple format input interface The TDA1388T supports the following data input formats; * I2S-bus with data word length of up to 20 bits. * LSB justified serial format with data word length of 16, 18 or 20 bits. DESCRIPTION 256fs 384fs Table 2 IF1 0 0 1 1 Data input formats IF2 0 1 0 1 I2S-bus
TDA1388T
FORMAT LSB-justified, 16 bits LSB-justified, 18 bits LSB-justified, 20 bits
The input formats are illustrated in Fig.3. Left and right data-channel words are time multiplexed. Input mode The TDA1388T has two input modes, a static-pin mode and a microcontroller mode. In the static-pin mode, the digital sound processing features such as mute left, mute right and de-emphasis are controlled by external pins. The other digital sound processing features have a default value. In the microcontroller mode, all the digital sound processing features can be controlled by the microcontroller. The controllable features are; * De-emphasis. * Volume left channel. * Volume right channel. * Flat/min/max switch. * Bass boost. * Treble. * Channel manipulation modes. The selection of one of the two modes is controlled by the ACP pin. When this pin is at logic 0 then the static pin mode will be selected. When the pin is at logic 1 then the microcontroller mode will be selected.
Table 3
Selectable values of the digital sound processing features FEATURES STATIC-PIN MODE 0 Hz or 44.1 kHz 0 dB (fixed) 0 dB (fixed) flat (fixed) flat set (fixed) flat set (fixed) external pin external pin L_CHANNEL = L (fixed) R_CHANNEL = R (fixed) MICROCONTROLLER MODE 0 Hz or 44.1 kHz 0 dB to - dB 0 dB to - dB flat/min/max flat, min or max set flat, min or max set selectable (see Table 4) selectable (see Table 4) see Table 10
De-emphasis Volume left channel Volume right channel Flat/min/max switch Bass boost Treble Mute left channel Mute right channel Channel manipulation modes
1995 Dec 08
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Philips Semiconductors
Objective specification
Bitstream continuous calibration filter-DAC for CD-ROM audio applications
STATIC-PIN MODE In the static-pin mode most of the features have a default value (see Table 3). The features that are controlled by the external pins are, mute left channel, mute right channel and de-emphasis. Table 4 External pin feature control in the static-pin mode PIN APPL0 APPL1 APPL2 MICROCONTROLLER MODE The exchange of data and control information between the microcontroller and the TDA1388T is accomplished through a serial hardware interface comprising the following pins; APPL0: microcontroller interface data line. APPL1: microcontroller interface mode line. APPL2: microcontroller interface clock line. Information transfer through the microcontroller bus is organized in accordance with the so-called `L3' format, in which two different modes of operation can be distinguished; address mode and data transfer mode (see Figs 4 and 5). The address mode is required to select a device communicating via the L3-bus and to define the destination registers for the data transfer mode. Data transfer for the TDA1388T can only be in one direction, input to the TDA1388T to program its sound processing and other functional features. FEATURE mute left channel mute right channel de-emphasis Table 5 BIT 1 0 0 1 1 Selection of data transfer BIT 0 0 1 0 1
TDA1388T
TRANSFER data (volume left, volume right, bass boost and treble) not used status (de-emphasis, mode and channel-manipulation) not used
Data bits 7 to 2 represent a 6-bit device address, with bit 7 being the MSB and bit 2 the LSB. The address of the TDA1388T is 000101 (bit 7 to bit 2). In the event that the TDA1388T receives a different address, it will deselect its microcontroller interface logic.
Data transfer mode
The selection preformed in the address mode remains active during subsequent data transfers, until the TDA1388T receives a new address command. The fundamental timing of data transfers is essentially the same as in the address mode, shown in Fig.4. The maximum input clock and data rate is 64fs. All transfers are bitwise, i.e. they are based on groups of 8 bits. Data will be stored in the TDA1388T after the eighth bit of a byte has been received. A multibyte transfer is illustrated in Fig.6.
Programming the sound processing and other features
The sound processing and other feature values are stored in independent registers. The first selection of the registers is achieved by the choice of data type that is transferred. This is performed in the address mode, BIT 1 and BIT 0 (see Table 5). The second selection is performed by the 2 MSBs of the data byte (BIT 7 and BIT 6). The other bits in the data byte (BIT 5 to BIT 0) is the value that is placed in the selected registers. When the data transfer of type "data" is selected, the features VOLUME_R, VOLUME_L, BASS BOOST and TREBLE can be controlled. When the data transfer of type "status" is selected, the features MODE, DE-EMPHASIS, CHANNEL_MANIP_R and CHANNEL_MANIP_L can be controlled.
Address mode
The address mode is used to select a device for subsequent data transfer and to define the destination registers. The address mode is characterized by APPL1 being LOW and a burst of 8 pulses on APPL2, accompanied by 8 data bits. The fundamental timing is shown in Fig.4. Data bits 0 to 1 indicate the type of the subsequent data transfer as shown in Table 5. Table 6 BIT 7 0 Data transfer of type "status" BIT6 M1 BIT 5 M0 BIT 4 DE BIT 3 OR1 BIT 2 OR0 BIT 1 OL1
BIT 0 OL0
REGISTER SELECTED MODE (1 : 0), DEEMPHASIS, CHANNEL_MANIP_R (1 : 0), CHANNEL_MANIP_L (1 : 0)
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Philips Semiconductors
Objective specification
Bitstream continuous calibration filter-DAC for CD-ROM audio applications
Table 7 BIT 7 0 0 1 1 Note 1. X = don't care MODE: a 2-bit value to program the mode of the sound processing filters of Bass Boost and Treble. There are three modes: flat, min and max. Table 8 The flat/min/max switch MODE 0 0 1 0 1 FUNCTION flat min min max Data transfer of type "data" BIT 6 0 1 0 1 BIT 5 VR5 VL5 X(1) X(1) BIT 4 VR4 VL4 BB4 TR4 BIT 3 VR3 VL3 BB3 TR3 BIT 2 VR2 VL2 BB2 TR2 BIT 1 VR1 VL1 BB1 TR1 BIT 0 VR0 VL0 BB0 TR0
TDA1388T
REGISTER SELECTED VOLUME_R (5 : 0) VOLUME_L (5 : 0) BASS BOOST (4 : 0) TREBLE (4 : 0)
DE-EMPHASIS: a 1-bit value to enable the digital de-emphasis filter. Table 9 De-emphasis FUNCTION no de-emphasis de-emphasis, 44.1 kHz
DEEM 0 1
MODE 1 0 0 1 1
CHANNEL_MANIP_R and CHANNEL_MANIP_L: both are a 2 bit value to program the right or left channel manipulation. Table 10 Channel manipulation modes CHANNEL_MANIP_L<1 : 0> 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11 CHANNEL_MANIP_R<1 : 0> 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 L_CHANNEL MUTE MUTE MUTE MUTE R R R R L L L L (L + R)/2 (L + R)/2 (L + R)/2 (L + R)/2 R_CHANNEL MUTE R L (L + R)/2 MUTE R L (L + R)/2 MUTE R L (L + R)/2 MUTE R L (L + R)/2
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Philips Semiconductors
Objective specification
Bitstream continuous calibration filter-DAC for CD-ROM audio applications
TDA1388T
VOLUME_R: a 6-bit value to program the right channel volume attenuation (VR5 to VR0). The range is 0 dB to - dB in steps of 1 dB. Table 11 Volume right settings VR5 0 0 0 0 : 1 1 1 1 1 VR4 0 0 0 0 : 1 1 1 1 1 VR3 0 0 0 0 : 1 1 1 1 1 VR2 0 0 0 0 : 0 1 1 1 1 VR1 0 0 1 1 : 1 0 0 1 1 VR0 0 1 0 1 : 1 0 1 0 1 VOLUME (dB) 0 0 -1 -2 : -58 -59 -60 - -
VOLUME_L: a 6-bit value to program the left channel volume attenuation (VL5 to VL0). The range is 0 dB to - dB in steps of 1 dB. Table 12 Volume left settings VR5 0 0 0 0 : 1 1 1 1 1 VR4 0 0 0 0 : 1 1 1 1 1 VR3 0 0 0 0 : 1 1 1 1 1 VR2 0 0 0 0 : 0 1 1 1 1 VR1 0 0 1 1 : 1 0 0 1 1 VR0 0 1 0 1 : 1 0 1 0 1 VOLUME (dB) 0 0 -1 -2 : -58 -59 -60 - -
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Philips Semiconductors
Objective specification
Bitstream continuous calibration filter-DAC for CD-ROM audio applications
TDA1388T
BASS BOOST: a 5-bit value to program the bass boost setting. The used set depends on the MODE bits. Table 13 Bass boost settings BASS BOOST BB4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 : 1 BB3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 : 1 BB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 : 1 BB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 : 1 BB0 FLAT SET (dB) 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : 0 MIN SET (dB) 0 0 0 0 2 2 4 4 6 6 8 8 10 10 12 12 14 14 16 16 18 18 18 18 18 18 18 18 : 18 MAX SET (dB) 0 0 0 0 2 2 4 4 6 6 8 8 10 10 12 12 14 14 16 16 18 18 20 20 22 22 24 24 : 24
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Philips Semiconductors
Objective specification
Bitstream continuous calibration filter-DAC for CD-ROM audio applications
TREBLE: a 5-bit value to program the treble setting. The used set depends on the MODE bits. Table 14 Treble settings TREBLE TR4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : 1 TR3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 : 1 TR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 : 1 TR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 : 1 TR0 FLAT SET (dB) 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : 0 * Normal stereo output. * Left/right reverse output. * Mono left/right output: (L + R)/2. * Output muting with soft mute. De-emphasis MIN SET (dB) 0 0 0 0 2 2 2 2 4 4 4 4 6 6 6 6 : 6
TDA1388T
MAX SET (dB) 0 0 0 0 2 2 2 2 4 4 4 4 6 6 6 6 : 6
Flat/min/max setting selection In the TDA1388T has three setting for the digital sound features bass boost and treble. The possible settings are called `flat', `min' and `max'. The flat setting has no influence on the audio signal, the minimum setting has a small influence on the audio signal and the maximum setting has a large influence on the audio signal. In the static-pin mode, the flat setting is used for the bass boost and treble filters. In the microcontroller mode, all three settings can by controlled by a register. Channel manipulation modes In the TDA1388T there is a channel manipulation function implemented. This function has a fixed value in the static-pin mode, the left signal on the left channel and the right signal on the right channel. In the microcontroller mode several option are possible. The different modes are as follows;
De-emphasis is controlled by an external pin in the static-pin mode and by a register in the microcontroller mode.The digital de-emphasis filter is dimensioned to produce the de-emphasis frequency characteristics for the sample rate 44.1 kHz. With its 18-bit dynamic range, the digital de-emphasis filter of the TDA1388T is a convenient and component saving alternative to analog de-emphasis. De-emphasis is synchronized to the sample clock, so that operation always takes place on complete samples.
1995 Dec 08
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Philips Semiconductors
Objective specification
Bitstream continuous calibration filter-DAC for CD-ROM audio applications
Volume control The volume of the left and right channels are controlled by a fixed value (0 dB) in the static-pin mode and by separate registers in the microcontroller mode. In the microcontroller mode the values of both channels can vary, independent of each other, from 0 dB to - dB. Since there is no headroom included into the sound control section, the volume control precedes the sound control. Full volume and neutral setting (flat) of the sound control results in full-scale output. Any tone boost will directly cause clipping, which can be avoided by reduction of the volume setting. Bass boost A strong bass boost effect, which is useful in compensating for poor response of portable headphone sets, is implemented digitally in the TDA1388T and can be controlled in the microcontroller mode. In the static-pin mode, the flat setting is fixed. In the microcontroller mode, valid settings range from flat (no influence on audio) to +18 dB with step sizes of 2 dB in minimum and to +24 dB with step sizes of 2 dB in maximum. The programmable bass boost filter is a 2nd-order shelving type with a fixed corner frequency of 130 Hz for the minimum setting and a fixed corner frequency of 230 Hz for the maximum setting and has a Butterworth characteristic. Because of the exceptional amount of programmable gain, bass boost should be used with adequate prior attenuation, using the volume control. Treble A treble effect is implemented digitally in the TDA1388T and can be controlled in the microcontroller mode. In the static-pin mode, the flat setting is fixed. In the microcontroller mode, valid settings range from flat (no influence on audio) to +6 dB with step sizes of 2 dB in minimum and to +6 dB with step sizes of 2 dB in maximum. The programmable treble filter is a 1st-order shelving type with a fixed corner frequency of 2.8 kHz for the minimum setting and a fixed corner frequency of 5.0 kHz for the maximum setting. Because of the exceptional amount of programmable gain, treble should be used with adequate prior attenuation, using the volume control. Soft mute Soft mute is controlled by external pins, for each channel one, in the static-pin mode and by the channel manipulation modes of left or right in the microcontroller mode. 1995 Dec 08 12
TDA1388T
When the mute is active for a channel, the value of the sample is decreased smoothly to zero following a raised cosine curve. 32 coefficients are used to step down the value of the data, each one being used 32 times before stepping on to the next. This amounts to a mute transition of 23 ms at fs = 44.1 kHz. When the mute is released, the samples are returned to the full level again following a raised cosine curve with the same coefficients being used in the reverse order. The mute, on the left or right channel, is synchronized to the sample clock, so that operation always takes place on complete samples. Oversampling and noise shaper The digital filter is four times oversampling filter. It consists of two sections which each increase the sample rate by 2. The 2nd-order noise shaper operates at 64fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique used in combination with a sign-magnitude coding enables high signal-to-noise ratios to be achieved. The noise shaper outputs a 5-bit PDM bitstream signal to the DAC. Continuous calibration DAC The dual 5-bit DAC uses the continuous calibration technique. This method, based on charge storage, involves exact duplication of a single reference current source. In the TDA1388T, 32 such current sources plus 1 spare source are continuously calibrated. The spare source is included to allow continuous convertor operation. The DAC receives a 5-bit data bitstream from the noise shaper. This data is converted so that no current is switched to the output during digital silence (input 00000H). In this way very high signal-to-noise performance is achieved. Stereo line driver High precision, low-noise amplifiers together with the internal conversion resistor RCONV1 and RCONV2 convert the converter output current to a voltage capable of driving a headphone. The voltage is available at VOL and VOR (pins 4 and 25). Stereo headphone driver High precision, low-noise amplifiers are capable of driving a headphone load. The voltage is available at HPOUTL and HPOUTR (pins 2 and 27).
handbook, full pagewidth
1995 Dec 08
RIGHT >=8 1 2 3 >=8 LSB MSB INPUT FORMAT S-BUS I2 B2 LSB MSB LEFT 16 15 2 1 16 15 RIGHT 2 1 MSB LSB-JUSTIFIED FORMAT 16 BITS B2 B15 LSB MSB B2 B15 LSB
WS
LEFT
Philips Semiconductors
1
2
3
BCK
DATA
MSB
B2
WS
BCK
DATA
Bitstream continuous calibration filter-DAC for CD-ROM audio applications
13
LEFT 18 17 16 15 2 1 18 RIGHT 17 16 15 2 1 MSB LSB-JUSTIFIED FORMAT 18 BITS B2 B3 B4 B17 LSB MSB B2 B3 B4 B17 LSB LEFT 18 17 16 15 2 1 20 19 18 RIGHT 17 16 15 2 1 B3 B4 B5 B6 B19 LSB MSB B2 B3 B4 B5 B6 B19 LSB
MGD019
WS
BCK
DATA
WS
20
19
BCK
DATA
MSB
B2
LSB-JUSTIFIED FORMAT 20 BITS
Objective specification
TDA1388T
Fig.3 Input formats.
Philips Semiconductors
Objective specification
Bitstream continuous calibration filter-DAC for CD-ROM audio applications
TDA1388T
handbook, full pagewidth
L3MODE t h;MA tLC t s;MA L3CLOCK tHC t h;MA t s;MA
Tcy t s;DAT t h;DAT
L3DATA
BIT 0
BIT 7
MGD016
Fig.4 Timing address mode.
handbook, full pagewidth
thalt
thalt
L3MODE tLC t s;MT tHC Tcy t h;MT
L3CLOCK
t h;DAT
t s;DAT
t h;DAT
L3DATA write
BIT 0
BIT 7
MGD017
Fig.5 Timing for data transfer mode.
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Philips Semiconductors
Objective specification
Bitstream continuous calibration filter-DAC for CD-ROM audio applications
TDA1388T
handbook, full pagewidth
thalt
L3MODE
L3CLOCK
L3DATA
address
data byte #1
data byte #2
address
MGD018
Fig.6 Multibyte transfer.
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). All voltage referenced to ground, VDDD = VDDA = VDDO 5 V; Tamb = 25 C, unless otherwise specified. SYMBOL VDD Txtal(max) Tstg Tamb Ves supply voltage maximum crystal temperature storage temperature operating ambient temperature electrostatic handling note 2 note 3 Notes 1. All VDD and VSS connections must be made to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor. 3. Equivalent to discharging a 200 pF capacitor via a 2.5 H series inductor. PARAMETER CONDITIONS note 1 - - -65 -20 -3000 -300 MIN. MAX. 7.0 +150 +125 +70 +3000 +300 V C C C V V UNIT
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Philips Semiconductors
Objective specification
Bitstream continuous calibration filter-DAC for CD-ROM audio applications
THERMAL CHARACTERISTICS SYMBOL Rth j-a SOP28 SSOP28 PARAMETER thermal resistance from junction to ambient in free air tbf tbf VALUE
TDA1388T
UNIT K/W K/W
DC CHARACTERISTICS VDDD = VDDA = VDDO = 5 V; Tamb = 25 C; RL = 5 k; all voltages referenced to ground (pins 1, 13 and 23); unless otherwise specified. SYMBOL VDDD VDDA VDDO IDDD IDDA IDDO Ptot VIH VIL |ILI| Cin Vref Rout(ref) RCONV Io(max) PARAMETER digital supply voltage analog supply voltage operational amplifier supply voltage digital supply current analog supply current operational amplifier supply current total power dissipation CONDITIONS note 1 note 1 note 1 at digital silence at digital silence at digital silence note 2 MIN. 4.5 4.5 4.5 - - - - 5.0 5.0 5.0 7.0 5.0 10 110 - - - - TYP. MAX. 5.5 5.5 5.5 - - - - UNIT V V V mA mA mA mW
Digital input pins HIGH level input voltage LOW level input voltage input leakage current input capacitance 0.7VDDD - - - VDDD + 0.5 V 0.3VDDD 10 10 V A pF
Analog audio pins reference voltage output reference resistance current-to-voltage conversion resistor maximum output current (THD+N)/S < 0.1% RL = 32 (THD+N)/S < 0.1% RL = 16 CL Notes 1. All power supply pins (VDD and VSS) must be connected to the same external power supply unit. 2. No operational amplifier load resistor. 3. Load capacitance larger than 50 pF, a 22 H inductor in parallel with a 270 resistor must be inserted between the load and the operational amplifier output. output load capacitance note 3 with respect to VSSA 0.45VDDA - - - - - 0.5VDDA 3 2.0 88 44 - 0.55VDDA - - - - 50 V k k mA mA pF
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Philips Semiconductors
Objective specification
Bitstream continuous calibration filter-DAC for CD-ROM audio applications
TDA1388T
AC CHARACTERISTICS (ANALOG) VDDD = VDDA = VDDO = 5 V; fi = 1 kHz; Tamb = 25 C; RL = 5 k all voltages referenced to ground (pins 1, 13 and 23); unless otherwise specified. SYMBOL RES VFS(rms) VDC(os) PARAMETER resolution output voltage swing (RMS value) output voltage DC offset with respect to reference voltage level Vref supply voltage ripple rejection VDDA and VDDO unbalance between the 2 DAC voltage outputs crosstalk between the 2 DAC voltage outputs for line outputs crosstalk between the 2 DAC voltage outputs for headphone outputs (THD+N)/S total harmonic distortion plus noise as a function of signal for the line output note 1 CONDITIONS - 0.9 - MIN. - 1.0 20 TYP. MAX. 18 1.1 - V mV UNIT bits
SVRR
- fripple = 1 kHz; Vripple(p-p) = 100 mV(peak); Cpin = 10 F maximum volume RL = 5 k, note 2 RL = 16 k, note 2 RL = 32 k, note 2 0 dB signal RL = 5 k -60 dB signal RL = 5 k 0 dB signal RL = 16 k 0 dB signal RL = 32 k -60 dB signal RL = 16 k or RL = 32 k - - - - - - - - - - - - - - 90
40
-
dB
|Vo| ct
0.1 90 60 65 -85 0.006 -35 1.8 -65 0.056 -70 0.032 -35 1.8 95
- - - - -80 0.013 -30 3.2 -60 0.1 - - -30 3.2 -
dB dB dB dB dB % dBA % dB % dB % dBA % dBA
total harmonic distortion plus noise as a function of signal for the headphone output
S/N Notes
signal-to-noise ratio at bipolar zero
A weighting; at code 00000H
1. Proportional to VDDA. 2. One output digital silence, the other maximum volume.
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Philips Semiconductors
Objective specification
Bitstream continuous calibration filter-DAC for CD-ROM audio applications
TDA1388T
AC CHARACTERISTICS (DIGITAL) VDDD = VDDA = VDDO = 4.5 to 5.5 V; Tamb = -20 to +70 C; RL = 5 k; all voltages referenced to ground (pins 1, 13 and 23); unless otherwise specified. SYMBOL Tcy tCWL tCWH BR fsys fWS tr tf tBCK(H) tBCK(L) ts;DAT th;DAT ts;WS th;WS clock cycle fsys LOW level pulse width fsys HIGH level pulse width clock input = data input rate system clock frequency word selection input frequency rise time fall time bit clock HIGH time bit clock LOW time data set-up time data hold time word selection set-up time word selection hold time fsys = 256fs fsys = 384fs PARAMETER CONDITIONS fsys = 256fs fsys = 384fs MIN. 81.3 54.2 22 22 - - 8.192 - - - 55 55 10 20 20 10 TYP. 88.6 59.1 - - MAX 122 81.3 - - - - 18.432 48 20 20 - - - - - - MHz kHz ns ns ns ns ns ns ns ns UNIT ns ns ns ns
Serial input data timing (see Fig.7) 64fs 48fs - 44.1 - - - - - - - -
Fig.7 Timing and input signals.
1995 Dec 08
18
Philips Semiconductors
Objective specification
Bitstream continuous calibration filter-DAC for CD-ROM audio applications
TEST AND APPLICATION INFORMATION
TDA1388T
handbook, full pagewidth
+5 V 100 F 4.7 4.7 100 F 100 nF
100 nF
(1)
100 nF L3 (2)
(1)
SYSTEM CLOCK INPUT I S-BUS OR LSB-JUSTIFIED SERIAL INPUT DATA
2
330 F 100 nF VSSD VDDD VSSA VDDA VSSO1 VDDO Vref 23 22 1 28 13 12 SYSCLK 14 6 BCK WS DATA 9 10 11 5 FILTCL VOL 1 nF 47 F 4.7 F 100 L R1 10 k 100 nF 10 F
IF1 IF2 ACP from MICROCONTROLLER APPL2/CL APPL1/MO APPL0/DA SYSSEL
4 7 8 19 18 17 16 15 24 2 27
TDA1388
3 HPINL HPOUTL HPOUTR
330 F
FILTCR 330 F VOR HPINR 1 nF 47 F 4.7 F 100 R R1 10 k
VSSO2 TC
25 21 20 26
MGD152
(1) Optional. (2) Chip inductor BLM32A07.
Fig.8 Application diagram.
1995 Dec 08
19
Philips Semiconductors
Objective specification
Bitstream continuous calibration filter-DAC for CD-ROM audio applications
PACKAGE OUTLINES SO28: plastic small outline package; 28 leads; body width 7.5 mm
TDA1388T
SOT136-1
D
E
A X
c y HE vMA
Z 28 15
Q A2 A1 pin 1 index Lp L 1 e bp 14 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 18.1 17.7 0.71 0.69 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT136-1 REFERENCES IEC 075E06 JEDEC MS-013AE EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-24 97-05-22
1995 Dec 08
20
Philips Semiconductors
Objective specification
Bitstream continuous calibration filter-DAC for CD-ROM audio applications
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
TDA1388T
SOT341-1
D
E
A X
c y HE vMA
Z 28 15
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 14 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 10.4 10.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.1 0.7 8 0o
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 REFERENCES IEC JEDEC MO-150AH EIAJ EUROPEAN PROJECTION
ISSUE DATE 93-09-08 95-02-04
1995 Dec 08
21
Philips Semiconductors
Objective specification
Bitstream continuous calibration filter-DAC for CD-ROM audio applications
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all SO and SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering SO Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. SSOP
TDA1388T
Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). METHOD (SO AND SSOP) During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1995 Dec 08
22
Philips Semiconductors
Objective specification
Bitstream continuous calibration filter-DAC for CD-ROM audio applications
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA1388T
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1995 Dec 08
23
Philips Semiconductors - a worldwide company
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Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCD47 (c) Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
513061/1100/01/pp24 Document order number: Date of release: 1995 Dec 08 9397 750 00516

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