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W83C42 KEYBOARD CONTROLLER
GENERAL DESCRIPTION
The W83C42 keyboard controller is programmed to support the IBM(R) compatible personal computer keyboard serial interface. The keyboard controller receives serial data from the keyboard, checks the parity of the data, translates the scan code, and presents the data to the system as a byte of data in its output buffer. The controller will interrupt the system when data is placed in its output buffer. The byte of data will be sent to the keyboard serially with an odd parity bit automatically inserted. The keyboard is required to acknowledge all data transmissions. No transmission should be sent to the keyboard until acknowledge is received for the previous byte sent. Winbond Electronics Corporation has developed a fast keyboard controller and BIOS to improve the performance of IBM PC/AT(R) 386TMDX/SX and 486TMDX/SX machines and their compatibles. Hardwire methodology is used in this keyboard controller instead of software implementation, as in the traditional 8042 keyboard BIOS. This enables the keyboard controller to respond instantly to all commands sent from the keyboard to the CPU BIOS. The keyboard controller enables popular programs such as AutoCAD(R), Microsoft(R) WindowsTM 3.1, NOVELL(R), and other programs to run much faster.
FEATURES
* * * * * * *
Supports IBM PC/AT 386DX/SX and 486 DX/SX system designs Runs much faster than traditional keyboard controllers Host interface compatible with traditional keyboard controller 6MHz~12MHz operating frequency Communicates with keyboard directly High-reliability CMOS technology Available packages: 40-pin DIP, 44-pin PLCC
IBM and PC/AT are registered trademarks of International Business Machines Corporation. 386 and 486 are trademarks of Intel Corporation. AutoCAD is a registered trademark of Autodesk, Inc. Microsoft is a registered trademark and Windows is a trademark of Microsoft Corporation. NOVELL is a registered trademark of Novell, Inc.
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Publication Release Date: July 1994 Revision A3
W83C42
PIN CONFIGURATION
40-pin DIP
T0 XIN XOUT RESET VDD CS VSS RD A2 WR NC D0 D1 D2 D3 D4 D5 D6 D7 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VDD T1 P27 (KDAT) P26 (KCLK) P25 (IEMP) P24 (INT) P17 (KINH) P16 (DISP) P15 (JUMP) P14 (RAM) P13 P12 P11 P10 NC
VDD
P23 P22 P21 (GA20) P20 (RC)
44-pin PLCC
V D D CS V SS RD A2 WR NC NC D0 D1 D2 D3
X
/ R E S E T
X
X O U T
4
X
X I N
3
X
T 0
2
X
N C
1
X
V D D
44
X
T 1
43
X
P 2 7
P 2 6
P 2 5
X
5 76 8 9 10 11 12 13 14 15 16 17 18 19
X X X X X 14 X X X X 15 X X X
20 21
X X
22 23 24
X X X
42 41 40 39 38 37 36 35 34 33 32 31 30 25 26 27 28 29
X X X X X X X X X X X X X X X X X
P24 P17 P16 P15 P14 NC P13 P12 P11 P10 NC
D 4
D 5
D 6
D 7
V S S
N C
P 2 0
P 2 1
P 2 2
P 2 3
V D D
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W83C42
PIN DESCRIPTION
PIN NO. (40-pin DIP) 1 2 3 4 5 6 7 8 9 10 11, 26 12, 13, 14, 15, 16, 17, 18, 19 20 21 22 23 24 25 27 28 29 30 31 32 33 34 PIN NO. (44-pin PLCC) 2 3 4 5 6 7 8 9 10 11 1, 12, 13, 23, 29, 34 14, 15, 16, 17, 18, 19, 20, 21 22 24 25 26 27 28 30 31 32 33 35 36 37 38 I/O I I O I I I I I I/O NAME T0 XIN XOUT RESET VDD CS VSS RD A2 WR NC D0-D7 FUNCTION K/B Clock Input Crystal Clock I/P Crystal Clock O/P Chip Reset Optional +5V Power Supply Chip Select Optional Ground Power I/O Read Connect to Address A2 I/O Write Reserved Data Bus D0 - D7
O O I/O I/O I/O I/O I/O I/O I I I I
VSS P20 P21 P22 P23 VDD P10 P11 P12 P13 P14 P15 P16 P17
Ground Power Supply Bit 0 of Port 2 (RCB: System Reset) Bit 1 of Port 2 (GA20: GATE A20) Bit 2 of Port 2 Bit 3 of Port 2 Optional +5V Power Supply Bit 0 of Port 1 Bit 1 of Port 1 Bit 2 of Port 1 Bit 3 of Port 1 Bit 4 of Port 1 (RAM Jumper Select) Bit 5 of Port 1 (JUMP) Bit 6 of Port 1 (Display Select) Bit 7 of Port 1 (K/B Inhibit Switch)
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Publication Release Date: July 1994 Revision A3
W83C42
Pin Description, continued
PIN NO. (40-pin DIP) 35 36 37 38 39 40
PIN NO. (44-pin PLCC) 39 40 41 42 43 44
I/O O O O O I -
NAME P24 P25 P26 P27 T1 VDD
FUNCTION Bit 4 of Port 2 (OBF O/P Interrupt) Bit 5 of Port 2 (I/P Buffer Empty) Bit 6 of Port 2 (K/B Clock O/P) Bit 7 of Port 2 (K/B Data O/P) K/B Data Input +5V Power Supply
BLOCK DIAGRAM
TRANSMIT CONTROL T0 T1 RECEIVE CONTROL SCAN CODE ROM
XOUT XIN WR RD CS A2 RESET
TRANSMIT REGISTER
HARDWIRE CONTROL & SELECT LOGIC
STATUS REGISTER
R64
STATUS BUFFER REGISTER
INPUT & OUTPUT PORT INTERFACE
D0- D7
DATA BUFFER REGISTER
W60 W64
INPUT BUFFER REGISTER
P10 P11 P12 P13 P14 (RAM Select) P15 (Manufacture Mode) P16 (Display) P17 (KBNH)
R60
OUTPUT BUFFER REGISTER OUTPUT PORT INTERFACE
P20 (RC) P21 (Gate A20) P22 P23 P24 P25 P26 (Keyboard Clock) P27 (Keyboard Data)
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W83C42
AC TIMING
NO. T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 DESCRIPTION Address Setup Time from WR Address Setup Time from RD WR Strobe Width RD Strobe Width Address Hold Time from WR Address Hold Time from RD Data Setup Time Data Hold Time Gate Delay Time from WR RD to Drive Data Delay RD to Floating Data Delay Data Valid After Clock Falling (SEND) K/B Clock Period K/B Clock Pulse Width Data Valid Before Clock Falling (RECEIVE) K/B ACK After Finish Receiving RC Fast Reset Pulse Delay (8 MHz) RC Pulse Width (8 MHz) Transmit Timeout Data Valid Hold Time XIN/XOUT Period ( 6-12 MHz ) 0 83 167 20 10 4 20 2 6 2 3 0 MIN. 0 0 20 20 0 0 50 0 10 20 20 4 MAX. UNIT nS nS nS nS nS nS nS nS nS nS nS S S S S S S S mS S nS
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Publication Release Date: July 1994 Revision A3
W83C42
TIMING WAVEFORMS
Write Cycle Timing
A2, CS T1 T5
T3 ACTIVE
WR
T7
T8
D0 - D7
DATA IN
T9 A20 OUTPUT PORT T17 FAST RESET PULS RC FE COMMAND T18
Read Cycle Timing
A2, CS AEN T2 T4 ACTIVE T10 T11 T6
RD
D0 - D7
DATA OUT
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W83C42
Send Data to K/B
CLOCK ( KCLK ) T12 SERIAL DATA ( KDAT ) T14 T13 T16
START
D0
D1
D2
D3
D4
D5
D6
D7
P
STOP
T19
Receive Data from K/B
CLOCK ( KCLK ) T15 SERIAL DATA ( T1 ) START T20 D0 D1 T14 D2 D3 T13 D4 D5 D6 D7 P
STOP
XIN/XOUT Clock
XIN CLK T21
ABSOLUTE MAXIMUM RATINGS
PARAMETER Ambient Operating Temperature Storage Temperature Supply Voltage to Ground Potential Applied Input/Output Voltage Power Dissipation RATING -0 to +85 -65 to +150 -0.3 to +7.0 -0.3 to +7.0 50 UNIT C C V V mW
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
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Publication Release Date: July 1994 Revision A3
W83C42
ELECTRICAL CHARACTERISTICS & CAPACITANCE
(Ta = 0 C to +70 C, VDD = +5V 5%)
SYMBOL VDD TA VIH VIL VOH VOL RIP ILI ILO IOL CL
DESCRIPTION Power Supply Operating Temperature High Level Voltage for TTL Min. I/P Low Level Voltage for TTL Max. I/P High Level Voltage for TTL Min. O/P Low Level Voltage for TTL Max. O/P Min. I/P Resist I/P Leakage Current O/P Leakage Current O/P Sink Current O/P Load Capacity
MIN. 4.75 0 2.0 -0.3 VDD -0.5
TYP. 5.0 25
MAX. 5.25 70 VDD 0.8
UNIT V V V V V
0.5 10K -10 -10 4 15 50 10 10
V A A mA pF
STATUS REGISTER
The status register is an 8-bit read-only register at I/O address hex 64 that holds information about the state of the keyboard controller and interface. It may be read at any time. BIT 0 1 2 BIT DESCRIPTION Output Buffer Full Input Buffer Full System Flag 0: Output Buffer Empty 1: Output Buffer Full 0: Input Buffer Empty 1: Input Buffer Full This bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller. It is set to 0 after a power-on reset 0: Data Byte 1: Command Byte 0: Keyboard is Inhibited 1: Keyboard is Not Inhibited 0: No Transmit Time Out Error 1: Transmit Time Out Error FUNCTION
3 4 5
Command/data Inhibit Switch Transmit Time Out
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W83C42
Status Register, continued
BIT 6 7
BIT DESCRIPTION Receive Time Out Parity Error
FUNCTION 0: No Receive Time Out Error 1: Receive Time Out Error 0: Odd Parity (No Error) 1: Even Parity (Error)
OUTPUT BUFFER
The output buffer is an 8-bit read-only register at I/O address hex 60. The keyboard controller uses the output buffer to send the scan code received from the keyboard and data bytes required by command to the system. The output buffer should be read only when the output buffer full bit in the register is 1.
INPUT BUFFER
The input buffer is an 8-bit write-only register at I/O address hex 60 or 64. Writing to address hex 60 sets a flag that indicates a data write; writing to address hex 64 sets a flag that indicates a command write. Data written to I/O address hex 60 are sent to the keyboard (unless the keyboard controller is expecting a data byte) following the controller's input buffer only if the input buffer full bit in the status register is set to 0.
I/O PORTS
The keyboard controller has two 8-bit I/O ports and two test inputs. One of the ports is assigned for input and the other for output. The controller uses the test inputs to read the state of the keyboard's clock line and data line. The following figures show bit definitions for the input, output, and test-input ports.
(A) Input Port Definitions
BIT 0 1 2 3 4 Undefined Undefined Undefined Undefined RAM on System Board 0: Disable 2nd 256 KB of System Board RAM 1: Enable 2nd 256 KB of System Board RAM Manufacturing Jumper Installed 0: Manufacturing Jumper 1: Jumper Not Installed FUNCTION
5
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Publication Release Date: July 1994 Revision A3
W83C42
Input Port Definitions, continued
BIT 6
FUNCTION Display Type Switch 0: Primary Display Attached to Color/graphics 0: Primary Display Attached to Monochrome Keyboard Inhibit Switch 0: Keyboard Inhibited 1: Keyboard Not Inhibited
7
(B) Output Port Definitions
BIT 0 1 2 3 4 5 6 7 System Reset Gate A20 Undefined Undefined Output Buffer Full Input Buffer Empty Keyboard Clock (Output) Keyboard Data (Output) FUNCTION
(C) Test-Input Definitions
BIT 0 1 FUNCTION Keyboard Clock (Input) Keyboard Data (Input)
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W83C42
COMMANDS (I/O ADDRESS HEX 64)
COMMAND 20 60 FUNCTION Read Command Byte of Keyboard Controller Write Command Byte of Keyboard Controller BIT 7 6 5 4 3 2 1 0 AA Self-test BIT 00 01 02 03 04 AB AD AE C0 D0 D1 E0 F0-FF BIT DEFINITIONS No Error Detected K/B Clock Line is Stuck Low K/B Clock Line is Stuck High K/B Data Line is Stuck Low K/B Data Line is Stuck High BIT DEFINITIONS Reserved IBM PC Compatible Mode IBM PC Mode Disable Keyboard Inhibit Override System Flag Reserved Enable Output Buffer Full Interrupt
Interface Test Disable Keyboard Feature Enable Keyboard Interface Read Input Port Read Output Port Write Output Port Read Test Inputs Pulse Output Port
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Publication Release Date: July 1994 Revision A3
W83C42
APPLICATION CIRCUIT
Asynchronous
2 3 RESETB SA2 IORB IOWB D0 - D7 4 1 39 9 6 5 8 10 12 13 14 15 16 17 18 19 7
X1 X2 RESET T0 T1 A2 CS VDD RD WR D0 D1 D2 D3 D4 D5 D6 D7 VSS
VDD P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24/OB P25/BF P26/KCLK P27/KDAT NC
25 27 28 29 30 31 32 33 34 21 22 23 24 35 36 37 38 11 RCB GATE A20
RAM SELECT JUMPER MANUFACTURING MODE JUMPER DISPLAY TYPE SWITCH
KEYBOARD INHIBIT SWITCH KEYBOARD INTERRUPT
KEYBOARD CLOCK KEYBOARD DATA VD
D
U?A 1 74ALS04 2 1
U?A 2 VCC 7407 U?B 3 7407 4 KEYBOARD DATA KEYBOARD CLOCK
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W83C42
Application Circuit, continued
Synchronous
PCLK
2 3
X1 X2 RESET T0 T1 A2 CS RD WR D0 D1 D2 D3 D4 D5 D6 D7 P10 P11 P12 P13 P14/RAM P15/MOD P16/DIS P17/INH P20/RCB P21/A20 P22 P23 P24 P25 P26/KCLK P27/KDAT 27 28 29 30 31 32 33 34 21 22 23 24 35 36 37 38 RCB GATE A20
RESETB SA2 IORB IOWB D0 - D7
4 1 39 9 6 8 10 12 13 14 15 16 17 18 19
RAM SELECT JUMPER MANFACTURING MODE JUMPER DISPLAY TYPE SWITCH
KEYBOARD INHIBIT SWITCH KEYBOARD INTERRUPT
KEYBOARD CLOCK KEYBOARD DATA VDD
U?A 1 74ALS04 2 1
U?A 2 7407 U?B 3 7407 4 KEYBOARD DATA VDD KEYBOARD CLOCK
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Publication Release Date: July 1994 Revision A3
W83C42
PACKAGE DIMENSIONS
40-pin PDIP
Symbol
Dimension in inch
Dimension in mm
Min. Nom. Max.
0.210 0.010 0.150 0.016 0.048 0.008 0.155 0.018 0.050 0.010 2.055 0.590 0.540 0.090 0.120 0 0.630 0.650 0.600 0.545 0.100 0.130 0.160 0.022 0.054 0.014 2.070 0.610 0.550 0.110 0.140 15 0.670 0.090
Min. Nom. Max.
5.33 0.25 3.81 0.41 1.22 0.20 3.94 0.46 1.27 0.25 52.20 14.99 13.72 2.29 3.05 0 16.00 16.51 15.24 13.84 2.54 3.30 4.06 0.56 1.37 0.36 52.58 15.49 13.97 2.79 3.56 15 17.02 2.29
D 40 21
A A1 A2 B B1 c D E E1 e1 L
a
1
E
eA S
1 S
2
20 E c A
1
Notes:
1. Dimensions D Max & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and . are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec.
AA
Base Plane Seating Plane
L B B1 e1
a
eA
44-pin PLCC
HD D
6 1 44 40
Symbol
39
Dimension in inch
Dimension in mm
Min. Nom. Max.
0.185 0.020 0.145 0.150 0.155 0.026 0.028 0.032 0.016 0.018 0.022 0.008 0.010 0.014
Min. Nom. Max.
4.70 0.51 3.68 0.66 0.41 0.20 3.81 0.71 0.46 0.25 3.94 0.81 0.56 0.36
7
EH
E
G
E
17
29
18
28
c
A A1 A2 b1 b c D E e GD GE HD HE L y
Notes:
0.648 0.653 0.658 16.46 16.59 16.71 0.648 0.653 0.658 16.46 16.59 16.71 0.050 BSC 1.27 BSC
0.590 0.610 0.630 14.99 15.49 16.00 0.590 0.610 0.630 14.99 15.49 16.00 0.680 0.690 0.700 17.27 17.53 17.78 0.680 0.690 0.700 17.27 17.53 17.78 0.090 0.100 0.110 0.004 2.29 2.54 2.79 0.10
L
2
AA
e Seating Plane GD
b b1
1
A y
1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec.
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W83C42
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792646 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27516023 FAX: 852-27552064
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2730 Orchard Parkway, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
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Publication Release Date: July 1994 Revision A3

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