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ASCELL3912
ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell
Preliminary Data Sheet
ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell - Preliminary Data Sheet ASCELL3912
Austria Mikro Systeme International AG
Key Features
* * * * * * * * * * * * * Supports triple band operation: Europe 868 MHz and 433 MHz-, US and Japan 315 MHz ISM band. Designed to be conform to EN 300 220, and FCC 47 CFR Ch.1 par.15 requirements. Provides highly reliable packet oriented data transmission in blocks of 128 bit. Event oriented single message transmission and status oriented and continuous message transmission supported. Special transmission protocol for high reliability even in presence of burst interferer (e.g. GSM) implemented. RX sensitivity of the receiver typical -100 dBm. Supports clock for an external C and allows clock free total shut down of the whole system. Wide supply range between 2.7 to 5.5 V. Low RX current, typical 10 mA @ 2.4 V. Low idle mode current, typical 1.2mA. Wide operating temperature range from -40 C to +85 C. Only a low cost XTAL for 25 ppm (868 MHz) or 50 ppm (433 and 315 MHz) reference frequency tolerance required. Minimum only 1 XTAL and 4 capacitors externally required.
General Description
The ASCELL3912 is a low power, triple ISM band (868 / 433 / 315 MHz), single channel FSK receiver designed to work in a remote control link together with the SC3911 transmitter system cell. The ASCELL3912 performs packet oriented data transmission, in a single message- or continuosmessage mode using a special protocol to ensure high reliability even in presence of strong pulsed interferers in close adjacent bands like e.g. GSM. A general bi-directional micro-controller (C) interface is provided, to support the C with clockand reset- signal, and to operate the highly efficient power up/down management. As external components the SC3911 need at minimum only a reference XTAL, and 4 capacitors.
Applications
* * * * * * Key-less car entry systems. Short range packet oriented data transmission. Security applications and alarm systems. Domestic remote control systems. Industrial remote control systems. Remote metering.
Rev. A, February 2000
Page 2 of 14
ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell - Preliminary Data Sheet ASCELL3912
Austria Mikro Systeme International AG
RF+ RFLC+ LCXTAL+ XTALAVDD AGND GMC RFGND
1 2 3
20 19 18
DVDD DATA D_CLK D_EN WAKEUP RE_INT C_CLK TEST2 TEST1 DGND
ASCELL3912
TSSOP-20
4 5 6 7 8 9 10
17 16 15 14 13 12 11
This pin-out is preliminary and will change for the real implementation!
This document contains information on products under development. Austria Mikro Systeme International AG reserves the right to change or discontinue this product without notice.
1
Functional Description
The Figure 1 shows the block diagram of the ASCELL3912. The analog part of the ASCELL3912 consists of a direct conversion receiver, a triple band RF synthesizer and the DC-cancellation. The digital part includes the burst interference resistant protocol decoder the control logic and the C interface.
LC +
LC -
G M C
I RF+ 10dB
VDD
DEM
RFQ
Digital Power Supply
GND
RFGND
-Det % n CLK GEN
AVDD
AGND
RF Power Supply
90 OSC PLL XO
RF-SEL RF-Power
DC-Offset Bandwith CTRL
XTAL+ XOT[3:0] XO-CLK LNA
AFC
XTAL-
STATE REGISTER
SETUPREGISTER
PROTOCOL DECODER
FIR DATARECOVERY SYNC
XO-SEL TEST1
Scan Test
Functional Test
INTERFACE
1/STR
Sleeptime control
ASCELL3912
TE ST 2
C _C LK
RE _I NT
W AK E_ UP
N D_ E
K D_ CL
DA TA
Figure 1:
Block diagram of the ASCELL3912.
Rev. A, February 2000
Page 3 of 14
ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell - Preliminary Data Sheet ASCELL3912
Austria Mikro Systeme International AG
1.1 Analog Receiver Part
The input signal is a low to moderately high modulation index continuous phase frequency shift keying modulated RF signal around a carrier Fc. This signal is amplified by the low noise amplifier (LNA) and fed to the In-phase and Quadrature-phase mixers (I/Q mixers). The mixers convert the RF signal directly to base band. The local oscillator signal for the I/Q mixers is generated by the on-chip PLL. The two base band signals (signals I and Q) are filtered and further amplified. After DC offset cancellation to remove the static and quasi-static DC offsets and to ensure fast wake-up of the receiver, the signals are hard limited. The rectangular signals I' and Q' are fed to the digital part where demodulation and the further signal processing is applied. 1.1.1 RF Synthesizer Frequency synthesis is performed by a conventional synthesizer consisting of a phase detector, a charge pump, a voltage controlled oscillator working at 315~868.3 MHz, and a feedback divider by 16 (315.00MHz); 32 (315, 433.92MHz), or 64 (868.3MHz). A truth table for the different frequencies is given in Table 1.
FXOSC / MHz Multiplier 19,6875 13.5600 13.5672 Table 1: 16 32 64 FC/ MHz 315.000 433.920 868.300 FB1 H L L FB0 L H L RF-SEL XO-SEL L L H L H H
Quartz and RF output frequencies.
Note: XO-SEL and RF-SEL are intenal generated Signals from the FB[1:0] bits of the setup information.
1.1.2 LNA The amplification of the LNA can be switched in two states. The gain can be switched of about 10dB with the LNA bit of the setup command.
Note: LNA is one bit of the setup information.
1.1.3 I/Q Down Converter The ASCELL3912 contains a high performance quadrature down converter with low DC offset and high isolation of RF- and LO-ports. 1.1.4 Base Band Filter To achieve optimum blocking performance, the base band filter is realized in two separated circuit blocks. The first filter block removes high level blocking signals out of receive band, the second filter block serves for high selectivity of adjacent interferers. 1.1.5 DC-Cancellation and Adjustment of Lower Cut-Off Frequency The DC offset is removed by a first order high-pass with switchable limit frequency. In the first step the frequency offset of transmitter and receiver is not compensated, therefore the lower band limit is about 10 kHz. In the second step, the receiver frequency is adjusted and the lower limit frequency of the DC-block is set to about 40 kHz and therefore the total bandwidth of pass band is reduced. At the output of the DC block is a switch to initialize the DC-offset in the powerup instant, at the instant of switching, and after appearance of high level interfering signals.
Rev. A, February 2000
Page 4 of 14
ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell - Preliminary Data Sheet ASCELL3912
Austria Mikro Systeme International AG
1.2 Digital Controller
The principal function of the digital controller is demodulation, bit synchronization and the detection of the received data protocol, according to the definition of transmitted bits. Furthermore, a first syntax check and plausibility check of detected data is provided. A data protocol received completely is put into a receive buffer, where a micro controller (C) can read it out via a serial interface. The receiver can be externally configured with several operation parameters, LNA gain setting, used frequency band, and timing constant for the watch dog timer. The serial interface also allows to configure the digital controller by the C. The receiver writes the state information into a status register. This status information can be read out from the C out of the status register of the receiver. 1.2.1 Microprocessor Clock The microprocessor clock frequency FCLK is generated by dividing the XTAL frequency FXOSC by 4 if XO-SEL is H and by dividing the XTAL frequency FXOSC by 6 if XO-SEL is L.
Note: XO-SEL and RF-SEL are internal generated signals from the FB[1:0] bits of the setup information.
1.2.2 ASCELL3912 Digital Part Timing In Figure 2 the timing of a complete receive sequence can be seen. Transmission starts at an arbitrary point in time. First the crystal oscillator is switched on. A minimum time of 5 ms is allowed for the frequency to settle to the final value. Then the receiver executes a wake-up sequence consisting of 6 wake-up bursts. The wake-up bursts are unequally spaced to guarantee interference free detection of an ongoing transmission also in the presence of burst interferers. During a wake-up burst the receiver scans for an active transmission on the air interface. The wake-up sequence is optimized to combat GSM and CT2 type interferers. After an ongoing transmission has been detected the receiver goes to receiving mode, the WAKE_UP line goes high, and reception of data starts. Depending on the number of interferers present, reception of all data may take up to 3 data blocks. As soon as all data has been detected successfully, the RE_INT pin issues a positive pulse, to indicate the availability of data, and the internal data ready flag (DR) in the ASCELL3912 state register is set. The RE_INT line may be used to trigger a interrupt procedure, which is executed at the availability of data. When data is read out by the micro controller the internal data ready flag (DR) in the RX-status register is cleared and it is only set, when a complete data sequence has received again. No further pulse is issued on the RE_INT line, but the micro controller has to poll for new data during an ongoing reception. If transmission stops, the WAKE_UP line goes low and a pulse is issued on the RE_INT line to indicate the termination of transmission at CMT. In Figure 2 also the timing where the microprocessor clock (C_CLK) is active is shown. The clock is active with the start of the detection phase of the SC3911. The clock is shut down 16 clock cycles (TCAI) after the falling edge of the second interrupt on the RE_INT pin.
Rev. A, February 2000
Page 5 of 14
ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell - Preliminary Data Sheet ASCELL3912
Austria Mikro Systeme International AG
TXStatus
SYNC 13.80ms TX-Start
DATA 12.28ms
SYNC 13.80ms
DATA 12.28ms
SYNC 13.80ms
DATA 12.28ms
SYNC 13.80ms
DATA 12.28ms
SYNC 13.80m s
DATA
Receiver-sleep-time = (STR +1) * 20 ms Wake-Up trigger start detection TXOS=5ms Wake up RX TDET1=26.08ms TDET0=12.28ms
TX- stop
Wake-Up trigger TDET2=64.44ms RX-sleep TSTOP30ms
RXStatus
XO- Receiver Wake up sequence Set max. 22.25ms
Data reception and store data
Data reception
XOSet
Interface-lines: Shown for TDET1 C_CLK WAKE_UP RE_INT TBWI 0.5ms TINT = 0.5ms Internal flags: RX DR C-readout data detection completed shown for TDET1 r r r r r Shown for TDET1 TCAI = 16/FCLK
Detection with 0 GSM-interferer
TDET0=12.28ms
Detection with 1 GSM interferer or in 50% Duty Cycle ModeTDET1=26.08ms Detection with 2 GSM interferer Active time after last useful data Cristal Oscillator setup-time TDET2=64.44ms TSTOP 30ms TXOS =5ms
Figure 2:
ASCELL3912 basic timing.
Note: The Interface timing and the timing of the internal flags are shown in Figure 2 for a detection time of TDET1.
1.2.3 Receiver Configuration The configuration register can be loaded from a C via the serial interface. The Table 2 below shows the contents of the configuration register. Bit b0 is the first transmitted bit. The setup contains the LNA set, frequency band and the sleep time interval of the receiver.
bit # 0 [1..2] Name LNA FB[1:0] Description LNA gain switch Configuration L= LNA Gain is high H= LNA Gain is -10dB Comments default default
Frequency band select with L, L (FB1, FB0) = 868.3 MHz FB1 is MSB L, H = 433.92 MHz H, L = 315 MHz H, H = not used Sleep time interval set of the receiver, with STR5 is MSB tsleep = (STR + 1) * 20ms
[3..8]
STR[5:0]
Note: for STR = 00h the witing period between two consecutive wakeup cycles will be 148 bit.
Table 2: Format of the configuration Register
Rev. A, February 2000
Page 6 of 14
ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell - Preliminary Data Sheet ASCELL3912
Austria Mikro Systeme International AG
1.2.4 Receiver Status Table 3 below shows the format of the state register. Bit b0 is the first which is transmitted by a readout of the C. The status register contains the information about a successful received date, active receiver and the information about the quality of the received signal.
bit # 0 1 Name DR RX Description Data received a complete message was received Receiver is active Status L= no data received H= data received successfully L= receiver not active H= data reception in progress
Note: This bit is set by the receiver when 6 bytes of a packet are correct. This bit in the status register is necessary for the comfort-orientated functions of the central locking functions.
Comments
[2..3]
RQ[1:0]
Signal quality indicates how many data packets are necessary for a complete message
L, L (RQ1, RQ0) = 1 packet L, H = 2 packets H, L = 3 packets H, H =4 packets
Table 3:
Format of the status register.
1.2.5 C Interface The ASCELL3912 contains a direct interface to a micro controller (C). The C interface of the ASCELL3912 consist of the following five pins: "Transmit/Received data input/output" (DATA). A bi-directional serial data line, with states "H" (recessive, or weak pull-up) and "L" (dominant). "Active "H" transmit data enable" (D_EN) "Transmit data clock input" (D_CLK). "Active "H" C interrupt output " (RE_INT). "Active "H" C wakeup output " (C_WAKEUP). "C clock output " (C_CLK).
1.2.5.1 Instruction Set
The following table shows the instruction set of the interface. The first two bits are the operation code, which determine the direction of the data transfer and which data is transferred.
Operation code 0 0 1 1 1 0 0 1 LNA Z Z Z FB1 LNA DR B0-b0 FB0 FB1 RX STR5 FB0 RQ1 Instruction or Data Comment
STR4 STR5 RQ0
STR3 STR4
STR2 STR3
STR1 STR2
STR0 STR1 STR0
Write ASCELL3912 setup Read ASCELL3912 setup Read ASCELL3912-State B15-b7 Read ASCELL3912-Data
Table 4:
Overview of the instruction set.
Rev. A, February 2000
Page 7 of 14
ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell - Preliminary Data Sheet ASCELL3912
Austria Mikro Systeme International AG
1.2.6 Timing Diagrams The following Figure 3 shows the timing for the write operation into the configuration register. First the opcode is transmitted and it is followed by 9 instruction bits.
D_CLK DATA D_EN
t 0 1 LNA FB1 FB0 STR5 STR0
Figure 3:
Write timing for the configuration register..
The following Figure 4 shows the timing of a read operation from the status register. After writing the operation code to the ASCELL3912, the ASCELL3912 stays in high impedance state for one more clock cycle and starts transmission of the selected bit sequence after that period.
D_CLK
C SC3912 0 gap=1 DR RX RQ1 RQ0
DATA D_EN
1
t
Figure 4:
Read timing for status register.
In the following Figure 5 shows read out of the received data. In the example Bx-bz stands for bit z of Byte y, so B7-b5 depicts bit 5 of byte 7.
D_CLK
C SC3912 1 gap=1 B0-b0 B0-b1 B15-b6 B15-b7
DATA D_EN
1
t
Figure 5:
Read out timing for received data (16 Bytes).
1.2.7 Interrupt and Wake-Up Pins To provide the micro controller with time-critical information the receive/end transmission interrupt (RE_INT) line is used. Figure 2 shows the timing of the RE_INT and WAKE_UP signals during the reception. A high pulse is issued on this line, when one of the both conditions appear: * * The reception of data is completed for the first time after a receiver wake-up. The transmission of data has stopped. This interrupt is necessary status oriented CMT for comfort orientated central locking functions (like window closing).
Rev. A, February 2000
Page 8 of 14
ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell - Preliminary Data Sheet ASCELL3912
Austria Mikro Systeme International AG
To distinguish between the two interrupt sources, the WAKE_UP line is used, as listed in the following table.
RE_INT 01 01 Table 5: WAKE_UP Interrupt source 1 0 Message received completely Transmission stopped
Interrupt sources and their meaning.
2
Electrical Characteristics
Absolute Maximum Ratings (non operating)
Symbol VDD; AVDD GND; AGND Vin Iin ESD Tstg Tlead Parameter Positive supply voltage Negative supply voltage Voltage at every input pin Input current into any pin except supply pins Electrostatic discharge Storage temperature Lead temperature -55 Min -0.5 0 Gnd-0.5 -10 Max 6 0 VCC+0.5 10 1k 125 260 Units V V V mA V C C
2) 1) 3)
Note
1) Test according to MIL STD 883C, Method 3015.7: HBM: R=1.5 k, C=100 pF, 5 positive pulses per pin against supply pins, 5 negative pulses per pin against supply pins [C2]. 2) 260 C for 10 sec (Reflow and Wave Soldering), 360 C for 3 sec (Manual soldering). 3) All pins, pins XTAL+,XTAL-, RF+,RF-,LC+ and LC- have 500 V ESD protection
Operating Conditions
Symbol VDD=AVDD TA IPrun IPidle IPsleep Pin,max Parameter Positive supply voltage Operating temperature Supply current into VDDA and VDDD pin Average supply current in idle mode. Average supply current in sleep mode. Maximum input power level Above this level circuit could be destroyed 30 Everything on Conditions / Notes Min 2.7 0 -40 0 Typ Max 5.5 0 +85 10 1.2 0,5 Units V V C. mA mA A dBm
GND=AGND Negative supply voltage
Rev. A, February 2000
Page 9 of 14
ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell - Preliminary Data Sheet ASCELL3912
Austria Mikro Systeme International AG
2.3 Receiver Operation
TA = 23 C, VDD, AVDD = 3.6 V, unless specified otherwise. Devive functional for TA= -40 to +85 C.
Symbol FC Parameter Carrier Frequency Conditions / Notes Depends on different external crystals. Capacitive part t.b.d. 61 19,6875 13.5600 13.5672 50 50 25 18.235 -96 -100 4 7 10 Without external filter. Without external filter Without external filter 0 21 63 -28 Min Typ 315.000 433.920 868.300 200~ 400 69 Max Units MHz MHz MHz kHz MHz MHz MHz ppm ppm ppm kbps dBm dB dB dB dB dB dB dBm
Rin ?F Fxosc
Input impedance
Nominal FSK frequency devi a- 315, 433.92, 868.3MHz tion Crystal oscillator (XOSC) frequency Crystal oscillator (XOSC) frequency tolerance Gross Data Rate Receiver sensitivity 315,000 MHz: max +/- 50ppm 433.920 MHz: max +/- 50ppm 868.300 MHz: max +/-25ppm 315,000 MHz: (-40~+85 C), 433.920 MHz: (-40~+85 C), 868.300 MHz: (-40~+85 C). Including protocol. -10 CTFxosc
DR,gross RF
1) Sens
RFSensT
Temperature sensitivity reduc- -40TA>+85 C. @maximum receiver sensitivity reduction @ 44 kHz offset
RFSensFoffim Receiver sensitivity reduction caused by frequency offset RFSensLNA BI200KHz2) BI1MHz2) BI10MHz2) PLOfeed Sensitivity reduction caused by LNA gain switching Blocking immunity 200 kHz - 1 MHz Blocking immunity 1-10 MHz Blocking immunity @ >10 MHz LO @ FC power available at LC+ and LC- nodes
1) 2)
Standard Receive Quality (SRQ): Message reception successfully finished after <80 ms in 80% of all transmission trails. CW blocking signal relative to applied useful signal with -94dBm power level and SRQ. Measured without frequency offset and at +25 C
Receiver Timing
Symbol TDni TDwi Tstop Parameter Time to received FSK data Time to received FSK data RX switch off time Conditions / Notes Configured for fast response (receiver sleep time = 0) Using low idle duty cycle the (receiver sleep time >0) Timeout for comfort functions Min 27 40 30 Typ Max 80 92 Units ms ms ms
Rev. A, February 2000
Page 10 of 14
ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell - Preliminary Data Sheet ASCELL3912
Austria Mikro Systeme International AG
2.5 Digital Pin Characteristics
TAMB = 23 C, VDD = 3.6 V, unless specified otherwise. GND is the 0 V reference.
Symbol Parameter C_CLK (C clock output) VOH VOL tr td jcc VIH VIL IIH IIL FD_CLK VOH VOL High level output voltage Low level output voltage Rise time Fall time Cycle to cycle jitter High level input voltage Low level input voltage High level input current Low level input current D_CLK frequency High level output voltage Low level output voltage IOH = -1mA IOL = 1mA VIH= VDD VIL =0 V -1 3 VDD-0.5 0.3 VDD-0.5 0.3 1 IOH =-1 mA IOL =1 mA CLoad = 10 pF CLoad = 10 pF VDD-0.5 20 20 +/-5 0.3 V V ns ns % V V A A kHz V V Conditions Min Typ Max Units
DATA(serial data input), D_EN (serial data enable input), D_CLK (serial data clock input)
RE_INT (interrupt output); WAKEUP (C wakeup output)
3
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Pin-out Information
Name RF+ RFLC+ LCXTAL+ XTALAVDD AGND GMC RFGND DGND TEST1 TEST2 uC_CLK RE_INT WAKEUP Type I I I/O I/O I O P P I/O I P I/O I/O O O O Description LNA input LNA input LNA tank LNA tank XTAL oscillator input XTAL oscillator output Analog positive supply Analog negative supply Base-Band Low Pass frequency set RF GND Digital negative supply pin for test purposes pin for test purposes Clock output for micro controller Interrupt at first received data block and receive end Micro controller wake up; high during ongoing reception
Note: pin numbers have arbitrary ordering and numbering - will be defined during design
Rev. A, February 2000
Page 11 of 14
ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell - Preliminary Data Sheet ASCELL3912
Austria Mikro Systeme International AG
Pin 17 18 19 20
Name D_EN D_CLK DATA DVDD
Type O I I/O P
Description Enable data bus Clock for serial interface Data Input / Output for serial interface Digital positive supply
4
RF
Application Schematic
Optional DC to 100 kHz
f =868.300 MHz LC+ RF+
IRF
LC-
GMC
PRA
QDC
2*BBF
2*BBA
2*ACC
2*CMP
DEM
Data
Pre Filter RFPreamp. Quadrature Down Converter 0 90 Baseband Filters Baseband Amplifiers Switchable AC-Coupling
DC-0 Bandwidth LNA Clock
Protocol Decoder
Comperators Sync Demodulator, Synchronizer
D_EN D_CLK DATA
Implementation Example
RFGND
+/-45
RE_INT
Receiver Timing
AFC
WAKEUP C_CLK DVCC DVCC
RF_LO = f
RF
VCO
Local Oscillator
LPF
DIV PHD
f/64
Loop-filter AGND Divider Phase Detector XTAL+
XTO
XTAL Oscillator DGND XTALG. Schultes, ISM868_RX Revision: 0, 99 07 16
DGND TEST
AVDD AVDD
AGND
Figure 6: Basic application schematic of the ASCELL3912.
Rev. A, February 2000
Page 12 of 14
ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell - Preliminary Data Sheet ASCELL3912
Austria Mikro Systeme International AG
5
Package Information
Figure 7: Physical dimensions of TSSOP-20. Symbol Minimal (mm/mil) A A1 b D e E E1 L ? 6.25/0.246 4.30/0.169 0.50/0.020 0 0.65 BSC 6.40/0.252 4.40/0.173 0.60/0.024 4 6.50/0.256 4.50/0.177 0.70/0.028 8 0.05/0.002 0.19/0.0075 Common Dimensions Nominal (mm/mil) 0.10/0.004 Maximal (mm/mil) 1.10/0.0433 0.15/0.006 0.30/0.0118
ASCell's are functional and in-spec circuits, which are usually available as samples with documentation and demoboard. How ever they are intentionally to be used as a basis for ASIC derivatives. If an ASCell fits into a customer's application as it is, it will be immediately qualified and transfered to an ASSP to be ordered as a regular AS product. Copyright (c) 2000, Austria Mikro Systeme International AG, Schlo Premstatten, 8141 Unterpremstatten, Austria. Telefon +43-(0)3136-500-0, Telefax +43-(0)3136-52501, E-Mail info@amsint.com
Rev. A, February 2000
Page 13 of 14
ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell - Preliminary Data Sheet ASCELL3912
Austria Mikro Systeme International AG
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, without the prior permission in writing by the copyright holder. To the best of its knowledge, Austria Mikro Systeme International asserts that the information contained in this publication is accurate and correct.
Rev. A, February 2000
Page 14 of 14

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