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| Da t a S h e e t , V2 . 0 , D ec e m b e r 2 0 0 3 H Y E 1 8 P 3 2 1 6 0 A C ( - /L ) 9 . 6 H Y E 1 8 P 3 2 1 6 0 A C ( - /L ) 1 2 . 5 H Y E 1 8 P 3 2 1 6 0 A C ( - /L ) 1 5 3 2 M Sy n ch r o n o u s Bu r st C e ll u la r R AM C e ll u la r R AM M e m o r y P r o d u c ts Never stop thinking. Edition 2003-12-16 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. D a t a S he et , V 2. 0 , D e c e m b e r 2 0 0 3 H Y E 1 8 P 3 2 1 6 0 A C ( - /L ) 9 . 6 H Y E 1 8 P 3 2 1 6 0 A C ( - /L ) 1 2 . 5 H Y E 1 8 P 3 2 1 6 0 A C ( - /L ) 1 5 3 2 M Sy n ch r o n o u s Bu r st C e ll u la r R AM C e ll u la r R AM M e m o r y P r o d u c ts Never stop thinking. HYE18P32160AC(-/L)9.6, HYE18P32160AC(-/L)12.5, HYE18P32160AC(-/L)15 Revision History: Previous Version: Page all all 22 31-33 all all (synch) all (synch) all (synch) all (synch) all all 2003-12-16 1.8, 1.9 (Target data sheet) V2.0 Subjects (major changes since last revision) converted to new datasheet template Addition of part numbered 12.5 which is the combination of 70ns Asynch and 80MHz burst speed change of PASR range setting : remove 3/4, then add 1/8 remove WAIT timing and parameter definition from asynchronous read 2nd bin of Icc2 added. Marking for low-power part puts "L" in the place of "-" No negative (falling) edge of CLK configuration supported ADV hold time from CLK added for burst operation tACLK relaxed to 7ns for grade of 9.6 tHD relaxed to 1.5ns for grade of 9.6 tLZ, tBLZ, tOLZ are adjusted S/W Register Entry mode is officially supported and specified We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com Template: mp_a4_v2.0_2003-06-06.fm HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Table of Contents 1 1.1 1.2 1.3 1.4 1.5 1.6 1.6.1 1.6.2 1.6.3 2 2.1 2.2 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.5 2.6 2.6.1 2.6.2 2.6.3 2.7 2.7.1 2.7.2 2.7.3 2.8 2.8.1 2.8.2 2.9 3 3.1 3.2 3.3 3.4 4 5 5.1 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 HYE18P32160AC(-/L)9.6/12.5/15 Ball Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 HYE18P32160AC(-/L)9.6/12.5/15 Ball Definition and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Commands Supported in SRAM-Type Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Commands Supported in NOR-Flash-Type Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Commands Supported in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Up and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Access To The Control Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refresh Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Partial Array Self Refresh (PASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Deep Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Compensated Self Refresh (TCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Saving Potential in Standby When Applying PASR, TCSR or DPD . . . . . . . . . . . . . . . . . . . Page Mode Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latency Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Burst Configurations/Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WAIT Signal in Synchronous Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hold Data Out Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRAM-Type Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NOR-Flash-Type Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Write with Address Latch (ADV) Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Read Mode Including Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Power & DC Operation Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 18 19 21 22 23 23 23 24 25 27 28 29 29 29 31 31 32 34 37 37 38 40 43 43 43 46 47 47 47 48 48 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Appendix A: Low-Frequency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Asynchronous Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Appendix B: S/W Register Entry Mode ("4-cycle method") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Data Sheet 5 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 CellularRAM - Interface Configuration Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Standard Ballout - HYE18P32160AC(-/L)9.6/12.5/15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 The two Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Control Register Write in SRAM-Type Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Control Register Write in NOR-Flash-Type Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Control Register Write in Synchronous Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PASR Programming Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PASR Configuration Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Latency Mode - Functional Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Data Out Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Asynchronous Read - Address Controlled (CS = OE = VIL, WE = VIH, UB and/or LB = VIL, CRE = VIL, ADV = VIL) 31 Asynchronous Read (WE = VIH, CRE = VIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Asynchronous Page Read Mode (CRE = VIL, ADV = VIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Asynchronous Write - WE Controlled (OE = VIH or VIL, CRE = VIL) . . . . . . . . . . . . . . . . . . . . . . . . 34 Asynchronous Write - CS Controlled (OE = VIH or VIL, CRE = VIL). . . . . . . . . . . . . . . . . . . . . . . . . 34 Asynchronous Write - UB, LB Controlled (OE = VIH or VIL, CRE = VIL) . . . . . . . . . . . . . . . . . . . . . 35 Asynchronous Write to Control Register (OE = VIH or VIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Synchronous Read Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Asynchronous Write with Address Latch (ADV) Control (followed by single-burst read) . . . . . . . . 40 Asynchronous Write with Address Latch (ADV) Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Asynchronous Write To Control Register in NOR-Flash Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Synchronous Write Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Synchronous Write to Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Synchronous Write Burst Followed by Synchronous Read Burst. . . . . . . . . . . . . . . . . . . . . . . . . . 45 Synchronous Read Burst Followed by Synchronous Write Burst. . . . . . . . . . . . . . . . . . . . . . . . . . 45 Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 P-VFBGA-54 (Plastic Very Thin Fine Pitch Ball Grid Array Package) . . . . . . . . . . . . . . . . . . . . . . 49 Low-Frequency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 S/W Register Entry timing (Address input = 1FFFFFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 RCR Mapping in S/W Register Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 BCR Mapping in S/W Register Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Data Sheet 6 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 22 Table 21 Product Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ball Description - HYE18P32160AC(-/L)9.6/12.5/15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Command Table (SRAM-Type Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of Commands (SRAM-Type Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Command Table (NOR-Flash-Type Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Command Table (NOR-Flash-Type Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of Commands in NOR-Flash Type Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Command Table (Full Synchronous Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of Commands in Synchronous Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standby Currents When Applying PASR, TCSR or DPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latency Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Parameters - Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Parameters - Asynchronous Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Parameters - Synchronous Read Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Parameters - Asynchronous Write With ADV Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Parameters - Synchronous Read/Write Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 11 13 13 14 14 15 16 16 23 27 28 33 36 39 41 46 47 47 47 48 48 Data Sheet 7 V2.0, 2003-12-16 32M Synchronous Burst CellularRAM CellularRAM HYE18P32160AC(-/L)9.6 HYE18P32160AC(-/L)12.5 HYE18P32160AC(-/L)15 1 1.1 * * * * * * * Overview Features * * * * * * * High density (1T1C-cell) Synchronous 32-Mbit Pseudo-Static RAM Designed for cell phone applications (CellularRAM) Functional-compatible (Asynchronous mode) to conventional low power asynchronous SRAM devices Organization 2M x 16 Refresh-free operation 1.8 V single power supply (VDD and VDDQ) Low power optimized design - ISTANDBY = 90 A (for L-part 1)) or 120uA (for standard part), data retention mode - IDPD = < 25 A (32M), non-data retention mode Low power features (partly adopted from the JEDEC standardized low power SDRAM specifications) - Temperature Compensated Self-Refresh (TCSR) - Partial Array Self-Refresh (PASR) - Deep Power Down Mode (DPD) User configurable interface supporting three different access protocols (values from 9.6 part) - asynchronous SRAM protocol, 70 ns random access cycle time, 20 ns page mode (read only) cycle time - NOR-Flash burst protocol, 70 ns write cycle time, 104 MHz burst mode read cycle - synchronous (bi-directional) interface protocol, 70 ns random cycle time, 104 MHz burst mode read/write cycle In NOR-Flash burst or in synchronous mode the additional user settings are featured - programmable fixed burst length of 4/8/16 words or continuous burst mode - programmable latency modes to adjust the desired burst frequency - wrap mode function - programmable WAIT signal polarity and timing Byte read/write control by UB/LB (Asynchronous mode and in synchronous burst read) Synchronous Data Input Mask function supported by UB/LB in synchronous burst write mode Wireless operating temperature range from -25 C to +85 C P-VFBGA-54 chip-scale package (9 x 6 ball grid) Table 1 Product Selection L9.61) 66 104 70 ns 90A 120A 90A -9.6 L12.51) 50 80 70 ns 120A 90A -12.5 L151) 40 66 85 ns 120A -15 HYE18P32160AC Maximum Input CLK frequency Lat = 2 (MHz) Lat = 3 Min. Random Cycle time (tRC) Stand-by current (ICC2) 1) Contact Factory HYE Extended Temp. part 18 P 3216 32M (x16 Org) 0 A C Chip Scale Package Design Revision number Device Type 0: standard (54-ball) VDD = 1.8 V typ. PSRAM product Data Sheet 8 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Overview 1.2 General Description The 32M Synchronous Burst CellularRAM (CellularRAM) is designed to meet the growing memory density and bandwidth demand in 3G cellular phone designs. Its high density 1T1C-cell concept, the multi-protocol interface capabilities, its highly optimized low power design and its refresh-free operation make the CellularRAM the perfect fit for 3G baseband applications. Configured in synchronous burst mode, a peak bandwidth of > 200 Mbyte/s is achieved at the max. clock rate of 104 MHz. The burst length can be programmed and set to either fixed burst lengths of 4, 8- or 16-words1) or set to continuous mode. The 16-word burst mode is specially designed for cached processor designs to speed up cache re-fill operations. In NOR-Flash, burst mode read accesses are synchronous whereas write accesses are of asynchronous nature. This is to retain compatibility to today's NOR-Flash protocols and thus to make sure that existing baseband designs do get instantly a performance gain in read direction by deploying the NOR-Flash burst protocol. The different access protocols that are supported by the CellularRAM are illustrated in Figure 1. Data byte control (UB, LB) is featured in all modes and provides dedicated lower and upper byte access. Protocols: Read: Write: Async/ Page Async /CS /WE /OE Sync. Burst Async w/ ADR Latch /CS /WE /OE CLK /ADV WAIT Sync Burst Sync Burst /CS /WE /OE CLK /ADV WAIT SRAM I/F NOR-Flash I/F Sync. I/F 32Mb CellularRAM (FBGA-54) 32Mb CellularRAM (FBGA-54) 32Mb CellularRAM (FBGA-54) Pinning: CLK /ADV /CS /WE /OE /UB /LB CRE A20-A0 /CS /WE /OE /UB /LB CRE A20-A0 32Mb CellularRAM (FBGA-54) DQ15-DQ0 32Mb CellularRAM (FBGA-54) DQ15-DQ0 WAIT Asynchronous I/F CLK=/ADV=Low and WAIT ignored in Asynchronous I/F Sync. Burst I/F & NOR-Flash Burst & Asynchronous I/F Figure 1 CellularRAM - Interface Configuration Options The CellularRAM can be operated from a single 1.8 V power supply feeding the core and the output drivers. The chip is fabricated in Infineon Technologies advanced low power 0.14 m process technology and comes in a P-VFBGA-54 package. 1) 1 word is equal 16 bits Data Sheet 9 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Overview 1.3 HYE18P32160AC(-/L)9.6/12.5/15 Ball Configuration 1 A B C D E F G H J LB# DQ8 DQ9 VSSQ VDDQ 2 OE# UB# DQ10 DQ11 DQ12 3 A0 A3 A5 A17 NC (A21) 4 A1 A4 A6 A7 A16 A15 A13 A10 NC (A22) 5 A2 CS# DQ1 DQ3 DQ4 DQ5 WE# A11 NC 6 CRE DQ0 DQ2 VDD VSS DQ6 DQ7 A20 NC DQ14 DQ13 DQ15 A18 WAIT A14 A12 A9 ADV# A19 A8 CLK Figure 2 Standard Ballout - HYE18P32160AC(-/L)9.6/12.5/15 Note: Figure 2 shows top view Data Sheet 10 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Overview 1.4 Table 2 Ball CLK HYE18P32160AC(-/L)9.6/12.5/15 Ball Definition and Description Ball Description - HYE18P32160AC(-/L)9.6/12.5/15 Type Input Detailed Function Clock Signal In synchronous burst mode, address and command inputs and data are referenced to CLK. In asynchronous SRAM-type mode the clock signal is ignored. During write accesses in NOR-Flash operation mode the CLK signal must be clamped to low. Control Register Enable CRE set to high enables the access to the control register map. By applying the SET CONTROL REGISTER (SCR) command (see Table 3) the address bus is loaded into the selected control register. Address Valid ADV signals in NOR-Flash and full synchronous mode that a valid address is present on the address bus. In NOR-Flash read mode and full synchronous mode the address is latched on the programmed clock edge while ADV is held low. In NOR-Flash write mode ADV can be used to latch the address, but can be held low as well. In asynchronous SRAM-type mode ADV needs to be active, it may be tied to active. Chip Select CS enables the command decoder when low and disables it when high. When the command decoder is disabled new commands are ignored, addresses are don't care and outputs are forced to high-Z. Internal operations, however, continue. For the details please refer to the command tables in Chapter 1.6. Output Enable OE controls DQ output driver. OE low drives DQ, OE high sets DQ to high-Z. Write Enable WE set to low while CS is low initiates a write command. Upper/Lower Byte Enable UB enables the upper byte DQ15-8 (resp. LB DQ7 ... 0) during read/write operations. UB (LB) deassertion prevents the upper (lower) byte from being driven during read or being written. Wait State Signal In synchronous mode, WAIT signal indicates the host system when the output data is valid during read and when the input data should be asserted during write operation. In asynchronous mode, the signal has to be ignored. Address Inputs During a Control Register Set operation by CRE access, the address inputs define the register settings. Data Input/Output The DQ signals 0 to 15 form the 16-bit data bus. Power Supply, Core Power and Ground for the internal logic. Power Supply, I/O Buffer Isolated Power and Ground for the output buffers to provide improved noise immunity. No Connect Please do not connect. Reserved for future use, i.e. E3: A21, J4: A22, see ballout in Figure 2 on Page 10. CRE Input ADV Input CS Input OE WE UB, LB Input Input Input WAIT Output 3-state A <20:0> Input DQ <15:0> 1 x VDD 1 x VSS 1 x VDDQ 1 x VSSQ 4 x NC I/O Power Supply Power Supply - Data Sheet 11 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Overview 1.5 Functional Block Diagram Address Decode A20-A0 1T1C-Cell Memory Array (2M x16) CLK ADV WAIT CRE CS WE OE UB LB Control Logic Async/ Page I/F NOR-Flash Burst I/F Sync. Burst I/F MUX DQ7-DQ0 DQ15-DQ8 additional pins necessary to operate the device in NOR-Flash and Synchronous mode Figure 3 Functional Block Diagram Data Sheet 12 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Overview 1.6 Commands The supported command set depends on the selected operation mode. By default the CellularRAM device is reset to the asynchronous SRAM-type mode after power-up. To put the device in a different operation mode the Bus Configuration Register must be programmed first accordingly. The valid control input states and sequences are listed below for the different operation modes. Other control signal combinations are not supported. 1.6.1 Commands Supported in SRAM-Type Mode In the SRAM-type operation mode all commands are of asynchronous nature. Table 3 lists the asynchronous commands supported in SRAM-type mode. CLK has to be held low for entire asynchronous mode operation. Table 3 Asynchronous Command Table (SRAM-Type Mode) Power Mode Active Active Active Standby~Active3) Standby Deep Power Down CS L L L L H H ADV WE L L L X X X H L L H X X OE L X 2) 2) Operation Mode READ WRITE SET CONTROL REGISTER NO OPERATION DESELECT DPD4) UB/ LB L1) L 1) CRE A19 L L H L X X V V L H X X X A20 - A0 ADR ADR RCR DIN BCR DIN X X X DQ15:0 DOUT DIN X High-Z High-Z High-Z X X X X X H X X 1) Table 3 reflects the behaviour if UB and LB are asserted to low. If only either of the signals, UB or LB, is asserted to low only the corresponding data byte will be output or written (UB enables DQ15 - DQ8, LB enables DQ7 - DQ0). 2) During a write access invoked by WE set to low the OE signal is ignored. 3) Stand-by power mode applies only to the case when CS goes low from DESELECT while no address change occurs. Toggling address results in active power mode. Also, NO OPERATION from any active power mode by keeping CS low consumes the power higher than stand-by mode. 4) Deep power down is maintained until control register is re-programmed to disable DPD control bit (RCR Bit 4). Note: `L' represents a low voltage level, `H' a high voltage level, `X' represents "Don't Care", `V' represents "Valid". Table 4 Mode READ Description of Commands (SRAM-Type Mode) Description The READ command is used to perform an asynchronous read cycle. The signals, UB and LB, define whether only the lower, the upper or the whole 16-bit word is output. The WRITE command is used to perform an asynchronous write cycle. The data is latched on the rising edge of either CS, WE, UB, LB, whichever comes first. The signals, UB and LB, define whether only the lower, the upper or the whole 16-bit word is latched into the CellularRAM. The control registers are loaded via the address inputs A19, A15 - A0 performing an asynchronous write access. Please refer to the control register description for details. The SCR command can only be issued when the CellularRAM is in idle state. The NOP command is used to perform a no operation to the CellularRAM, which is selected (CS = 0). Operations already in progress are not affected. Power consumption of this command mode varies by address change and initiating condition. WRITE SET CONTROL REGISTER NO OPERATION Data Sheet 13 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Overview Table 4 Mode DESELECT Description of Commands (SRAM-Type Mode) (cont'd) Description The DESELECT function prevents new commands from being executed by the CellularRAM. The CellularRAM is effectively deselected. I/O signals are put to high impedance state. DPD stops all refresh-related activities and entire on-chip circuit operation. Current consumption drops below 25 A. Wake-up from DPD also requires 150 s to get ready for normal operation. DPD 1.6.2 Commands Supported in NOR-Flash-Type Mode In NOR-Flash-type mode read commands are performed on a synchronous base whereas write commands are performed in an asynchronous way. In synchronous read mode all operations are defined by the states of the control signals CS, ADV, OE, WE and UB, LB at the positive (default) edge of the data clock. To put the device in NOR-Flash-type mode the Bus Configuration Register must be programmed first accordingly. Table 5 lists the truth table for the supported asynchronous write commands, while Table 5 lists the supported synchronous read commands. Table 5 Asynchronous Command Table (NOR-Flash-Type Mode) Power Mode Active Active Standby~Active3) Standby Deep Power Down CS L L L H H ADV WE L L H X X L L H X X OE X1) X 1) Operation Mode WRITE SET CONTROL REGISTER NO OPERATION DESELECT DPD 4) UB/ LB L2) X X X X CRE A19 L H L L X V L H X X X A20 - A0 ADR RCR DIN BCR DIN X X X DQ15:0 DIN X High-Z High-Z High-Z H X X 1) During a write access invoked by WE set to low the OE signal is ignored. 2) Table 5 reflects the behaviour if UB and LB are asserted to low. If only either of the signals, UB or LB, is asserted to low only the corresponding data byte will be output or written (UB enables DQ15 - DQ8, LB enables DQ7 - DQ0). 3) Stand-by power mode applies only to the case when CS goes low from DESELECT while no address change occurs. NO OPERATION from any active power mode by keeping CS low consumes the power higher than stand-by mode. 4) Deep power down is maintained until control register is re-programmed to disable the bit for deep power down (RCR Bit 4). Note: `L' represents a low voltage level, `H' a high voltage level, `X' represents "Don't Care", `V' represents "Valid". Table 6 Synchronous Command Table (NOR-Flash-Type Mode) Power Mode Active Active Standby~Active4) Standby Deep Power Down CLK L->H L->H L->H L->H L CS L L L H H ADV WE L H H X X H H H X X UB/ LB 1) X L 2) Operation Mode BURST INIT BURST READ NO OPERATION DESELECT DPD 6) CRE A20 - A0 L L L X X ADR X X X X DQ15:0 X DOUT3) High-Z5) High-Z High-Z X X X 1) OE does the same function to all DQ pins with UB and LB during read operation. 2) Table 6 reflects the behaviour if UB and LB are asserted to low. If only either of the signals, UB or LB, is asserted to low only the corresponding data byte will be output or written (UB enables DQ15 - DQ8, LB enables DQ7 - DQ0). If both signals are disabled the device is put in deselect mode. Data Sheet 14 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Overview 3) Output driver controlled by the asynchronous OE signal 4) Stand-by power mode applies only to the case when CS goes low from DESELECT while no address change occurs. NO OPERATION from any active power mode by keeping CS low consumes the power higher than stand-by mode. 5) The asynchronous OE control signal has to be asserted to `H'. 6) Deep power down is maintained until control register is re-programmed to disable the bit for deep power down (RCR Bit 4). Note: `L' represents a low voltage level, `H' a high voltage level, `X' represents "Don't Care", `V' represents "Valid". Table 7 Mode WRITE Description of Commands in NOR-Flash Type Mode Description The WRITE command is used to perform an asynchronous write cycle. While the address is latched by the rising edge of ADV, the data is latched by the rising edge of either CS, WE, UB, LB, whichever comes first. The signals, UB and LB, define whether only the lower, the upper or the whole 16-bit word is latched into the CellularRAM. The BURST INIT command is used to initiate a synchronous burst read access and to latch the burst start address. The burst length is determined by the bit2 bit0 in the Bus Configuration Register. The BURST READ command is used to perform a synchronous burst read access. The first data is output after the number of clock cycles as defined by the programmed latency mode. The control registers are loaded via the address inputs A19, A15 - A0 performing an asynchronous NOR-Flash type write access. Please refer to the control register description for details. The SCR command can only be issued when the CellularRAM is in idle state and no bursts are in progress. The NOP command is used to perform a no operation to the CellularRAM, which is selected (CS = 0). Operations already in progress are not affected. The DESELECT function prevents new commands from being executed by the CellularRAM. The CellularRAM is effectively deselected. I/O signals are put to high impedance state. DPD stops all refresh-related activities and entire on-chip circuit operation. Current consumption drops below 25 A. Wake-up from DPD also requires 150 s to get ready for normal operation. BURST INIT BURST READ SET CONTROL REGISTER NO OPERATION DESELECT DPD Data Sheet 15 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Overview 1.6.3 Commands Supported in Synchronous Mode In bi-directional synchronous mode read and write operations are performed on a complete synchronous base. To put the device in full synchronous mode the Bus Configuration Register must be programmed first accordingly. Table 8 shows the truth table for the supported synchronous read/write commands. Table 8 Synchronous Command Table (Full Synchronous Mode) Power Mode Active Active Active Active Active Standby~Active4) Standby CLK L->H L->H L->H L->H L->H L->H L->H CS L L L L L L H H ADV WE L H L H L H X X H X L X L H X X UB/ CRE A19 LB 1) X L2) X L2) X X X X L X L X H L X X V X V X L H X X X A20 - A0 ADR X ADR X RCR DIN BCR DIN X X X DQ15:0 X DOUT3) X DIN X High-Z5) High-Z High-Z Operation Mode BURST INIT READ BURST READ BURST INIT WRITE BURST WRITE SET CONTROL REGISTER NO OPERATION DESELECT DPD6) Deep Power Down L 1) OE does the same function to all DQ pins with UB and LB during read operation. 2) Table 8 reflects the behaviour if UB and LB are asserted to low. If only either of the signals, UB or LB, is asserted to low only the corresponding data byte will be output or written (UB enables DQ15 - DQ8, LB enables DQ7 - DQ0). If both signals are disabled the device is put in deselect mode. 3) Output driver controlled by the asynchronous OE control signal 4) Stand-by power mode applies only to the case when CS goes low from DESELECT while no address change occurs. NO OPERATION from any active power mode by keeping CS low consumes the power higher than stand-by mode. 5) The asynchronous OE control signal has to be asserted to `H'. 6) Deep power down is maintained until control register is re-programmed to disable the bit for deep power down (RCR Bit 4). Note: `L' represents a low voltage level, `H' a high voltage level, `X' represents "Don't Care", `V' represents "Valid". Table 9 Mode BURST INIT Description of Commands in Synchronous Mode Description The BURST INIT command is used to initiate a synchronous burst access and to latch the burst start address. The burst length is determined by the setting in the Bus Configuration Register. The BURST READ command is used to perform a synchronous burst read access. The first data is output after the number of clock cycles as defined by the programmed latency mode. The BURST WRITE command is used to perform a synchronous burst write access. The point of time when the first data is written is indicated by the WAIT signal. It varies with the selected clock frequency and the occurrence of a refresh cycle. The control registers are loaded via the address inputs A19, A15 - A0 performing a single word burst. Please refer to the control register description for details. The SCR command can only be issued when the CellularRAM is in idle state and no bursts are in progress. The NOP command is used to perform a no operation to the CellularRAM, which is selected (CS = 0). Operations already in progress are not affected. 16 V2.0, 2003-12-16 BURST READ BURST WRITE SET CONTROL REGISTER NO OPERATION Data Sheet HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Overview Table 9 Mode DESELECT Description of Commands in Synchronous Mode (cont'd) Description The DESELECT function prevents new commands from being executed by the CellularRAM. The CellularRAM is effectively deselected. I/O signals are put to high impedance state. DPD stops all refresh-related activities and entire on-chip circuit operation. Current consumption drops below 25 A. Wake-up from DPD also requires 150 s to get ready for normal operation. DPD Data Sheet 17 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description 2 2.1 Functional Description Power-Up and Initialization The power-up and initialization sequence guarantees that the device is preconditioned to the user's specific needs. Like conventional DRAMs, the CellularRAM must be powered up and initialized in a predefined manner. VDD and VDDQ must be applied at the same time to the specified voltage while the input signals are held in "DESELECT" state (CS = High). After power on, an initial pause of 150 s is required prior to the control register access or normal operation. Failure to follow these steps may lead to unpredictable start-up modes. Please note the default operation mode after power up is the asynchronous SRAM I/F mode (see Chapter 2.4). VDD, VDDQ VDD,VDDQ,min t PU =150s ready for normal operation Figure 4 Power Up Sequence Data Sheet 18 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description 2.2 Access To The Control Register Map Write-only access to the control register map is enabled by applying the SCR command asserting the CRE-pin to high. In combination with CRE set to high, Pin A19 designates the operation to one of either control registers. Pin A19 set to low selects the Refresh Control Register (RCR), Pin A19 set to high addresses the Bus Configuration Register (BCR). Write and read access to the control registers is also available at S/W entry method. For details, please refer to "Appendix B: S/W Register Entry Mode ("4-cycle method")" on Page 51. Bus Control Register BCR A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 1 0 0 0 OM 0 Latency Mode WP 0 WC 0 1 IMP 0 BW Burst Length Refresh Control Register RCR A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 PM TCSR DPD 0 PASR A19 is the selection address between BCR and RCR All '0' are reserved bits and must be set to zero. (BCR.A6 has to be set to one) Figure 5 The two Control Registers A20-A0 OPCODE Latch OPCODE on Address A19 Address BCR 0(RCR), 1(BCR) (Latch Opcode) ADV CS UB, LB Write Opcode WE Initiate Control Register Access CRE DQx Don't Care Figure 6 Control Register Write in SRAM-Type Mode Data Sheet 19 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description Open Address Bus Latch A20-A0 OPCODE ADDRESS Select Control Register Close Address Bus Latch A19 0(RCR), 1(BCR) CRE ADV CS Initiate Control Register Access Wri te la tc he d OPCODE to selected Control Register WE UB, LB DQ15-DQ0 Don't Care Figure 7 Control Register Write in NOR-Flash-Type Mode CLK Latch Control Register Value A20-A0 OPCODE Latch Control Register Address A19 0(RCR),1(BCR) CRE Initiate Control Register Access ADV CS OE WE UB, LB WAIT DQ15-DQ0 Don't Care Figure 8 Data Sheet Control Register Write in Synchronous Mode 20 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description 2.3 Refresh Control Register The Refresh Control Register (RCR) allows to save stand-by power additionally by making use of the Temperature-Compensated Self Refresh (TCSR), Partial-Array Self Refresh (PASR) and Deep Power Down (DPD) features. The Refresh Control Register is programmed via the Control Register Set command (with CRE = 1 and A19 = 0) and retains the stored information until it is reprogrammed or the device loses power. Please note that the RCR contents can only be set or changed when the CellularRAM is in idle state. RCR Refresh Control Register A20 0 A19 RS A18 A17 A16 A15 (CRE, A19 = 10B) A14 A13 A12 A11 A10 0 A9 A8 A7 PM A6 A5 A4 DPD A3 0 A2 A1 PASR A0 TCSR Field RS PM Bits 19 7 Type1) Description w w Register Select 0 set to 0 to select this RCR (= 1 to select BCR). Page Mode Enable/Disable In asynchronous operation mode the user has the option to toggle A0 - A3 in a random way at higher rate (20 ns vs. 70 ns) to lower access times of subsequent reads with 16-word boundary. In synchronous mode this option has no effect. The max. page length is 16 words. Please note that as soon as page mode is enabled the CS low time restriction applies. This means that the CS signal must not be kept low longer than tCSL = 10 s. Please refer to Figure 15. 0 page mode disabled (default) 1 page mode enabled Temperature Compensated Self Refresh The 2-bit wide TCSR field features four different temperature ranges to adjust the refresh period to the actual case temperature. Since DRAM technology requires higher refresh rates at higher temperature this is a second method to lower power consumption in case of low or medium temperatures. 11 +85 C (default) 00 +70 C 01 +45 C 10 +15 C Deep Power Down Enable/Disable The DPD control bit puts the CellularRAM device in an extreme low power mode cutting current consumption to less than 25 A. Stored memory data is not retained in this mode. Though the settings of both control registers RCR and BCR are also stored during DPD. 0 DPD enabled 1 DPD disabled (default) TCSR [6:5] w DPD 4 w Data Sheet 21 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description Type1) Description w Partial Array Self Refresh The 3-bit PASR field is used to specify the active memory array. The active memory array will be kept periodically refreshed whereas the disabled parts will be excluded from refresh and previously stored data will get lost. The normal operation still can be executed in disabled array, but stored data is not guaranteed. This way the customer can dynamically adapt the memory capacity in steps of 8 Mbit (4Mbit at lowest) to one's need without paying a power penalty. Please refer to Figure 9. 000 entire memory array (default) 001 lower 1/2 of the memory array (16 Mb) 010 lower 1/4 of the memory array (8 Mb) 011 lower 1/8 of the memory array (4 Mb) 100 zero 101 upper 1/2 of the memory array (16 Mb) 110 upper 1/4 of the memory array (8 Mb) 111 upper 1/8 of the memory array (4 Mb) Reserved must be set to `0' Field PASR Bits [2:0] Res 20, [18:8], 3 w 1) w: write-only access 2.3.1 Partial Array Self Refresh (PASR) By applying PASR the user can dynamically customize the memory capacity to one's actual needs in normal operation mode and standby mode. With the activation of PASR there is no longer a power penalty paid for the larger CellularRAM memory capacity in case only e.g. 8 Mbits are used by the host system. Bit2 down to bit0 specify the active memory array and its location (starting from bottom or top). The memory parts not used are powered down immediately after the mode register has been programmed. Advice for the proper register setting including the address ranges is given in Figure 9. PASR.Bit2,1,0 16M 8M 4M 0M 1FFFFFh 1FFFFFh 101 110 111 100 8M 180000h 17FFFFh 8M 100000h 0FFFFFh 8M 080000h 07FFFFh 000 000000h 32M 8M 000000h 011 4M 010 8M 001 16M PASR.Bit2,1,0 Figure 9 PASR Programming Scheme PASR is effective in normal operation and standby mode as soon as it has been configured by register programming. Default setting is the entire memory array. Figure 10 shows an exemplary PASR configuration where it is assumed that the application uses max. 8 Mbit out of 32 Mbit. Data Sheet 22 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description 32Mb CellularRAM 24Mb Deactivated Active Memory Array defined by PASR to 8Mb RCR.Bit 2,1,0= 010 07FFFFh 000000h 8M Activated Figure 10 PASR Configuration Example 2.3.2 Deep Power Down Mode To put the device in deep power down mode the DPD control bit must be asserted to low. Once set into this extreme low power mode current consumption is cut down to less than 25 A. All internal voltage generators inside the CellularRAM are switched off and the internal self-refresh is stopped. This means that all stored memory information will be lost by entering DPD. Only the register values of BCR and RCR are kept valid during DPD. To leave the Deep Power Down mode again the Refresh Configuration Register has to be accessed and the DPD bit has to be programmed to high level voltage. A guard time of at least 150 s has to be met where no commands beside a NOP must be applied to re-enter again standby or idle mode. 2.3.3 Temperature Compensated Self Refresh (TCSR) The 2-bit wide TCSR field features four different temperature ranges to adjust the refresh period to the actual case temperature. DRAM technology requires higher refresh rates at higher temperature. At low temperature the refresh rate can be reduced, which reduces as well the standby current of the chip. This feature can be used in addition to PAR to lower power consumption in case of low or medium temperatures. Please refer to Table 10. 2.3.4 Power Saving Potential in Standby When Applying PASR, TCSR or DPD Table 10 demonstrates the currents in standby mode when PASR, TCSR or DPD is applied. Table 10 Operation Mode NO OPERATION/ DESELECT Standby Currents When Applying PASR, TCSR or DPD Power Mode STANDBY PASR TCSR PASR Bit Controlled RCR.Bit6-5 RCR.Bit2-0 Wake-Up Active Phase Array - - - Full 1/2 1/4 1/8 0 0 85 90(120) 80(105) 70(90) 60(75) 50(60) Standby [A] 70 75(100) 68(90) 62(80) 55(70) 50(60) 45 60(80) 56(75) 53(70) 52(65) 50(60) 15 50(60) 50(60) 50(60) 50(60) 50(60) DPD DEEP POWER DPD DOWN RCR.Bit4 ~150 s 25.0 Data Sheet 23 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description 2.3.5 Page Mode Enable/Disable In asynchronous operation mode, the user has the option to enable page mode to toggle A0 - A3 in random way at higher cycle rate (20 ns vs. 70 ns) to lower access times of subsequent reads within 16-word boundary. Write operation is not supported in the manner of page mode access. In synchronous mode, this option has no effect. The max. page length is 16 words, so which A0 - A3 is regarded as page-mode address. If the access needs to cross the boundary of 16-word (any difference in A20 - A4), then it should start over new random access cycle, which is the same as asynchronous read operation. Please note that as soon as page mode is enabled the CS low time restriction applies. This means that the CS signal must not kept low longer than tCSL = 10 s. Please refer to Figure 15. Refresh Control Register (RCR) A20 A19 A18 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 0 0 0 0 PM TCSR DPD 0 PASR Control Register Control Register Select A19 0 1 control reg RCR BCR Page Mode Bit A7 0 1 page mode disabled (def.) enabled Deep Power Down Mode A4 0 1 power down enabled disabled (def.) Partial Array Self Refresh A2 0 0 0 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 refreshed memory area entire memory array (def.) lower 1/2 of memory array lower 1/4 of memory array lower 1/8 of memory array zero upper 1/2 of memory array upper 1/4 of memory array upper 1/8 of memory array Temperature-Compensated Self-Refresh A20, A18....A8, A3: reserved, must be set to '0'. A6 1 0 0 1 A5 1 0 1 0 max. case temp. +85C (def.) +70C +45C +15C 0 1 1 1 1 Data Sheet 24 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description 2.4 Bus Control Register The Bus Control Register (BCR) specifies the interface configurations. For the various configuration options please refer to the register description below. The Bus Control Register is programmed via the Control Register Set command (with CRE = 1 and A19 = 1) and retains the stored information until it is reprogrammed or the device loses power. Please note that the BCR contents can only be set or changed when the CellularRAM is in idle state. Note: Bit 9 must be set to "0" and bit 6 to "1" for proper operation. BCR Bus Control Register A20 0 A19 1 A18 A17 A16 0 A15 OM (CRE, A19 = 11B) A14 A13 A12 A11 A10 0 Latency Mode WP A9 0 A8 WC A7 0 A6 1 A5 IMP A4 0 A3 BW A2 A1 A0 Burst Length Field RS OPMODE Bits 19 15 Type1) Description w w Register Select 1 set to 1 to select this BCR (= 0 to select RCR). Operation Mode The CellularRAM supports three different interface access protocols, * the SRAM-type protocol with asynchronous read and write accesses * the NOR-FLASH-type protocol with synchronous read and asynchronous write accesses * the FULL SYNCHRONOUS mode with synchronous read and synchronous write accesses Operating the device in synchronous mode maximizes bandwidth. The NOR-Flash type mode is the recommended mode for legacy baseband systems which are not able to run the synchronous write protocol. The OPMODE bit defines whether the device is operating in synchronous (fully or partially) mode or asynchronous mode. 0 NOR-FLASH-type mode read: synchronous burst mode write: asynchronous access mode 0 FULL SYNCHRONOUS mode read: synchronous burst mode write: synchronous burst mode The mode of write operation, NOR-FLASH or FULL SYNCHRONOUS, is adaptively detected: This is done by detecting a rising clock edge during ADV valid. If a rising clock edge occurs within ADV valid, FULL SYNCHRONOUS write is detected. If there is no rising clock edge then NOR FLASH write is detected. Please refer to Figure 22 on Page 40 for asynchronous write and to Figure 25 on Page 43 for synchronous write. 1 SRAM-type mode (default) read: asynchronous access mode write: asynchronous access mode Latency Mode The latency mode has to be adjusted to the desired burst frequency. Depending on the programmed latency, driving 1st data output is delayed by the number of clock cycles as specified in this field counting from the address valid strobe signal, ADV. 010 latency code 2, max 66 MHz burst clock frequency 011 latency code 3 (default), max 104 MHz burst clock frequency Note: All others reserved. LAT [13:11} w Data Sheet 25 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description Type1) Description w WAIT Polarity The WAIT polarity control bit allows the user to define the polarity of the WAIT output signal. The WAIT output line is used during a synchronous read burst to signal when the output data is invalid. 0 active low 1 active high (default) WAIT Configuration The WAIT signal configuration control bit specifies whether the WAIT signal is asserted at the time of the delay or whether it is asserted one clock cycle in advance. 0 WAIT is asserted during the delay 1 WAIT is asserted one data cycle before the delay (default) Output Impedance For adaptation to different system characteristics the output impedance can be configured. 0 Full drive for 50 systems (default) 1 Quarter drive Burst Wrap The burst wrap control bit defines whether there is a wrap around within a burst access or not. In case of fixed 8-word burst length, this means that after word7, word0 is going to be output in wrap mode. In case of continuous burst mode the internal address counter will wrap from the last address, 1FFFFFH to 000000H regardless of the setting. Please note this setting is only used for burst read mode, since burst write mode is always continuous. 0 wrap 1 no wrap (default) Burst Length (Burst Read only) Via the burst length field the user can select between fixed burst lengths of 4, 8, and 16 and any arbitrary burst length by choosing the continuous mode option. In continuous mode the burst length is controlled by the active low period of the read control lines CS and OE. Please note this setting is only used for burst read mode. Burst write mode is always continuous independent of this register setting. 001 4-word burst 010 8-word burst 011 16-word burst 111 continuous (default) Reserved must be set to `0' Field WP Bits 10 WC 8 w IMP 5 w BW 3 w BL [2:0] w Res 20, w [18:16], 14, 9, 7, 4 1) w: write-only access Data Sheet 26 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description 2.4.1 Latency Modes The latency mode defines the number of clock cycles which pass before the first output data is valid within a read burst access (counting from the clock edge where ADV was detected low). The number of inserted wait cycles increases along with the input clock frequency. Please refer to Table 11 for the proper setting. Please note that the first access delay might be extended by another 1-3 wait cycles in case the burst read or write access collides with an ongoing self-refresh operation. Table 11 Latency Mode Configuration Max. Input Clock Frequency [MHz] -9.6 0 1 2 3 reserved reserved 66 104 -12.5 reserved reserved 50 80 -15 reserved reserved 40 66 Latency Mode CLK Control Read N NOP NOP NOP NOP NOP NOP NOP code0 (reserved) DQx QN+1 code1 (reserved) QN+2 QN+3 QN+4 QN+5 QN+6 QN+7 DQx code2 QN+1 QN+2 QN+3 QN+4 QN+5 QN+6 QN+7 DQx code3 QN+1 QN+2 QN+3 QN+4 QN+5 QN+6 QN+7 DQx QN+1 QN+2 QN+3 QN+4 QN+5 QN+6 QN+7 Don't Care Figure 11 Latency Mode - Functional Diagram Data Sheet 27 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description 2.4.2 Read Burst Configurations/Sequences The numbers of words that are read during a burst read access is defined by the burst length field which is programmed in the Bus Control Register. The user can either program fixed burst lengths of 4-words, 8-words or 16-words or operate the device in continuous mode operation. The burst start address is latched by ADV set to low. An internal address counter then increments automatically the address with respect to the programmed burst length. Continuous burst operation does not stop automatically though a row boundary has been reached. In other words, unlike with fixed burst lengths, a continuous burst goes on until it is actively terminated by bringing CS to high sampled at the valid edge of CLK. The wrap mode option specifies whether the burst address overflows and restarts at address 0 (A3 - A0) or keeps incrementing. In continuous burst mode, the internal address counter wraps to 000000H if the operation goes on past the last address, 1FFFFFH regardless of wrap mode setting. For the several possible burst sequences please refer to Table 12. The burst length is only configurable for burst read while burst write uses always continuous burst mode, independent of the burst length setting in the burst control register BCR. Same for burst wrap, in burst write there is always the default - no wrap - used, independent on read burst register setting. Table 12 Burst Sequences Starting Address (A3 A2 A1 A0) Wrap On 4 xx00 xx01 xx10 xx11 x000 x001 x010 x011 x100 x101 x110 x111 0000 0001 0010 ... ... 1101 1110 1111 n 0123 1230 2301 3012 01234567 12345670 23456701 34567012 45670123 56701234 67012345 70123456 0 1 2 ... 13 14 15 1 2 3 ... 14 15 0 2 3 4 ... 15 0 1 ... ... 13 14 15 ... 10 11 12 14 15 0 ... 11 12 13 15 0 1 ... 12 13 14 Sequential Burst Addressing Scheme (decimal) Wrap Off 0123 1234 2345 3456 01234567 12345678 23456789 3 4 5 6 7 8 9 10 4 5 6 7 8 9 10 11 5 6 7 8 9 10 11 12 6 7 8 9 10 11 12 13 7 8 9 10 11 12 13 14 0 1 2 ... 13 14 15 1 2 3 ... 14 15 16 2 3 4 ... 15 16 17 ... ... 13 14 15 ... 26 27 28 14 15 16 ... 27 28 29 15 16 17 ... 28 29 30 Burst Length 8 16 Continuous 1) Cmax = 1FFFFFH Cn, Cn+1, Cn+2, ... Cmax1), 0, 1, ... (default, write burst) Data Sheet 28 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description 2.4.3 WAIT Signal in Synchronous Burst Mode The WAIT signal is used in synchronous burst read mode to indicate to the host system when the output data is invalid. Periods of invalid output data within a burst access might be caused either by first access delays, by delays induced by row boundary crossings or by self-refresh cycles. To match with the Flash interfaces of different microprocessor types the polarity and the timing of the WAIT signal can be configured. The polarity can be programmed to either active low or active high logic. The timing of the WAIT signal can be adjusted as well. Depending on the BCR setting the WAIT signal will be either asserted at the same time the data becomes invalid or it will be set active already one clock period in advance. In asynchronous read mode including page mode, the WAIT signal is not used but always stays asserted as BCR bit 10 is specified. In this case, system should ignore WAIT state, since it does not reflect any valid information of data output status. 2.4.4 Hold Data Out Mode The configuration of Hold Data Out mode is not supported. Please note that valid data is held always for one clock cycle. BCR.WP= 0 BCR.HDO= 0 BCR.WC=1: BCR.WC=0: CLK WAIT WAIT DQ15-DQ0 BCR.WP= 0 BCR.HDO= 1 Q0 Q1 Q2 Q3 Q4 Q5 Not supported Don't care Figure 12 Data Out Configuration 2.5 Self-Refresh The CellularRAM relieves the host system from triggering and commanding refresh-operations like it is the case with conventional DRAMs by performing automatic self-refresh. Self-refresh operations are autonomously scheduled and performed by the CellularRAM device. Data Sheet 29 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description Bus Control Register (BCR) A19 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 1 OM 0 Latency Mode WP 0 WC 0 1 IMP 0 BW Burst Length Control Register Control Register Select A19 0 1 control reg selects RCR selects BCR Operation Mode A15 0 1 opmode sync mode async./ page mode (def) WAIT Polarity A10 0 1 polarity active low active high (def) WAIT Configuration A8 0 1 timing at delay one data cycle in advance (def) Output Impedance latency reserved reserved code2 code3 (def) A5 0 1 Drive strength full drive (def) 1/4 drive Burst Length A2 0 0 0 1 A1 0 1 1 1 A0 1 0 1 1 length 4 8 16 continuous (def) all others reserved Latency Mode A13 A12 A11 0 0 0 0 0 0 1 1 0 1 0 1 Burst Wrap A3 0 1 wrap mode wrap no wrap (def) (note) A9 must be set to "0" for proper operation (note) A6 must be set to "1" for proper operation all others reserved Data Sheet 30 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description 2.6 SRAM-Type Mode In SRAM-type mode the CellularRAM applies the standard asynchronous SRAM protocol to perform read and write accesses. 2.6.1 Asynchronous Read After power-up the CellularRAM operates per default in asynchronous SRAM-type mode. The synchronous clock line, CLK has to be held low, while address latch signal, ADV can be held low for entire read and write operation in this mode or toggled to latch valid address input (refer to "Asynchronous Write with Address Latch (ADV) Control" on Page 40 for details). WAIT is always asserted as BCR. Bit 10 is programmed, so that the controller should ignore WAIT during asynchronous mode operation. Reading from the device in asynchronous mode is accomplished by asserting the Chip Select (CS) and Output Enable (OE) signals to low while forcing Write Enable (WE) to high. If the Upper Byte (UB) control line is set active low then the upper word of the addressed data is driven on the output lines, DQ15 to DQ8. If the Lower Byte (LB) control line is set active low then the lower word of the addressed data is driven on the output lines, DQ7 to DQ0. The access time is determined by the triggering input - slowest one in low-going transition - among valid address (tAA), CS(tCO), OE(tOE), UB or LB(tBA), or ADV(tAADV). tRC A20-A0 tOH tAA ADDRESS DQ15-DQ0 Previous Data Data Valid Not Valid Figure 13 Asynchronous Read - Address Controlled (CS = OE = VIL, WE = VIH, UB and/or LB = VIL, CRE = VIL, ADV = VIL) tRC A20-A0 tVPH tAA tAADV ADDRESS tOH ADV CS tCPH tCO tBPH UB, LB tBA tBHZ WE tHZ OE tLZ tBLZ tOLZ tOE tOHZ Data Valid DQ15-DQ0 Don't Care Figure 14 Asynchronous Read (WE = VIH, CRE = VIL) Data Sheet 31 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description 2.6.2 Page Mode If activated by RCR.Bit7 page mode allows to toggle the four lower address bits (A3 to A0) to perform subsequent random read accesses (max. 16-words by A3 - A0) at much faster speed than 1st read access. Page mode operation supports only read access in CellularRAM. As soon as page mode is activated, CS low time restriction (tCSL ) applies. In case of CS staying low longer than tCSL limit, then it is alternative way to toggle non-page address (A20 - A4) no later than tCSL,max. Therefore the usage of page mode is only recommended in systems which can respect this limitation. ADV has to be held low for entire page operation. Please see also application note on Page 50. A20-A4 tRC ADDRESS tPC ADR ADR ADR ADR A3-A0 ADDRESS tAA CS tCO tCSL tHZ UB, LB tBHZ WE tBLZ OE tOLZ tOH Data tPAA Data Data Data Data tOHZ tLZ DQ15-DQ0 Don't Care Figure 15 Asynchronous Page Read Mode (CRE = VIL, ADV = VIL) Data Sheet 32 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description Table 13 Parameter Read cycle time Address access time ADV access time ADV high time Page address cycle time Page address access time Output hold from address change Chip select access time UB, LB access time OE to valid output data Chip select pulse width low time Chip select to output active Chip select disable to high-Z output UB, LB enable to output active UB, LB disable to high-Z output Output enable to output active Output disable to high-Z output CS high time when toggling UB, LB high time when toggling Timing Parameters - Asynchronous Read Symbol 9.6, 12.5 Min. Max. - 70 70 - - 20 - 70 70 20 10 - 8 - 8 - 6 - - Min. 85 - - 7 25 - 6 - - - - 6 - 6 - 3 - 15 15 70 - - 5 20 - 5 - - - - 6 - 6 - 3 - 10 10 15 Max. - 85 85 - - 25 - 85 85 25 10 - 8 - 8 - 8 - - ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns ns - - - - - - - - - - - - - - - - - - - Unit Notes tRC tAA tAADV tVPH tPC tPAA tOH tCO tBA tOE tCSL tLZ tHZ tBLZ tBHZ tOLZ tOHZ tCPH tBPH Data Sheet 33 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description 2.6.3 Asynchronous Write Writing to the device in asynchronous SRAM mode is accomplished by asserting the Chip Select (CS) and Write Enable (WE) signals to low. ADV can be used to latch the address (refer to "Asynchronous Write with Address Latch (ADV) Control" on Page 40 for details) or simply held low for entire write operation. If the Upper Byte (UB) control line is set active low then the upper word (DQ15 to DQ8) of the data bus is written to the specified memory location. If the Lower Byte (LB) control line is set active low then the lower word (DQ7 to DQ0) of the data bus is written to the specified memory location. Write operation takes place when either one or both UB and LB is asserted low. The data is latched by the rising edge of either CS, WE, or UB/LB whichever signal comes first. tWC A20-A0 tVPH ADDRESS tAW tWR ADV tVS CS tCW UB, LB tBW tWPH WE tAS tWP tDW tDH Data Valid tWHZ tOW DQx IN DQx OUT Don't Care Figure 16 Asynchronous Write - WE Controlled (OE = VIH or VIL, CRE = VIL) tWC A20-A0 tVPH ADDRESS tAW tWR ADV tVS tAS t CPH tCW CS UB, LB tBW WE tWP tDW tDH DQx IN tWHZ tLZ, tBLZ Data In Valid DQx OUT Don't Care High-Z Figure 17 Data Sheet Asynchronous Write - CS Controlled (OE = VIH or VIL, CRE = VIL) 34 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description tWC A20-A0 tVPH ADDRESS tAW tWR ADV tVS CS tAS tCW tBPH tBW UB, LB WE tWP tDW tDH DQx IN tWHZ tBLZ, tLZ Data In Valid DQx OUT Don't Care High-Z Figure 18 Asynchronous Write - UB, LB Controlled (OE = VIH or VIL, CRE = VIL) The programming of control register in SRAM-type mode is performed in the similar manner as asynchronous write except CRE being held high during the operation. Note that CRE has to meet set-up (tCRES) and hold time (tCREH) of valid state (= High) in reference to WE falling and rising edge, respectively. ADV may be kept low for entire operation. CS should toggle at the end of the operation to get ready for following access. tWC A20-A0 OPCODE tAW tWR A19 tVPH 0(RCR), 1(BCR) ADV CS tCW UB, LB tWPH WE tAS tWP CRE tCRES tAW tCREH DQx IN tWHZ tLZ, tBLZ Don't Care High-Z DQx OUT High-Z Figure 19 Data Sheet Asynchronous Write to Control Register (OE = VIH or VIL) 35 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description Table 14 Parameter Write cycle time Address (incl. CRE) set-up time Address valid to end of write Write recovery time Chip select pulse width low time Chip select to end of write ADV high time ADV setup to end of write Byte control valid to end of write Write pulse width Write pulse pause CS high time when toggling UB, LB high time when toggling Write to output disable End of write to output enable (OE = low) Write data setup time Write data hold time CRE setup time (to WE = CE = low) CRE hold time (from WE high) Timing Parameters - Asynchronous Write Symbol 9.6, 12.5 Min. Max. - - - - 10 - - - - - - - - 8 - - - - - Min. 85 0 85 0 - 85 7 85 85 45 15 15 15 - 3 20 0 5 0 70 0 70 0 - 70 5 70 70 40 10 10 10 - 3 20 0 5 0 15 Max. - - - - 10 - - - - - - - - 10 - - - - - ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns - - - - - - - - - - - - - - - - - - - Unit Notes tWC tAS tAW tWR tCSL tCW tVPH tVS tBW tWP tWPH tCPH tBPH tWHZ tOW tDW tDH tCRES tCREH Data Sheet 36 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description 2.7 NOR-Flash-Type Mode In NOR-Flash mode the CellularRAM applies the NOR-Flash protocol to perform read and write accesses to the memory. Read accesses can be executed in synchronous burst mode, while write accesses are executed in asynchronous mode using ADV as address latch strobe signal. 2.7.1 Synchronous Read Mode [Disclaimer] WAIT signal of all synchronous timings below is shown in the case of WC=0 (at delay) and WP=0 (active low) though it is not default state. In synchronous read mode all operations are referred to the rising or falling clock signal edge. Refresh cycles or page boundary crossings are indicated by the WAIT output signal which stalls the processor for this period. tCLK tCKL CLK tSP tHD ADR tHD tCKH A20-A0 tSP tVPH ADV tVP tABA tHD tCBPH CS tCSS tOD tAOE OE tSP tHD tOL WE UB, LB tCWT Latency Code2 tWK tKOH tACLK tWZ WAIT DQ15-DQ0 Don't Care Q0 Q1 Q2 Q3 Q4 in case the burst read access collides with an ongoing refresh cycle addi ti onal WAIT cycles might be inserted While row boundary crossing occurs, WAIT is asserted Figure 20 Synchronous Read Burst Data Sheet 37 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description 2.7.2 Burst Suspend While in synchronous burst operation, the bus interface may need to be assigned to other memory transaction sharing the same bus. Burst suspend mode is used to fulfill this operation. Keeping CS low (WAIT stays asserted indicating valid data output on DQ pins, though they are tri-stated), burst suspend can be initiated with halted CLK. CLK can stay at either high or low state. As specified, duration of keeping CS low can not exceed tCSL maximum, which is 10 s, so that internal refresh operation is able to run properly. In this event of exceeding tCSL maximum, termination of burst by bringing CS to high is strongly recommended instead of using burst suspend mode, then reissuing of the discontinued burst command is required. t CL K Burst Suspend tC KL C LK t SP t HD t CK H A20-A0 A DR t SP ADV tVP H tC SS tV P tABA t C SL tO D tH D t CB P H CS OE tS P t AO E tOL *1 WE tH D tA O E UB , LB tCW T Latency C ode2 tW K tA C L K tO D Q0 Q1 t KO H Q1 Q2 Q3 tW Z W A IT D Q 15-D Q 0 Don't C are *1: In case /O E being held low , Q 1 is m aintain ed on DQ /C S low tim e in b urst suspend shou ld not exceed 10us for intern al refresh operation. Figure 21 Burst Suspend Data Sheet 38 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description Table 15 Parameter Clock period frequency Clock period Clock high time Timing Parameters - Synchronous Read Burst Symbol Min. Lat = 3 fCLK3 Lat = 2 fCLK2 Lat = 3 tCLK3 Lat = 2 tCLK2 - - 9.6 15 3 3 - 3 1.5 5 4 - 3.5 - 5 3 0 - - 0 - - 2 9.6 Max. 104 66 - - - - 1.8 - - - - 35 20 10 - - 6 20 7 7 7 7 - - - 12.5 20 3.5 3.5 - 3.5 2 5 4 - 4 - 6 3 0 - - 0 - - 2 12.5 Min. Max. 80 50 - - - - 2 - - - - 46.5 20 10 - - 8 20 9 8 9 9 - Min. - - 15 25 4 4 - 4 2 7 6 - 4 - 8 3 0 - - 0 - - 3 15 Max. 66 40 - - - - 2 - - - - 54 20 10 - - 8 25 11 8 11 11 - MHz - MHz - ns ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns - - - - - - - 1) Unit Notes tCKH tCKL Clock low time tT Clock rise/fall time tSP Input setup time to CLK (except CS) tHD Input hold time from CLK tVPH ADV pulse width high ADV pulse width low tVP st Burst read 1 access delay from CLK tABA CS low setup to CLK tCSS Chip select pulse width low time tCSL tCBPH CS pulse width high tOL OE or LB/UB low to output low-Z CS, OE, or LB/UB high to output high-Z tOD tAOE OE low to output delay tCWT CS low to WAIT valid tWZ CS high to WAIT high-Z tWK CLK to WAIT valid tACLK CLK to output delay tKOH Output hold from CLK - 2) 3) - - - - - - - - - - 1) ADV low for new burst command can not be issued while the previous burst is in burst_init cycle (within latency). 2) In case of refresh collision to the first access, more WAIT cycles will be added. 3) For proper synchronous burst operation, tCSSmax should be met. Otherwise, it is strongly recommended to use CellularRAM in asynchronous mode of operation, instead. Data Sheet 39 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description 2.7.3 Asynchronous Write with Address Latch (ADV) Control In asynchronous write mode, the synchronous clock is switched off and CLK has to be held low. The access protocol is shown with ADV-latching scheme and it can be applied to write operation in SRAM-type mode. CLK tWC tAW tCKA tSP tHD A20-A0 tVPH ADDRESS tAVS tVP tVS tAS tCPH tCW tAVH ADR tSP tVP tABA tCSS tOD tAOE tWR tWP tSP tHD tOL tHD ADV CS tCBPH OE tWPH WE UB, LB tBW Latency Code2 tWZ tWK tACLK Q0 tKOH WAIT tDS tDH Data Input tCWT DQ15-DQ0 Don't Care Figure 22 Asynchronous Write with Address Latch (ADV) Control (followed by single-burst read) tW C tA W A 2 0 -A 0 ADDR ESS tA V S tA V H ADV CS tV P tV S tAS tC W OE tW P H tW R tW P WE UB, LB tB W tD S tD H D a ta In p u t D o n 't C a r e D Q 1 5 -D Q 0 Figure 23 Asynchronous Write with Address Latch (ADV) Control Data Sheet 40 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description The programming of control register in NOR-Flash-type mode is performed in the similar manner as asynchronous write with ADV control except CRE being held high during the code input operation. Note that CRE has to meet set-up (tCRS) and hold time (tCRH) of valid state (= High) in reference to ADV rising edge. ADV may be kept low for entire operation or go high to latch valid control register information at its rising edge. CLK tWC tAW tCKA A20-A0 opcode tAVS tAVH tWR ADDRESS A19 0(RCR), 1(BCR) tCRH CRE tVPH tCRS ADV CS tVP tVS tCW OE tWPH tWP WE UB, LB DQ15-DQ0 Don't Care Figure 24 Table 16 Parameter Asynchronous Write To Control Register in NOR-Flash Mode Timing Parameters - Asynchronous Write With ADV Control Symbol 9.6, 12.5 Min. Max. - - - - - - - - - - - - - - Min. 35 85 0 10 5 85 10 10 85 85 85 45 15 8 25 70 0 10 5 70 8 8 70 70 70 40 10 5 15 Max. - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns - - - - - - - - - - - - - - Unit Notes WE high to CLK valid Write cycle time Address setup time to write start Address setup to ADV high Address hold from ADV high Address to end of write ADV pulse width high ADV pulse width low ADV setup to end of write CS to end of write UB/LB to end of write Write pulse width low Write pulse width high CS high time (synch_read) tCKA tWC tAS tAVS tAVH tAW tVPH tVP tVS tCW tBW tWP tWPH tCBPH Data Sheet 41 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description Table 16 Parameter CS high time (asynch_write, mixed) Write recovery time Data setup to WE high Data hold from WE high CRE setup to ADV high CRE hold from ADV high Timing Parameters - Asynchronous Write With ADV Control (cont'd) Symbol 9.6, 12.5 Min. Max. - - - - - - Min. 15 0 20 0 10 5 10 0 20 0 10 5 15 Max. - - - - - - ns ns ns ns ns ns - 1 - - - - Unit Notes tCPH tWR tDS tDH tCRS tCRH Note: 1. tWR is valid only when ADV latch of address does not take place until the end of write. Data Sheet 42 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description 2.8 Synchronous Mode [Disclaimer] WAIT signal of all synchronous timings below is shown in the case of WC=0 (at delay) and WP=0 (active low) though it is not default state. In synchronous mode, read and write operations are synchronized to the clock. Refresh cycles or page boundary crossings are indicated to the host system by asserting the WAIT signal which in turn stalls the processor. WAIT polarity, WAIT timing, synchronicity to the falling/rising clock edge, the burst length and further options are user configurable and can be programmed via the bus configuration register (BCR). 2.8.1 Synchronous Read Mode Including Burst Suspend Refer to Section 2.7.1 and Section 2.7.2. All the timing and parameters are same as described in read operation for NOR-Flash-Type mode. 2.8.2 Synchronous Write Mode In synchronous write mode, UB and LB are used as byte control of data input mask. At the rising edge of CLK, their state is sampled and determined whether the coupled byte (DQ15-8 for UB and DQ7-0 for LB) is updated by input data. Proper set-up time and hold time to CLK should be met. As discussed in Section 2.4, synchronous burst write is always configured as continuous and no wrap, so that it has to be terminated by CS high state after the burst fulfills required length of cycles. tCLK tCKL CLK tSP tHD tCKH A20-A0 ADR tSP ADV tVPH tVP tCSS tHD tCBPH CS OE t SP tHD WE tSP UB, LB tCWT tWK tHD tWZ Hi-z Latency Code2 (mask) tHD D0 t SP D1 D2 D3 D4 WAIT DQ15-DQ0 Don't Care in case the burst write access collides with an ongoing refresh cycle additional WAIT cycles might be inserted Figure 25 Synchronous Write Burst Data Sheet 43 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description tCLK tCKL CLK tSP tHD tCKH A20-A0 OPCODE tSP tHD A19 0(RCR), 1(BCR) tSP tHD CRE tSP tHD ADV tCSS tHD CS (wait for tWCmin for new command cycle) OE tSP tHD WE UB, LB tCWT Hi-z tWZ WAIT DQ15-DQ0 Don't Care Figure 26 Synchronous Write to Control Register Data Sheet 44 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description tCLK tCKL CLK tSP tHD tCKH tSP tHD ADR A20-A0 ADR ADV tVP tCSS tCBPH tHD tCSS tCBPH tVP CS tABA tHD tOD tAOE OE tSP tHD tSP tHD tOL WE UB, LB tCWT Hi-z Latency Code2 tWK tHD D0 tSP Don't Care D1 D2 D3 tWZ tCWT tACLK Q0 Q1 Latency Code2 tWK tKOH Q2 Q3 tWZ WAIT DQ15-DQ0 in case the burst write access collides with an ongoing refresh cycle additional WAIT cycles might be inserted Figure 27 Synchronous Write Burst Followed by Synchronous Read Burst tCLK tCKL CLK tSP tHD tCKH tSP tHD A20-A0 ADR ADR ADV tVPH tVP tCBPH tCSS tOD tAOE tSP tHD tOL tSP tVP tHD CS tCSS tABA tHD OE tHD WE UB, LB tCWT Latency Code2 tWK tACLK tKOH Q0 Q1 Q2 Q3 tWZ tCWT (Hi-z) Latency Code2 D0 tSP D1 tHD D2 D3 tWZ tWK WAIT DQ15-DQ0 Don't Care in case the burst access collides with an ongoing refresh cycle additional WAIT cycles might be inserted Figure 28 Synchronous Read Burst Followed by Synchronous Write Burst Data Sheet 45 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Functional Description Table 17 Parameter Clock period frequency Clock period Clock high time Timing Parameters - Synchronous Read/Write Burst Symbol Min. Lat = 3 fCLK3 Lat = 2 fCLK2 Lat = 3 tCLK3 Lat = 2 tCLK2 - - 9.6 15 3 3 - 3 1.5 5 4 - 3.5 - 5 3 0 - - 0 - - 2 9.6 Max. 104 66 - - - - 1.8 - - - - 35 20 10 - - 6 20 7 7 7 7 - - - 12.5 20 3.5 3.5 - 3.5 2 5 4 - 4 - 6 3 0 - - 0 - - 2 12.5 Min. Max. 80 50 - - - - 2 - - - - 46.5 20 10 - - 8 20 9 8 9 9 - Min. - - 15 25 4 4 - 4 2 7 6 - 4 - 8 3 0 - - 0 - - 3 15 Max. 66 40 - - - - 2 - - - - 54 20 10 - - 8 25 11 8 11 11 - MHz - MHz - ns ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns - - - - - - - 1) Unit Notes tCKH tCKL Clock low time tT Clock rise/fall time tSP Input setup time to CLK (except CS) tHD Input hold time from CLK tVPH ADV pulse width high ADV pulse width low tVP st Burst read 1 access delay from CLK tABA CS low setup to CLK tCSS Chip select pulse width low time tCSL tCBPH CS pulse width high tOL OE or LB/UB low to output low-Z CS, OE, or LB/UB high to output high-Z tOD tAOE OE low to output delay tCWT CS low to WAIT valid tWZ CS high to WAIT high-Z tWK CLK to WAIT valid tACLK CLK to output delay tKOH Output hold from CLK - 2) 3) - - - - - - - - - - 1) ADV low for new burst command can not be issued while the previous burst is in burst_init cycle (within latency). 2) In case of refresh collision to the first access, more WAIT cycles will be added. 3) For proper synchronous burst operation, tCSSmax should be met. Otherwise, it is strongly recommended to use CellularRAM in asynchronous mode of operation, instead. 2.9 General AC Input/Output Reference Waveform The input timings refer to a midlevel of VDDQ/2 while as output timings refer to midlevel VDDQ/2. The rising and falling edges are 10 - 90% and < 2 ns. Data Sheet 46 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Electrical Characteristics 3 3.1 Table 18 Parameter Electrical Characteristics Absolute Maximum Ratings Absolute Maximum Ratings Symbol Limit Values Min. Max. +85 +150 260 +2.45 +3.6 +3.6 180 +50 C C C V V V mW mA - - - - - - - - -25 -55 - -0.3 -0.3 -0.3 - -50 Unit Notes Operating temperature range Storage temperature range Soldering peak temperature (10 s) Voltage of VDD supply relative to VSS Voltage of VDDQ supply relative to VSS Voltage of any input relative to VSS Power dissipation Short circuit output current TC TSTG TSold VDD VDDQ VIN PD IOUT Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 3.2 Recommended Power & DC Operation Ratings All values are recommended operating conditions unless otherwise noted. Table 19 Parameter Power supply voltage, core Power supply voltage, 1.8 V I/Os Input high voltage Input low voltage Table 20 Parameter Output high voltage (IOH = -0.2 mA) Output low voltage (IOL = 0.2 mA) Input leakage current Output leakage current DC Characteristics Symbol Min. Limit Values Typ. - - - - Max. - V V A A - - - - Unit Notes Recommended DC Operating Conditions Symbol Min. Limit Values Typ. 1.8 1.8 - - Max. 1.95 2.25 V V V V - - - - 1.7 1.7 Unit Notes VDD VDDQ VIH VIL VDDQ - 0.4 -0.2 VDDQ + 0.2 0.4 VOH VOL ILI ILO VDDQ x 0.8 - - - VDDQ x 0.2 1 1 Data Sheet 47 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Electrical Characteristics Table 21 Parameter Operating Current * * * * * Async read/write random @tRCmin Async read/write random @tRC=1s Async Page read Sync burst (continuous) Burst Initial access IDD1 IDD1L IDD1P IDD4 IDD5 - - - - - - - 20 5 15 20 35 90 120 - - - - - - - 20 5 15 18 35 90 120 - - - - - - - 17 5 12 15 30 90 120 A A A Operating Characteristics Symbol 9.6 12.5 15 Unit Test Notes 1) Min. Max. Min. Max. Min. Max. mA Condition Vin = VDD or VSS, Chip enabled, Iout = 0 Stand-By Current : L-part Stand-By Current : Standard Deep Power Down Current IDD2 Vin = VDD or VSS,Chip deselected, (Full array) - - IDD3 - 25 - 25 - 25 Vin = VDD or VSS - 1) The specification assumes the output disabled. 3.3 Output Test Conditions VDDQ 5.4kOhm DUT 5.4kOhm 30pF Test point Figure 29 Output Test Circuit Please refer to section Section 2.9. 3.4 Table 22 Pin Pin Capacitances Pin Capacitances Limit Values Min. Max. 5.0 5.0 6.0 6.0 pF pF pF pF - - - - Unit Condition A20 - A0, CS, OE, WE, UB, LB, CRE, ADV CLK DQ15 - DQ0 WAIT TA = +25 C freq. = 1 MHz Vpin = 0 V (sampled, not 100% tested) Data Sheet 48 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Package Outlines 4 Package Outlines Figure 30 P-VFBGA-54 (Plastic Very Thin Fine Pitch Ball Grid Array Package) You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. SMD = Surface Mounted Device Data Sheet 49 Dimensions in mm V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Appendix A: Low-Frequency Mode 5 5.1 Appendix A: Low-Frequency Mode Asynchronous Access Depending on the random access frequency two cases are distinguished: High Frequency Mode ( 100 kHz): There are no tRC max. time nor CS/OE max. low time restrictions during subsequent random read or write accesses. Low Frequency Mode (< 100 kHz): There are no tRC max. time nor CS/OE max. low time restrictions if all control signals (CS, OE, WE, UB/LB) follow the modified timing as shown below, see attached timing diagram and timing table. There is no extra mode register setting necessary. tARV tAWV ADDRESS A20-A0 CS tAA WE tWPV tDWV Data Valid DQ<15:0> Data Valid Figure 31 Parameter Low-Frequency Mode Symbol Min. 9.6, 12.5 Max. - - - - Min. 85 85 85 85 70 70 70 70 15 Max. - - - - ns ns ns ns - - - - Unit Notes Address stable time for read access Address stable overlap with write pulse Write pulse width Data to write time overlap tARV tAWV tWPV tDWV Data Sheet 50 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Appendix B: S/W Register Entry Mode ("4-cycle method") 6 Appendix B: S/W Register Entry Mode ("4-cycle method") Other than CRE-controlled SCR operation, CellularRAM supports software (S/W) method as an alternative to access the control registers. Since S/W register entry mode consists of 4 consecutive access cycles to top memory location (all addresses are "1"), it is often referred as "4-cycle method". 4-cycles starts from 2 back-to-back read cycles (initializing command identification) followed by one write cycle (command identification completed and which control register is accessed is known), then final write cycle for configuring the selected control register by the given input or read cycle to check the content of the register through DQ pins. It does function the configuration of control register bits like the way with dedicated pin, CRE method, but there are a few differences from CREcontrolled method as follow; * * Register read mode (checking content) is supported with S/W register entry as well as register write (program). The mode bits for control register are supplied through DQ <15:0> instead of address pins in CRE-controlled. Though each register has 21-bits (A<20:0>) for 32M CellularRAM, only low 16-bit registers becomes valid during S/W method. Only asynchronous read and write is allowed for consecutive 4 access cycles to top address. No synchronous timing is supported. If this entry mode is used in synchronous mode, then clock should stop running and stay at low level. Instead of A19 bit state, the selection of which control register, BCR or RCR, is done with the state of DQ<15:0> given at 3rd cycle. ("00h" for RCR, "01h" for BCR) Since S/W register entry asks for 4 complete access cycles in a row and the device is designed operating with internally regulated supply which is going to be discharged in deep power-down (DPD) mode, DPD function is not supported with this programming method. The method is realized by the device exactly when 2 consecutive read cycles to top memory location is followed by write cycle to the same location, so that any exceptional cycle combination - not only access mode, but also the number of cycles - will fail in invoking the register entry mode properly. * * * * tRC Amax-A0 tWC All "1"s All "1"s All "1"s All "1"s ADV# CS UB, LB WE OE DQ15-DQ0 (Cycle Type) (Function) Read to top memory location (1st) Read to top memory location (2nd) Wait for next write to confirm S/W register entry 0000h(RCR) or 0001h(BCR) Register bits Write to top memory location Select RCR or BCR Write or Read to top memory location (Write) Configure selected register by DQ inputs (Read) Output selected register contents through DQ Don't Care Figure 32 S/W Register Entry timing (Address input = 1FFFFFh) Data Sheet 51 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Appendix B: S/W Register Entry Mode ("4-cycle method") D15 D8 D7 D6 D5 D4 D3 D2 D1 D0 DQ<15:0> 0 0 PM TCSR DPD* 0 PASR Control Register Page Mode Bit D7 0 1 page mode disabled (def.) enabled Deep Power Down Mode D4 X power down disabled (def.) Partial Array Self Refresh D2 0 0 0 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 refreshed memory area entire memory array (def.) lower 1/2 of memory array lower 1/4 of memory array lower 1/8 of memory array zero upper 1/2 of memory array upper 1/4 of memory array upper 1/8 of memory array D15....D8, D3: reserved, must be set to '0'. Temperature-Compensated Self-Refresh D6 1 0 0 1 D5 1 0 1 0 max. case temp. +85C (def.) +70C +45C +15C 0 1 1 1 1 Figure 33 RCR Mapping in S/W Register Entry D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DQ <15:0> OM 0 Latency Mode WP 0 WC 0 1 IMP 0 BW Burst Length Control Register Burst Length D2 0 0 0 Operation Mode D15 0 1 opmode sync mode async./ page mode (def) WAIT# Polarity D10 0 1 polarity active low active high (def) WAIT# Configuration D8 0 1 timing at delay one data cycle in advance (def) Output Impedance latency reserved reserved code2 code3 (def) D5 0 1 wrap mode full drive (def) 1/4 drive Burst Wrap D3 0 1 wrap mode wrap no wrap (def) 1 D1 0 1 1 1 D0 1 0 1 1 length 4 8 16 continuous (def) all others reserved Latency Mode D13 D12 D11 0 0 0 0 0 0 1 1 0 1 0 1 all others reserved Figure 34 BCR Mapping in S/W Register Entry Data Sheet 52 V2.0, 2003-12-16 www.infineon.com Published by Infineon Technologies AG |
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