 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE LOW VOLTAGE PLL CLOCK DRIVER IDT5V9351 FEATURES: * * * * * * * * Fully integrated PLL Output frequency up to 200MHz 2.5V and 3.3V Compatible Compatible with PowerPCTM, Intel, and high performance RISC microprocessors Output frequency configurable Cycle-to-cycle jitter max. 22ps RMS Compatible with MPC9351 Available in TQFP package DESCRIPTION: The IDT5V9351 is a high performance, zero delay, low skew, phase-lock loop (PLL) clock driver. It has four banks of configurable outputs. The IDT5V9351 uses a differential PECL reference input and an external feedback input. These features allow the IDT5V9351 to be used as a zero delay, low skew fan-out buffer. REF_SEL allows selection between PECL input or TCLK, a CMOS clock driver input. If PLL_EN is set to low and REF_SEL to high, it will bypass the PLL. By doing so, the IDT5V9351 will be in clock buffer mode. Any clock applied to TCLK will be divided down to four output banks. When PLL_EN is set high, PLL is enabled. Any clock applied to TCLK will be clocked in both phase and frequency to FBIN. PECL clock is activated by setting REF_SEL to low. FUNCTIONAL BLOCK DIAGRAM (pullup) 0 REF (pulldown) tCLK REF_SEL FBIN (pulldown) (pulldown) 1 1 0 /2 /4 /8 1 0 D Q QA PECL_CLK PECL_CLK PLL FB 200 - 400MHz 0 D 1 PLL_En (pullup) Q QB QC0 0 fSELA fSELB fSELC fSELD (pulldown) 1 (pulldown) QD0 (pulldown) QD1 (pulldown) 0 D 1 QD3 Q QD2 D Q QC1 QD4 OE (pulldown) The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE 1 MARCH 2003 DSC-5972/16 (c) 2003 Integrated Device Technology, Inc. IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION REF_SEL PLL_EN TCLK GND GND VCC QA QB ABSOLUTE MAXIMUM RATINGS(1) Symbol VCC VI VO IIN 24 23 22 21 20 19 18 17 Description Supply Voltage Input Voltage DC Output Voltage Input Current DC Output Current Storage Temperature Max. -0.3 to +4.6 -0.3 to VCC+0.3 -0.3 to VCC+0.3 20 50 -55 to +150 Unit V V V mA mA C 32 VCCA FBIN fSELA fSELB fSELC fSELD GND PECL_CLK 1 2 3 4 5 6 7 8 9 31 30 29 28 27 26 25 QC0 VCC QC1 GND QD0 VCC QD1 GND IO TSTG NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 10 11 12 13 14 15 16 CAPACITANCE (TA = +25C, F = 1.0MHz) Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Min. Typ. 4 10 Max. Unit pF pF PECL_CLK -- -- -- -- VCC QD4 VCC TQFP TOP VIEW GND QD3 QD2 OE GENERAL SPECIFICATIONS Symbol VTT HBM LU Description Output Termination Voltage ESD (Human Body Model) Latch-Up Immunity 2000 200 Min. Typ. VCC/2 Max. Unit V V mA LOGIC DIAGRAM(1,2) RF VCC CF 10nF VCCA VCC 33...100nF NOTES: 1. IDT5V9351 requires an external RC filter for the analog power supply pin VCCA. 2. For VCC = 2.5V, RF = 9-10, CF = 22F. For VCC = 3.3V, RF = 5-15, CF = 22F. 2 IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE PIN DESCRIPTION Terminal Name PECL-CLK PECL-CLK TCLK FBIN REF_SEL fSEL(D:A) OE QA QB QC (1:0) QD (4:0) VCCA VCC GND PLL_EN 30 2 32 3, 4, 5, 6 10 28 26 22, 24 12, 14, 16, 18, 20 1 11, 15, 19, 23, 27 7, 13, 17, 21, 25, 29 31 I PLL enable input. When set HIGH, PLL is enabled. When set LOW, PLL is disabled. Ground Negative power supply PWR PWR Positive power supply for PLL Positive power supply for I/O and core I I I I I O O O O Single-ended reference clock signal or test clock Feedback signal input Reference clock input Frequency control pin Output enable/disable Bank A clock output Bank B clock output Bank C clock output Bank D clock output No. 8, 9 Type I Description Differential clock reference, LOW voltage positive ECL input FUNCTIONALITY Control REF_SEL PLL_EN OE FSELA FSELB FSELC FSELD Default 0 1 0 0 0 0 0 0 Selects PECL_CLK as reference clock Test mode with PLL Disabled Outputs enabled QA = VCO / 2 QB = VCO / 4 QC = VCO / 4 QD = VCO / 4 1 Selects TCLK as reference clock PLL Enabled Outputs disabled QA = VCO / 4 QB = VCO / 8 QC = VCO / 8 QD = VCO / 8 NOTE: 1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to FBIN. 3 IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE FUNCTION TABLE(1) INPUTS fSELA 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 fSELB 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 fSELC 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 fSELD 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QA 2 * CLK 2 * CLK 4 * CLK 4 * CLK 2 * CLK 2 * CLK 4 * CLK 4 * CLK CLK CLK 2 * CLK 2 * CLK CLK CLK 2 * CLK 2 * CLK OUTPUTS QB CLK CLK 2 * CLK 2 * CLK CLK / 2 CLK / 2 CLK CLK CLK CLK 2 * CLK 2 * CLK CLK / 2 CLK / 2 CLK CLK QC CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK QD CLK CLK / 2 2 * CLK CLK CLK CLK / 2 2 * CLK CLK CLK CLK / 2 2 * CLK CLK CLK CLK / 2 2 * CLK CLK NOTE: 1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to FBIN. DC ELECTRICAL CHARACTERISTICS TA = -40C to +85C, VCC = 3.3V 5% Symbol VIH VIL VPP VCMR VOH VOL ZOUT IIN ICC ICCPLL Parameter Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode(1) Output HIGH Voltage(2) Output LOW Voltage(2) Output Impedance Input Leakage Current Maximum Quiescent Supply Current Maximum PLL Supply Current Test Conditions LVCMOS Inputs LVCMOS Inputs PECL_CLK PECL_CLK IOH = -24mA IOL = 24mA IOL = 12mA Min. 2 -- 250 1 2.4 -- -- -- -- -- -- Typ. -- -- -- -- -- -- -- 14 - 17 -- -- 3 Max VCC + 0.3 0.8 -- VCC - 0.6 -- 0.55 0.3 -- 150 1 5 Unit V V mV V V V A mA mA All VCC Pins VCCA Only NOTES: 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. The IDT5V9351 outputs can drive series or paralell terminated 50 (or 50 to VCC/2) transmission lines on the incident edge. 4 IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE PLL INPUT REFERENCE CHARACTERISTICS VCC = 3.3V 5%, TA = -40C to +85C Symbol tR, tF fREF Parameter TCLK Input Rise/Fall Levels, 0.8V to 2V Reference Input Frequency (1) Min. -- 100 50 25 0 25 Max 1 200 100 50 300 75 Unit ns MHz / 2 feedback / 4 feedback / 8 feedback fREFDC Static Test Mode Reference Input Duty Cycle % NOTE: 1. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider for the TCLK or PECL_CLK inputs. AC ELECTRICAL CHARACTERISTICS (1) TA = -40C to +85C, VCC = 3.3V 5% Symbol tR, tF VPP VCMR tPW tSK(O) fVCO fMAX tPD tPLZ, tPHZ tPZL, tPZH BW tJ tJIT (PER) tJIT () tLOCK Parameter Output Rise/Fall Time Peak-to-Peak Input Voltage Common Mode Range Output Duty Cycle Output to Output Skew PLL VCO Lock Range Maximum Output Frequency Propagation Delay (Static Phase Offset) Output Disable Time Output Enable Time PLL Closed Loop Bandwidth Cycle-to-Cycle Jitter / 4 feedback (Single Output Frequency Configuration) Period Jitter / 4 feedback (Single Output Frequency Configuration) I/O Phase Jitter Maximum PLL Lock Time (2) Conditions 0.55V to 2.4V LVPECL LVPECL 100-200 MHz 50-100 MHz 25-50 MHz Min. 0.1 500 1.2 45 47.5 48.75 -- 200 100 50 25 -50 25 -- -- Typ. -- -- -- 50 50 50 -- -- -- -- -- -- -- -- -- 9 - 20 3 - 9.5 1.2 - 2.1 10 8 4 - 17 -- Max 1 1000 VCC - 0.9 55 52.5 51.75 150 400 200 100 50 150 325 10 10 -- -- -- 22 15 -- 1 Unit ns mV V % ps MHz MHz ps ns ns MHz ps ps ps ms / 2 output / 4 output / 8 output TCLK to FBIN PECL_CLK to FBIN / 2 feedback / 4 feedback / 8 feedback RMS Value RMS Value RMS Value -3db point of PLL transfer characteristic -- -- -- -- -- -- -- NOTES: 1. AC Characteristics apply for parallel output termination of 50 to VTT. 2. VCMR(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within VPP(AC) specifications. 5 IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS TA = -40C to +85C, VCC = 2.5V 5% Symbol VIH VIL VPP VCMR VOH VOL IIN CIN ZOUT CPD ICC ICCPLL Parameter Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode(1) Output HIGH Voltage(2) Output LOW Voltage(2) Input Current Input Capacitance Output Impedance Power Dissipation Capacitance Maximum Quiescent Supply Current Maximum PLL Supply Current Test Conditions LVCMOS Inputs LVCMOS Inputs PECL_CLK PECL_CLK IOH = -15mA IOL = 15mA Min. 1.7 -- 250 1 1.8 -- -- -- -- -- -- -- Typ. -- -- -- -- -- -- -- 4 17 - 20 10 -- 3 Max VCC + 0.3 0.7 -- VCC - 0.6 -- 0.6 150 -- -- -- 1 5 Unit V V mV V V V A pF pF mA mA All VCC Pins VCCA Only NOTES: 1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the HIGH input is within the VCMR range and the input swing lies within the VPP specification. 2. The IDT5V9351 outputs can drive series or paralell terminated 50 (or 50 to VCC/2) transmission lines on the incident edge. PLL INPUT REFERENCE CHARACTERISTICS VCC = 2.5V 5%, TA = -40C to +85C Symbol tR, tF fREF fREFDC Parameter TCLK Input Rise/Fall Levels, 0.7V to 1.7V Reference Input Frequency (1) Min. -- 100 50 25 25 Max 1 200 100 50 75 Unit ns MHz % / 2 feedback / 4 feedback / 8 feedback Reference Input Duty Cycle NOTE: 1. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider for the TCLK or PECL_CLK inputs. 6 IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (1) TA = -40C to +85C, VCC = 2.5V 5% Symbol tR, tF VPP VCMR tPW tSK(O) fVCO fMAX tPD tPLZ, tPHZ tPZL, tPZH BW tJ tJIT (PER) tJIT () tLOCK Parameter Output Rise/Fall Time Peak-to-Peak Input Voltage Common Mode Range Output Duty Cycle Output to Output Skew PLL VCO Lock Range Maximum Output Frequency Input to FBIN Delay Output Disable Time Output Enable Time PLL Closed Loop Bandwidth Cycle-to-Cycle Jitter / 4 feedback (Single Output Frequency Configuration) Period Jitter / 4 feedback (Single Output Frequency Configuration) I/O Phase Jitter Maximum PLL Lock Time (2) Conditions 0.6V to 1.8V LVPECL LVPECL 100-200 MHz 50-100 MHz 25-50 MHz Min. 0.1 500 1.2 45 47.5 48.75 -- 200 100 50 25 -100 0 -- -- Typ. -- -- -- 50 50 50 -- -- -- -- -- -- -- -- -- 4 - 15 2-7 0.7 - 2 10 8 6 - 25 -- Max 1 1000 VCC - 0.6 55 52.5 51.75 150 400 200 100 50 100 300 12 12 -- -- -- 22 15 -- 1 Unit ns mV V % ps MHz MHz ps ns ns MHz ps ps ps ms / 2 output / 4 output / 8 output TCLK to FBIN PECL_CLK to FBIN / 2 feedback / 4 feedback / 8 feedback RMS Value RMS Value RMS Value -3db point of PLL to transfer characteristic -- -- -- -- -- -- -- NOTES: 1. AC Characteristics apply for parallel output termination of 50 to VTT. 2. VCMR(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within VPP(AC) specifications. 7 IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS IDT5V9351 D.U.T. Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 RT = 50 VTT VTT TCLK AC Test Reference for VCC = 2.5V and VCC = 3.3V IDT5V9351 D.U.T. ZO = 50 Pulse Generator Z = 50 ZO = 50 RT = 50 VTT RT = 50 VTT PECL_CLK AC Test Reference 2V VCC/2 Input 0.8V 1ns 1ns VCC 2V 0.8V 0V tCLK VCC/2 Input Characteristics for 3.3V FBIN tPD VCC/2 1.7V VCC/2 Input 0.7V 1ns 1ns VCC 1.7V 0.7V 0V PECL_CLK PECL_CLK Prop Delay Input Characteristics for 2.5V 1.8V VCC/2 0.6V Output tR tF VOH 1.8V 0.6V VOL 0.55V Output tR 2.4V VCC/2 VOH 2.4V 0.55V VOL tF Output Test Conditions for VCC = 2.5V 5% 8 Output Test Conditions for VCC = 3.3V 5% IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE CCLK FBIN TJ(0) = T0 - T1 MEAN I/O Jitter VCC VCC/2 GND tP T0 tPW = tP/T0 x 100% Output Duty Cycle TJ = Tn - Tn+1 Tn Tn+1 Cycle-to-Cycle Jitter TJ(PER) = Tn - 1/f0 T0 Period Jitter 9 IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXXX Device Type XX Package X Process I -40C to +85C (Industriall) PR Thin Quad Flat Pack 5V9351 Low Voltage PLL Clock Driver CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com for Tech Support: logichelp@idt.com (408) 654-6459 10 |
Price & Availability of IDT5V9351PR
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |