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| INTEGRATED CIRCUITS DATA SHEET SAA7712H Sound effects DSP Preliminary specification File under Integrated Circuits, IC02 1999 Aug 05 Philips Semiconductors Preliminary specification Sound effects DSP CONTENTS 1 1.1 1.2 2 3 4 5 6 7 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 8.1.8 8.1.9 8.1.10 8.2 8.2.1 8.2.2 8.2.3 8.3 8.3.1 8.3.2 8.3.3 8.4 8.4.1 8.4.2 8.5 8.6 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 8.6.6 8.6.7 8.7 8.8 8.9 8.10 FEATURES Hardware features Software features APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION FUNCTIONAL DESCRIPTION Analog outputs Analog output circuit DAC frequency DACs Upsample filter Performance Power-On Mute (POM) Power-off plop suppression Pin VREFDA Internal DAC current reference Supply of the analog outputs I2S-bus inputs and outputs Digital data stream formats Slave I2S-bus inputs Master I2S-bus inputs and outputs Equalizer accelerator Introduction Configuration of equalizer sections Overflow detection Clock circuit and oscillator General description Supply of the crystal oscillator Programmable phase-locked loop circuit I2C-bus control Introduction Characteristics of the I2C-bus Bit transfer Start and stop conditions Data transfer Acknowledge State of the I2C-bus interface during and after Power-on reset External control pins Reset pin Power supply connection and EMC Test mode connections 9 9.1 9.2 9.3 9.4 9.5 9.6 10 11 12 13 14 15 16 17 18 19 19.1 19.2 19.3 19.4 19.5 20 21 22 I2C-BUS FORMAT SAA7712H Addressing Slave address (pin A0) Write cycles Read cycles I2C-bus memory map summary I2C-bus memory map details LIMITING VALUES THERMAL CHARACTERISTICS DC CHARACTERISTICS ANALOG OUTPUTS CHARACTERISTICS OSCILLATOR CHARACTERISTICS I2S-BUS TIMING CHARACTERISTICS I2C-BUS TIMING CHARACTERISTICS APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS 1999 Aug 05 2 Philips Semiconductors Preliminary specification Sound effects DSP 1 1.1 FEATURES Hardware features SAA7712H * Digital Signal Processor (DSP) core: - 18 bits data width, 12 bits coefficient width - Separate X, Y and P memories (both 384 bytes word XRAM and YRAM, 3 kbytes word PROM) - 1 kbytes delay line memory suited for Dolby Pro Logic Surround. * Inputs: - 2 slave 18-bit digital stereo inputs: I2S-bus and LSB-justified serial formats - 2 master 18-bit digital stereo inputs: I2S-bus and LSB-justified serial formats. * Outputs: - 4 DACs with 4-times oversampling and noise shaping, fed to 4 output pins and configurable from the DSP program, as left, right, front and surround channels of a Dolby Pro Logic Surround system - 2 master 18-bit digital stereo outputs: I2S-bus and LSB-justified serial formats. * 4-channel 5-band or 2-channel 10-band I2C-bus controlled parametric equalizer * I2C-bus microcontroller interface for: - Access to full X and Y memory space - Control of hardware settings: selectors, programmable clock generations, etc. * Controllable Phase-Locked Loop (PLL) to generate the high frequency DSP clock from common fundamental oscillator crystal * 3.3 V process with 3.3 or 5 V digital periphery: - 3.3 or 5 V I2S-bus and I2C-bus microcontroller interfacing. * Operating temperature range from 0 to 70 C. 1.2 Software features * Dolby Pro Logic Surround/Dolby 3 stereo: Trademark of Dolby Laboratories Licensing Corporation * Noise generation: A pink noise generator is included for installation of the Dolby Pro Logic/Dolby 3 stereo mode * Hall/Matrix Surround: When no Dolby Pro Logic Surround source material is available then this mode can be used to produce a signal in the surround channel * Incredible Surround (222-IS): This algorithm expands the stereo width (stereo expander). This is intended to be used when the 2 speakers are placed close together (TV set and Midi set). * Robust Incredible Surround (222-RIS): Same as incredible surround only an alternative algorithm * 3D Surround (422) or Incredible Virtual Surround: Dolby Pro Logic Surround reproduced by 2 speakers (L and R) * IS-3D Surround (422-IS): Same as 3D Surround (422) only with extra stereo width expander on left and right * RIS-3D Surround (422-RIS): Same as IS-3D Surround (422) with alternative algorithm * 3D Surround (423) or Incredible Virtual Surround: Dolby Pro Logic Surround reproduced by 3 speakers (L, C and R) * IS-3D Surround (423-IS): Same as 3D Surround (423) only with extra stereo width expander on left and right * RIS-3D Surround (423-RIS): Same as IS-3D Surround (423-IS) with alternative algorithm 1999 Aug 05 3 Philips Semiconductors Preliminary specification Sound effects DSP * Voice cancelling (karaoke): Rejects voice out of source material, mainly intended to be used with karaoke. Several karaoke modes available in stereo mode and in Dolby Pro Logic mode, such as (auto) voice cancel, (auto) centre voice cancel, (auto) multi left and (auto) multi right. * Microphone mix modes (karaoke): Mono microphone mixed to left, right and centre channel * Spectrum analysis: 3-band spectrum analyser is provided * Dolby B: Both a Dolby B encoder as well as a Dolby B decoder is implemented * 2 Room solution: In all modes not requiring more than 2 output channels (stereo and karaoke incredible surround) it is also possible to feed the source signal to the other 2 output channels (with same processed or not processed signal) * Dynamic Bass Enhancement (DBE): Dynamic bass enhancement generates a sub-woofer channel, which is either a separate output or is added to the front channels * Volume processing: Independent volume processing of all 4 output channels * AC-3/MPEG-2: Inputs available intended to be used with an AC-3/MPEG-2 co-processor. In this mode the SAA7712H can be used as post-processor. * Output redirection: Several output configurations are possible (normal 4 channel, special 4 + 2 channel, record 2 + 2 channel, 6 or 6 + 2 channel). Depending on the sample frequency several combinations of the above mentioned features are possible. 2 APPLICATIONS 3 GENERAL DESCRIPTION SAA7712H The SAA7712H provides for digital signal processing power in TV systems and home theatre systems. A DSP core is equipped with digital inputs and outputs, a 5-band parametric equalizer accelerator, a digital co-processor interface and a delay line memory. This architecture accommodates on-chip standard sound processing, incredible surround, Dolby Pro Logic Surround and other surround sound processing algorithms. The architecture also supports co-processing, e.g. to add to the processing power of the internal DSP core or for multi-channel surround decoding. All settings and parameters are controlled by an I2C-bus interface. The available interfaces support a high application flexibility. The DSP core communicates over 32 dedicated registers. The selected digital input is master for the data rate of the DSP core. This input can be selected among 2 slave I2S-bus inputs. The 4 outputs from the core are passed through 4 DACs and then routed to 4 output pins. Two master I2S-bus outputs and two master I2S-bus inputs can serve as an I2S-bus co-processor interface. Eight of the remaining registers are used for communication with the hardware equalizer, and eight for communication with the delay line memory. All I2S-bus inputs and outputs support the Philips I2S-bus format as well as 16, 18 and 20-bit LSB-justified formats. The SAA7712H can be used in TV sets with: * Dolby Pro Logic Surround, incredible surround, 3D Surround and advanced acoustics processing * Multi-channel sound decoding (AC-3 and MPEG-2) on a co-processor. The SAA7712H can be used for post-processing. 1999 Aug 05 4 Philips Semiconductors Preliminary specification Sound effects DSP 4 QUICK REFERENCE DATA SYMBOL VDD3V VDD5V IDDD3V IDDD5V PARAMETER supply voltage 3.3 V analog and digital supply voltage 5 V periphery DC supply current of the 3.3 V digital core part DC supply current of the 5 V digital periphery part CONDITION with respect to VSS with respect to VSS at fDSP18; maximum activity of the DSP at fDSP18; maximum activity of the DSP; VDD5 = 5 V at fDSP18; maximum activity of the DSP; VDD5 = 3.3 V IDDA Ptot DC supply current of the analog part total power dissipation at zero input and output signal at fDSP18; maximum activity of the DSP RL > 5 k; f = 1 kHz; A-weighted f = 1 kHz; -60 dB; A-weighted f = 20 Hz to 17 kHz; A-weighted fxtal = 16.384 MHz fxtal = 18.432 MHz 3 3 - - - - - - MIN. TYP. 3.3 3.3 or 5 - - - - - -75 SAA7712H MAX. 3.6 5.5 80 5 5 10 0.4 -60 V V UNIT mA mA mA mA W dBA (THD + N)/S DAC total harmonic distortion-plus-noise to output signal DRDAC DSDAC fxtal fDSP16 fDSP18 5 DAC dynamic range DAC digital silence crystal frequency DSP clock frequency DSP clock frequency 90 - 10.000 - - 96 -107 - - - - -102 19.456 32.256 32.544 dBA dBA MHz MHz MHz ORDERING INFORMATION TYPE NUMBER PACKAGE NAME QFP80 DESCRIPTION plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height VERSION SOT318-1 SAA7712H 1999 Aug 05 5 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... handbook, full pagewidth VDACP1 VDACN1 I2S_IO_BCK OSC_IN OSC_OUT I2S_IO_OUT1 I2S_IO_OUT2 RTCB DSP_OUT1 DSP_OUT2 DSP_IN1 DSP_IN2 TEST1 TEST2 TSCAN SHTCB DSP_RESET I2S_IO_WS I2S_IO_IN1 I2S_IO_IN2 EQOV 1999 Aug 05 SAA7712H 27 29 28 I2S-BUS INPUT SWITCH INCREDIBLE SURROUND (IS, RIS) DOLBY PRO LOGIC or DOLBY 3 STEREO or HALL/MATRIX CENTRE VOICE CANCELLING SURROUND CHANNEL DELAY from audio source 1 I2S_IN1_WS I2S_IN1_BCK I2S_IN1_DATA I2S_IN2_WS I2S_IN2_BCK I2S_IN2_DATA 3D SURROUND 24 26 25 IS-3D SURROUND from audio source 2 RIS-3D SURROUND 6 Philips Semiconductors Sound effects DSP BLOCK DIAGRAM VREFDA POM 15 8 18 2-CHANNEL 10-BAND EQUALIZER 19 17 16 VOLUME PROCESSING QUAD DAC 11 12 4-CHANNEL 5-BAND EQUALIZER 10 9 OUT0_I OUT0_V OUT1_I OUT1_V OUT2_I OUT2_V OUT3_I OUT3_V 6 SYS_CLK 21 OSCILLATOR AND PLL 62 63 47 48 HOST I/O TEST 44 I2C-BUS INTERFACE A0 31 32 30 33 36 37 60 59 58 20 40 41 38 39 57 76 77 46 SDA 45 SCL MGS206 Preliminary specification SAA7712H Fig.1 Block diagram. Philips Semiconductors Preliminary specification Sound effects DSP 7 PINNING INFORMATION SYMBOL n.c. n.c. n.c. n.c. n.c. n.c. n.c. POM OUT3_V OUT3_I OUT2_I OUT2_V VSSA2 VDDA2 VREFDA OUT1_V OUT1_I OUT0_I OUT0_V EQOV SYS_CLK VDDD5V1 VSSD5V1 I2S_IN2_WS I2S_IN2_DATA I2S_IN2_BCK I2S_IN1_WS I2S_IN1_DATA I2S_IN1_BCK I2S_IO_BCK I2S_IO_IN1 I2S_IO_IN2 I2S_IO_WS VDDD5V2 VSSD5V2 I2S_IO_OUT1 I2S_IO_OUT2 DSP_IN1 1999 Aug 05 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 not connected not connected not connected not connected not connected not connected not connected power-on mute; timing determined by external capacitor analog voltage output 3 analog current output 3 analog current output 2 analog voltage output 2 analog ground supply 2 analog supply voltage 2 (3 V) voltage reference of the analog part analog voltage output 1 analog current output 1 analog current output 0 analog voltage output 0 equalizer overflow line output test pin output digital supply voltage 1; peripheral cells only (3 or 5 V) digital ground supply 1; peripheral cells only (3 or 5 V) I2S-bus or LSB-justified format left-right data input from a digital audio source 2 I2S-bus clock or LSB-justified format input from a digital audio source 2 I2S-bus or LSB-justified format left-right data input from a digital audio source 1 I2S-bus clock or LSB-justified format input from a digital audio source 1 I2S-bus bit clock output for interface with DSP co-processor chip I2S-bus input data channel 1 from DSP co-processor chip I2S-bus input data channel 2 from DSP co-processor chip I2S-bus word select output for interface with DSP co-processor chip digital supply voltage 2; peripheral cells only (3 or 5 V) digital ground supply 2; peripheral cells only (3 or 5 V) I2S-bus output data channel 1 to DSP co-processor chip I2S-bus output data channel 2 to DSP co-processor chip digital input 1 of the DSP core (F0 of the status register) 7 DESCRIPTION SAA7712H PIN TYPE AP2D AP2D AP2D AP2D AP2D APVSS APVDD AP2D AP2D AP2D AP2D AP2D B4CR BT4CR VDD5 VSS5 IBUFD IBUFD IBUFD IBUFD BT4CR IBUFD IBUFD BT4CR VDD5 VSS5 BT4CR BT4CR IBUFD I2S-bus or LSB-justified format word select input from a digital audio source 2 IBUFD I2S-bus or LSB-justified format word select input from a digital audio source 1 IBUFD Philips Semiconductors Preliminary specification Sound effects DSP SAA7712H SYMBOL DSP_IN2 DSP_OUT1 DSP_OUT2 VDDD5V3 VSSD5V3 A0 SCL SDA TEST1 TEST2 VSSD3V1 VSSD3V2 VSSD3V3 VDDD3V1 VDDD3V2 VSSD3V4 VSSD3V5 VSSD3V6 DSP_RESET RTCB SHTCB TSCAN VSS_OSC OSC_IN OSC_OUT VDD_OSC n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. VDACP1 VDACN1 PIN 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 DESCRIPTION digital input 2 of the DSP-core (F1 of the status register) digital output 1 of the DSP-core (F2 of the status register) digital output 2 of the DSP-core (F3 of the status register) digital supply voltage 3; peripheral cells only (3 or 5 V) digital ground supply 3; peripheral cells only (3 or 5 V) I2C-bus slave subaddress selection input I2C-bus serial clock input I2C-bus serial data input/output test pin 1 test pin 2 digital ground supply 1 of 3 V core only digital ground supply 2 of 3 V core only digital ground supply 3 of 3 V core only digital supply voltage 1 of 3 V core only digital supply voltage 2 of 3 V core only digital ground supply 4 of 3 V core only digital ground supply 5 of 3 V core only digital ground supply 6 of 3 V core only reset (active LOW) asynchronous reset test control block (active LOW) shift clock test control block scan control ground supply crystal oscillator circuit crystal oscillator input; crystal oscillator sense for gain control or forced input in slave mode crystal oscillator output; drive output to 11.2896 MHz crystal 3 V supply voltage crystal oscillator circuit not connected not connected not connected not connected not connected not connected not connected not connected not connected not connected not connected not used not used PIN TYPE IBUFD B4CR B4CR VDD5 VSS5 IBUFD SCHMITCD BD4SCI4 BD4CR BT4CR VSS3S VSS3S VSS3S VDD3 VDD3 VSS3S VSS3S VSS3S IBUFU IBUFD IBUFD IBUFD VSS3S OSC OSC VDD3 1999 Aug 05 8 Philips Semiconductors Preliminary specification Sound effects DSP SAA7712H SYMBOL n.c. n.c. n.c. Table 1 PIN 78 79 80 not connected not connected not connected DESCRIPTION PIN TYPE Pin types PIN DESCRIPTION 4 mA slew rate controlled digital output 4 mA slew rate controlled digital I/O 4 mA slew rate controlled digital I/O with pull-down resistor 4 mA slew rate controlled 3-state digital output digital input digital input with pull-up resistor digital input with pull-down resistor I2C-bus input/output with open-drain NMOS 4 mA output Schmitt trigger input analog input/output analog input/output 5 V VDD internal 3 V VDD internal 3 or 5 V VSS internal substrate 5 V VSS external analog VDD analog VSS PIN NAME B4CR BD4CR BD4CRD BT4CR IBUF IBUFU IBUFD BD4SCI4 SCHMITCD AP2D OSC VDD5 VDD3 VSS3S VSS5 APVDD APVSS 1999 Aug 05 9 Philips Semiconductors Preliminary specification Sound effects DSP SAA7712H 77 VDACN1 handbook, full pagewidth 76 VDACP1 75 n.c. 74 n.c. 73 n.c. 72 n.c. 71 n.c. 70 n.c. 69 n.c. 68 n.c. 67 n.c. 66 n.c. 65 n.c. 64 VDD_OSC 63 OSC_OUT 62 OSC_IN 61 VSS_OSC 60 TSCAN 59 SHTCB 58 RTCB 57 DSP_RESET 56 VSSD3V6 55 VSSD3V5 54 VSSD3V4 53 VDDD3V2 52 VDDD3V1 51 VSSD3V3 50 VSSD3V2 49 VSSD3V1 48 TEST2 47 TEST1 46 SDA 45 SCL 44 A0 43 VSSD5V3 42 VDDD5V3 41 DSP_OUT2 DSP_OUT1 40 80 n.c. 79 n.c. n.c. n.c. n.c. 1 2 3 n.c. 4 n.c. n.c. n.c. POM OUT3_V 5 6 7 8 9 OUT3_I 10 OUT2_I 11 OUT2_V 12 78 n.c. SAA7712H VSSA2 13 VDDA2 14 VREFDA 15 OUT1_V 16 OUT1_I 17 OUT0_I 18 OUT0_V 19 EQOV 20 SYS_CLK 21 VDDD5V1 22 VSSD5V1 23 I2S_IN2_WS 24 I2S_IN2_DATA 25 I2S_IN2_BCK 26 I2S_IN1_WS 27 I2S_IN1_DATA 28 I2S_IN1_BCK 29 I2S_IO_BCK 30 I2S_IO_IN1 31 I2S_IO_IN2 32 I2S_IO_WS 33 VDDD5V2 34 VSSD5V2 35 I2S_IO_OUT1 36 I2S_IO_OUT2 37 DSP_IN1 38 DSP_IN2 39 MGS207 Fig.2 Pin configuration. 1999 Aug 05 10 Philips Semiconductors Preliminary specification Sound effects DSP 8 8.1 8.1.1 FUNCTIONAL DESCRIPTION Analog outputs ANALOG OUTPUT CIRCUIT 8.1.3 DACS SAA7712H Each of the four low noise high dynamic range DACs consists of a signed-magnitude DAC with current output, followed by a buffer operational amplifier. 8.1.4 UPSAMPLE FILTER Depending on the configuration of the equalizer sections, the SAA7712H has 2 or 4 analog outputs which are supplied by the same power supply. Each of these outputs has a voltage and a current pin (see Fig.3). The signals are available on 2 outputs (OUT0 and OUT1), or 4 outputs (OUT0, OUT1, OUT2 and OUT3). To reduce spectral components above the audio band, a fixed 4 times oversampling and interpolating digital filter is used. The filters give an out-of-audio-band attenuation of at least 29 dB. The filter is followed by a first-order noise shaper to expand the dynamic range to more than 105 dB. The band around multiples of the sample frequency of the DAC (4fs) is not affected by the digital filter. A capacitor must be added in parallel with the DAC output amplifier to attenuate this out-of-band noise further to an acceptable level. In Fig.4 the overall frequency spectrum at the DAC audio output without external capacitor or low-pass filter for the audio sampling frequencies of 38 kHz is shown. In Fig.5 the detailed spectrum around fs is shown for an fs of 38, 44.1 and 48 kHz. The pass band bandwidth (-3 dB) is 1 f . 2s handbook, halfpage OUT0_I (OUT1_I) MSB BIT 0 to 13 DAC MGS208 OUT0_V (OUT1_V) Vref Fig.3 Analog output circuit. 8.1.2 DAC FREQUENCY The sample rate (fs) of the selected source is the frame rate of the DSP. The word clock for the upsample filter and the clock for the DACs, at 4fs, are derived internally from the word select of the selected audio source. 1999 Aug 05 11 Philips Semiconductors Preliminary specification Sound effects DSP SAA7712H MGS209 handbook, full pagewidth (dB) 0 -10 -20 -30 -40 -50 -60 0 100 200 300 400 fs = 38000 Hz f (kHz) 500 Fig.4 Overall frequency spectrum audio output. handbook, full pagewidth 0 MGS210 (dB) -10 -20 -30 -40 -50 0 0 0 10000 11605 12632 20000 23211 25263 30000 34816 37895 fs = 38000 Hz fs = 44100 Hz fs = 48000 Hz f (Hz) Fig.5 Detailed frequency spectrum audio output. 1999 Aug 05 12 Philips Semiconductors Preliminary specification Sound effects DSP 8.1.5 PERFORMANCE 8.1.6 POWER-ON MUTE (POM) SAA7712H The signed-magnitude noise-shaped DAC has a dynamic range in excess of 100 dB. The signal-to-noise ratio of the audio output at full-scale is determined by the word length of the converter. The noise at low outputs is fully determined by the noise performance of the DAC. Since it is a signed-magnitude type, the noise at digital silence is also low. As a disadvantage, the total THD is higher than conventional DACs. The typical total harmonic distortion-plus-noise to signal ratio as a function of the output level is shown in Fig.6. To avoid any uncontrolled noise at the audio outputs after power-on of the IC, the reference current source of the DAC is switched off. The capacitor on pin POM determines the time after which this current has a soft switch-on. So at power-on the current audio signal outputs are always muted. The loading of the external capacitor is done in two stages via two different current sources. The loading starts at a current level that is 9 times lower than the current loading after the voltage on pin POM has passed the 1 V level. This results in an almost dB linear behaviour. 8.1.7 POWER-OFF PLOP SUPPRESSION handbook, halfpage -20 MGS211 (THD + N)/S (dB) -40 Power should still be provided to the analog part of the DAC, while the digital part is switching off. As a result, the output voltage will decrease gradually allowing the power amplifier some extra time to switch-off without audible plops. If a 5 V power supply is present, the supply voltage of the analog part of the DAC can be fed from the 5 V power supply via a 1.8 V zener diode. A capacitor, connected to the 3.3 V power supply, provides power to the analog part when the 5 V power supply is switching off fast. -60 -80 -80 -60 -40 -20 output level (dB) 0 Fig.6 Typical (THD + N)/S curve as a function of the output level. 1999 Aug 05 13 Philips Semiconductors Preliminary specification Sound effects DSP 8.1.8 PIN VREFDA 8.2 8.2.1 I2S-bus inputs and outputs SAA7712H With two internal resistors half the supply voltage (VDDA2) is obtained and coupled to an internal buffer. This reference voltage is used as DC voltage for the output operational amplifiers and as reference for the DAC. In order to obtain the lowest noise and to have the best ripple rejection, a filter capacitor has to be added between this pin and ground. 8.1.9 INTERNAL DAC CURRENT REFERENCE DIGITAL DATA STREAM FORMATS For communication with external digital sources a serial 3-line bus is used. This I2S-bus has one line for data, one line for clock and one line for the word select. See Fig.7 for the general waveform formats of the four possible formats. The serial digital inputs (and outputs) of the SAA7712H are capable of handling multiple formats: Philips I2S-bus and LSB-justified formats of 16, 18 and 20 bits word sizes. In Philips I2S-bus format, the number of bit clock (BCK) pulses may vary in the application. When the transmitter word length is smaller than the receiver word length, the receiver will fill in zeroes at the LSB side. When the transmitter word length exceeds the receiver word length, the LSBs are skipped. For correct operation of the DACs, there should be a minimum of 16 bit clocks per word select. In the LSB-justified formats, the transmitter and receiver must be set to the same format. Be aware that a format switch between 20, 18 and 16 bits LSB-justified formats is done by changing the relative timing of the word select edges. The data bits remain unchanged. In the 20 bits format, the 2 LSBs are zeroes. In the 16 bits format, the 2 data bits following the word select edge are not zero, but undefined. In fact, these are the LSBs of the 18-bit word. The timing specification for the waveforms of the serial digital inputs and outputs are given in Fig.17. As a reference for the internal DAC current and for the DAC current source output, a current is drawn from the level on pin VREFDA to pin VSSA2 (ground) via an internal resistor. The absolute value of this resistor also determines the absolute current of the DAC. This means that the absolute value of the current is not that fixed due to the spread of the current reference resistor value. This, however, does not influence the absolute output voltages because these voltages are also derived from a conversion of the DAC current to the actual output voltage via internal resistors. 8.1.10 SUPPLY OF THE ANALOG OUTPUTS All the analog circuitry of the DACs and the operational amplifiers are fed by 2 supply pins, VDDA2 and VSSA2. Pin VDDA2 must have sufficient decoupling to prevent THD degradation and to ensure a good power supply rejection ratio. The digital part of the DAC is fully supplied from the chip core supply. 1999 Aug 05 14 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 Aug 05 WS 1 BCK DATA MSB B2 MSB B2 INPUT FORMAT I2 S-BUS MSB 2 LEFT 3 1 2 RIGHT 3 WS LEFT 16 BCK DATA MSB B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS MSB B2 B15 LSB 15 2 1 RIGHT 16 15 2 1 Philips Semiconductors Sound effects DSP Fig.7 All serial data I/O formats. handbook, full pagewidth 15 WS LEFT 18 BCK DATA MSB B2 B3 B4 B17 LSB MSB B2 B3 B4 B17 LSB 17 16 15 2 1 18 RIGHT 17 16 15 2 1 LSB-JUSTIFIED FORMAT 18 BITS WS 20 BCK 19 LEFT 18 17 16 15 2 1 20 19 18 RIGHT 17 16 15 2 1 Preliminary specification DATA MSB B2 B3 B4 B5 B6 B19 LSB MSB B2 B3 B4 B5 B6 B19 LSB MGS212 SAA7712H LSB-JUSTIFIED FORMAT 20 BITS Philips Semiconductors Preliminary specification Sound effects DSP 8.2.2 SLAVE I2S-BUS INPUTS Table 3 SAA7712H I2C-bus audio_source mode bit (0FF9H, see Table 13) OUTPUT I2S_IN1 (default) I2S_IN2 The SAA7712H has two slave I2S-bus inputs, I2S_IN1 and I2S_IN2 with respective data lines I2S_IN1_DATA and I2S_IN2_DATA, word select lines I2S_IN1_WS and I2S_IN2_WS and bit clock lines I2S_IN1_BCK and I2S_IN2_BCK. The external source is master and supplies the bit clock and word select. The I2C-bus bits audio_format(2 to 0) allow for selection of the desired I2S-bus format (see Table 13). The bits, needed for selecting a certain format, are explained in Table 2. The input circuitry is limited in handling the number of BCK pulses per WS period. If the word rate of the selected digital input source is fs, the bit clock must be a continuous clock in the range of 16fs fbit(CLK) 256fs. The minimum limit of the audio sample frequency is determined by 1 f 18 SCL. The maximum limit of the audio sample frequency is determined by DSP_clock/481 Hz. Table 2 I2C-bus audio_format mode bits (0FF9H, see Table 13) OUTPUT BIT 9 0 - - - 1 BIT 8 0 0 1 1 0 BIT 7 0 1 0 1 0 internal format (for test purposes only) LSB-justified, 16 bits LSB-justified, 18 bits LSB-justified, 20 bits standard I2S-bus (default) AUDIO_SOURCE Bit 5 0 1 8.2.3 MASTER I2S-BUS INPUTS AND OUTPUTS For the co-processor I/O interface, the SAA7712H acts as a master. The SAA7712H supplies both the bit clock and word select. The I2C-bus bits host_io_format(1 and 0) allow for selection of the desired I2S-bus format (see Table 13). The bits needed for selecting a certain format are given in Table 4. All I2S-bus output lines, I2S_IO_WS, I2S_IO_BCK, I2S_IO_OUT1 and I2S_IO_OUT2, can be 3-stated with I2C-bus bit en_host_io (see Table 13). The word select and bit clock of the co-processor I/O interface are derived from the word select and bit clock of the audio source selected according to Table 3. The incoming bit clock can be divided by 1, 2, 4 or 8 depending on the needs of an external connected co-processor. These selections can be done with I2C-bus bits cloop_mode(2 to 0) (see Table 13). The meaning of these bits is shown in Table 5. AUDIO_FORMAT The selection of the DSP input among the decimated analog input and the I2S-bus inputs I2S_IN1 and I2S_IN2 is controlled with I2C-bus bit audio_source (see Table 13). The meaning of this bit can be found in Table 3. 1999 Aug 05 16 Philips Semiconductors Preliminary specification Sound effects DSP Table 4 I2C-bus host_io_format bits (0FF9H, see Table 13) HOST_IO_FORMAT OUTPUT BIT 11 0 0 1 1 Table 5 BIT 10 0 1 0 1 standard I2S-bus (default) LSB-justified format, 16 bits LSB-justified format, 18 bits LSB-justified format, 20 bits SAA7712H I2C-bus cloop_mode bits (0FF9H, see Table 13) CLOOP_MODE OUTPUT BIT 15 0 1 - - - - BIT 14 - - 0 0 1 1 BIT 13 - - 0 1 0 1 bypass WS (default) WS 50% duty factor bypass BCLK (default) divide BCLK by 2 divide BCLK by 4 divide BCLK by 8 If the gain setting causes the audio signal to exceed the maximum level in one of the filter sections, the signal will be clipped and the equalizer overflow output (pin EQOV) will be set HIGH until the end of the next audio sample period. 8.3.2 CONFIGURATION OF EQUALIZER SECTIONS 8.3 8.3.1 Equalizer accelerator INTRODUCTION The equalizer accelerator is a hardware accelerator to the DSP core. Both its inputs and outputs are stored in registers of the DSP core. The equalizer cannot be used and cannot be programmed if no word select and bit clock signal are present on a selected digital source input; see audio_source bit in Table 3 (I2S_IN1 or I2S_IN2). The minimum required DSP_clock is 481fs. The equalizer accelerator contains one second-order filter data path that is 20 times multiplexed. With this circuit, a 2-channel equalizer of 10 second-order sections per channel or a 4-channel equalizer of 5 second-order sections per channel can be realised. The centre frequency, gain and Q-factor of all 20 second-order sections can be set independently from each other. Every section is followed by a selectable attenuation of 0 or 6 dB. Per section, 4 bytes of the I2C-bus register are needed to store the settings. The equalizer settings can be updated during normal operation. An application program supports the programming of the equalizer. The equalizer accelerator can make a 2-channel equalizer of 10 second-order sections per channel or a 4-channel equalizer of 5 second-order sections per channel. The sections of one channel can be chained one after the other. Depending on the I2C-bus control bit two_four (see Table 11), the 20 filter sections are combined for the appropriate configuration, as illustrated in Fig.8. 1999 Aug 05 17 Philips Semiconductors Preliminary specification Sound effects DSP SAA7712H handbook, full pagewidth 1 A IN0 2 3 4 5 OUT0 2 channel B IN1 2 channel OUT1 C IN2 OUT2 D IN3 MGS213 OUT3 Fig.8 Configurations of the equalizer sections. 8.3.3 OVERFLOW DETECTION The equalizer has an overflow flag. This flag is fed to output pin EQOV. If an overflow is detected in one of the filter sections, the signal is clipped to the maximum allowed level. The overflow flag is immediately set. It remains at a HIGH-level during the remaining part of the current audio sample period and for the whole next sample period. If no overflow is detected during this next sample period, the overflow flag goes to a LOW-level at the beginning of the sample period after that. Otherwise, the overflow flag remains at a HIGH-level for at least one other audio sample period. 8.4 8.4.1 Clock circuit and oscillator GENERAL DESCRIPTION The gain of the oscillator is internally controlled by the AGC block. A sine wave with a peak-to-peak voltage close to the oscillator power supply voltage is generated. The AGC block prevents clipping of the sine wave and therefore the higher harmonics are as low as possible. At the same time, the voltage of the sine wave is as high as possible so reducing the jitter going from sine wave to clock signal. The sinusoidal output is converted into a CMOS compatible clock by the comparator. The second mode of operation shown in Fig.10, is the slave mode which is driven by a master clock directly. The signal to pin OSC_IN can be driven to the power supply voltages VDD_OSC and VSS_OSC. 8.4.2 SUPPLY OF THE CRYSTAL OSCILLATOR The chip has a crystal clock oscillator. It can use a crystal at either fxtal = 16.384 MHz = 512 x 32 kHz or fxtal = 18.432 MHz = 576 x 32 kHz in fundamental mode. The block diagram of this Pierce oscillator is shown in Fig.9. The active element needed to compensate for the loss resistance of the crystal is the block Gm. This block is placed between the external pins OSC_IN and OSC_OUT. The power supply connections of the oscillator are separate from the other supply lines. This is to minimize the feedback from the ground bounce of the chip to the oscillator circuit. Pin VSS_OSC is used as the ground supply and pin VDD_OSC as the positive supply. 1999 Aug 05 18 Philips Semiconductors Preliminary specification Sound effects DSP SAA7712H handbook, full pagewidth 0.5VDD_OSC AGC Gm clock out 100 k on chip 62 OSC_IN off chip R bias 63 OSC_OUT 64 VDD_OSC 61 VSS_OSC MGS214 C1 10 pF C2 10 pF Fig.9 Block diagram of the crystal oscillator circuit. handbook, full pagewidth 0.5VDD_OSC AGC Gm clock out 100 k on chip 62 OSC_IN off chip Rbias 63 OSC_OUT 64 VDD_OSC 61 VSS_OSC MGS215 C3 5 pF C1 10 pF slave input C2 10 pF Fig.10 Block diagram of the oscillator in slave mode. 1999 Aug 05 19 Philips Semiconductors Preliminary specification Sound effects DSP 8.5 Programmable phase-locked loop circuit SAA7712H The clock of the DSP is generated with a programmable PLL. To select the required DSP clock see Table 6. The N factor (ranging from 93 to 181) can be selected with I2C-bus bits PLL_div(14 to 11), see Table 10. Depending on the crystal and the required DSP clock the I2C-bus bits pll_fs_sel and bits dsp_turbo must be set. The maximum limit of the audio sample frequency is determined by DSP_clock/481 Hz. Table 6 I2C-bus bits PLL_div and dividing factors N of the programmable DSP clock DSP CLOCK FREQUENCY (MHz) PLL_DIV(14 to 11) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Notes 1. fxtal = 16.384 MHz; pll_fs_sel = 1 and dsp_turbo = 1, see Table 11. 2. fxtal = 18.432 MHz; pll_fs_sel = 1 and dsp_turbo = 1, see Table 11. 3. Usable frequency. N 93 (default) 99 106 113 121 126 132 137 143 148 154 159 165 170 176 181 TDA9875(1) 23.808(3) 25.344(3) 27.136 28.928 30.976 32.256 33.792(3) 35.072(3) 36.608(3) 37.888(3) 39.424(3) 40.704(3) 42.240(3) 43.520(3) 45.056(3) 46.336(3) MSP3410D(2) 26.784 28.512 30.528 32.544 34.848(3) 36.288(3) 38.016(3) 39.456(3) 41.184(3) 42.624(3) 44.352(3) 45.792(3) 47.520(3) 48.960(3) 50.688(3) 52.128(3) 1999 Aug 05 20 Philips Semiconductors Preliminary specification Sound effects DSP 8.6 8.6.1 I2C-bus control INTRODUCTION 8.6.2 SAA7712H CHARACTERISTICS OF THE I2C-BUS A general description of the I2C-bus format can be obtained from Philips Semiconductors, International Marketing and Sales Communications (IMSC). For the external control of the SAA7712H a fast I2C-bus is implemented. This is a 400 kHz bus which is downward compatible with the standard 100 kHz bus. There are different types of control instructions: * Instructions to control the DSP program, program the coefficient RAM and read the values of parameters * Instructions to control the equalizer, program the equalizer coefficient RAM to be able to change the centre frequency, gain and Q-factor of the equalizer sections * Instructions to control the source selection and programmable parts, e.g. PLL clock speed. The detailed description of the I2C-bus and commands is given in the following sections. The description of the different bits in the memory map is given in Section 9.6. The equalizer cannot be used and cannot be programmed if there is no word select and bit clock signal present on a selected digital source input; see audio_source bit in Table 3 (I2S_IN1 and I2S_IN2). The minimum limit of the audio sample frequency is determined by 118fSCL. The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to VDD via a pull-up resistor when connected to the output stages of a microcontroller. For a 400 kHz I2C-bus the recommendation from Philips Semiconductors must be followed (e.g. up to loads of 200 pF on the bus a pull-up resistor can be used, between 200 to 400 pF a current source or switched resistor must be used). Data transfer can only be initiated when the bus is not busy. 8.6.3 BIT TRANSFER One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Fig.11). The maximum clock frequency is 400 kHz. To be able to run on this high frequency all the inputs and outputs connected to this bus must be designed for this high speed I2C-bus according to the Philips specification. handbook, full pagewidth SDA SCL data line stable; data valid change of data allowed MGS216 Fig.11 Bit transfer on the I2C-bus. 1999 Aug 05 21 Philips Semiconductors Preliminary specification Sound effects DSP 8.6.4 START AND STOP CONDITIONS SAA7712H Both data and clock lines will remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as a START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as a STOP condition (P) (see Fig.12). handbook, full pagewidth SDA SCL S START condition P STOP condition MGS217 Fig.12 START and STOP conditions. 8.6.5 DATA TRANSFER A device generating a message is a `transmitter' and a device receiving a message is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves'. handbook, full pagewidth SDA MSB acknowledgement signal from receiver byte complete interrupt within receiver clock line held LOW while interrupts are serviced SCL S START condition 1 2 7 8 9 ACK 1 2 3 to 8 9 ACK MGS218 acknowledgement signal from receiver Fig.13 Data transfer on the I2C-bus. 1999 Aug 05 22 Philips Semiconductors Preliminary specification Sound effects DSP 8.6.6 ACKNOWLEDGE SAA7712H Set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition (see Fig.14). 8.6.7 STATE OF THE I2C-BUS INTERFACE DURING AND AFTER POWER-ON RESET The number of data bits transferred between the START and STOP conditions from the transmitter to the receiver is not limited. Each byte of eight bits is followed by one acknowledge bit (see Fig.13). The acknowledge bit is a HIGH-level left on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line (left HIGH by the transmitter) during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. During reset (see Section 8.8), the internal SDA line is kept HIGH and pin SDA is therefore high-impedance. The SDA line remains HIGH until a master pulls it down to initiate communication. handbook, full pagewidth data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition 1 2 7 8 9 MGS219 clock pulse for acknowledgement Fig.14 Acknowledge on the I2C-bus. 1999 Aug 05 23 Philips Semiconductors Preliminary specification Sound effects DSP 8.7 External control pins SAA7712H A more or less fixed relationship between the DSP_RESET time constant and the POM time constant is obligatory. The voltage on pin POM determines the current flowing in the DACs. For 0 V on pin POM, the DAC currents are zero and so also the DACs output voltages. When a 3 V supply voltage (VDDA2) is supplied to pin POM, the DAC currents are at their nominal (maximum) value. Long before the DAC outputs get their nominal output voltages, the DSP must be in normal operating mode to reset the output register. Therefore, the time constant of DSP_RESET must be shorter than the time constant of POM. For advised capacitors see the application diagram. The reset has the following function: * All I2C-bus registers are reset to their default values * The DSP algorithm is re-started * The external control output pins are reset (see Section 8.7) * Pin SDA is high-impedance. When the level on the reset pin is HIGH, the DSP algorithm starts to run. In addition to the reset pin, there is also a software reset; bit PC_reset (bit 15, 0FFDH, see Table 11). This reset has the following function: * The DSP algorithm is re-started * The external control output pins are reset (see Section 8.7). For external control two input pins are implemented. The status of these pins can be changed by applying a logic level. The status of these pins is recorded in the internal status register. The function of each input pin is determined by the DSP software. Pin DSP_IN1: * Logic 0 or left open-circuit means volume coefficients updates are possible (default) * Logic 1 means no updates of volume coefficients are possible. Pin DSP_IN2: * If the 3-band spectrum analyser is used: - Logic 1 will reset the band registers of the analyser - Logic 0 or left open-circuit means no reset of the band registers will be done (default). * If the 3-band spectrum analyser is not used: - The state of pin DSP_IN2 can be read via an I2C-bus command. To control external devices two output pins are implemented. The status of these pins is controlled by the DSP program. The functions of these pins are determined by the DSP software. Pin DSP_OUT1: * To drive pin DSP_OUT1 via an I2C-bus command. Pin DSP_OUT2: * To drive pin DSP_OUT2 via an I2C-bus command. 8.8 Reset pin The reset signal on pin DSP_RESET is active LOW and has an internal pull-up resistor. Between this pin and ground a capacitor should be connected to allow a proper switch-on of the supply voltage. The capacitor value is such that the chip is in the reset state as long as the power supply is not stabilized. 1999 Aug 05 24 Philips Semiconductors Preliminary specification Sound effects DSP 8.9 Power supply connection and EMC 9.3 Write cycles I2C-bus SAA7712H The digital part of the chip has in total 5 positive supply line connections and 8 ground connections. To minimise radiation the chip should be put on a double layer PCB with a large ground plane on one side. The ground supply lines should have a short connection to this ground plane. A coil and capacitor network in the positive supply line can be used as high frequency filter. 8.10 Test mode connections configuration for a write cycle is shown in The Fig.15. The write cycle is used to write the bytes to control the PLL for the DSP clock generation, the format of the I2S-bus and some other settings. More details can be found in the I2C-bus memory map (see Table 8). The data length is 2 or 3 bytes, depending on the accessed memory. The slave receiver detects the address and adjusts the number of bytes accordingly. For XRAM, the data word length is 18 bits and 3 bytes are sent over the I2C-bus. The upper 6 bits (i.e. bit 7 to bit 2) of the first byte DATA H are don't care. For YRAM, the data word length is 12 bits and 2 bytes are sent over the I2C-bus. The left nibble (i.e. bit 7 to bit 4) of the first byte DATA H is don't care. 9.4 Read cycles I2C-bus Pins TSCAN, RTCB and SHTCB are used to put the chip in test mode and to test the internal connections. Each pin has an internal pull-down resistor to ground. In the application these pins can be left open-circuit or connected to ground. 9 9.1 I2C-BUS FORMAT Addressing Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always done with the first byte transmitted after the START procedure. 9.2 Slave address (pin A0) The SAA7712H acts as a slave receiver or a slave transmitter. Therefore, the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. The slave address is shown in Table 7. Table 7 MSB 0 0 1 1 1 1 A0 Slave address LSB R/W configuration for a read cycle is shown in The Fig.16. The read cycle is used to read the data values from XRAM or YRAM. The master starts with a START condition (S), the SAA7712H address `0011110' and a logic 0 (write) for the read/write bit. This is followed by an acknowledge of the SAA7712H. The master then writes the memory high address and memory low address where the reading of the memory content of the SAA7712H must start. The SAA7712H acknowledges these addresses both. The master than generates a repeated START and again the SAA7712H address `0011110' but this time followed by a logic 1 (read) of the read/write bit. From this moment on, the SAA7712H will send the memory content in groups of 2 (YRAM) or 3 (XRAM) bytes to the I2C-bus, each time acknowledged by the master. The master stops this cycle by generating a negative acknowledge, then the SAA7712H frees the I2C-bus and the master can generate a STOP condition (P). The subaddress bit A0 corresponds to the hardware address pin A0 which allows the device to have two addresses. This allows the control of two SAA7712Hs via the same I2C-bus. 1999 Aug 05 25 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 Aug 05 A Philips Semiconductors Sound effects DSP S00111000C K ADDR H A C K ADDR L A C K DATA H A C K DATA M A C K DATA L A CP K auto increment if repeated n-groups of 3 (2) bytes address R/W MGD568 S = START condition. ACK = acknowledge from DSP (SDA LOW). ADDR H and ADDR L = address DSP register. DATA H, DATA M and DATA L = data of XRAM or registers. DATA H and DATA M = data of YRAM. P = STOP condition. Fig.15 Master transmitter writes to the DSP registers. 26 A S00111000C K ADDR H A C K ADDR L A A CS00111001C K K DATA H A C K DATA M A C K DATA L A CP K auto increment if repeated n-groups of 3 (2) bytes address R/W R/W MGA808 - 1 Preliminary specification S = START condition. ACK = acknowledge from DSP (SDA LOW). ADDR H and ADDR L = address DSP register. DATA H, DATA M and DATA L = data of XRAM or registers. DATA H and DATA M = data of YRAM. P = STOP condition. SAA7712H Fig.16 Master transmitter reads from the DSP registers. Philips Semiconductors Preliminary specification Sound effects DSP 9.5 I2C-bus memory map summary SAA7712H The I2C-bus memory map contains all defined I2C-bus bits. The map is split into two different sections: hardware memory registers and the RAM definitions. The preliminary memory map is given in Table 8. Table 8 I2C-bus memory map FUNCTION various settings (see Table 9) equalizer YRAM XRAM 4 x 16 bits 40 x 16 bits 384 x 12 bits 384 x 18 bits SIZE SUBADDRESSES 0FF9H to 0FFFH 0F80H to 0FA7H 0800H to 097FH 0000H to 017FH Table 9 I2C-bus memory map: overview of various settings REGISTER NAME SUBADDRESS 0FFFH (see Table 10) 0FFDH (see Table 11) 0FFAH (see Table 12) 0FF9H (see Table 13) I2C_DCS_CTR I2C_ADDA I2C_SEL I2C_HOST 9.6 I2C-bus memory map details Table 10 I2C_DCS_CTR register (0FFFH) NAME - loopo_on_off PLL_div - SIZE (BITS) 10 1 4 1 reserved pin SYS_CLK output enable: on (logic 1) or off (logic 0) off PLL clock division factor for DSP_clock (see Table 6) reserved 93 DESCRIPTION DEFAULT BIT POSITION 9 to 0 10 14 to 11 15 1999 Aug 05 27 Philips Semiconductors Preliminary specification Sound effects DSP Table 11 I2C_ADDA register (0FFDH) NAME - pll_fs_sel dsp_turbo two_four - pc_reset SIZE (BITS) 10 1 1 1 2 1 reserved divide oscillator by 2 (logic 1) double DSP_clock (logic 1) 2-channel 10-band (logic 1) or 4-channel 5-band (logic 0) equalizer configuration reserved re-start DSP algorithm (logic 1) or DSP running (logic 0) DSP running division doubling 4-channel 5-band DESCRIPTION DEFAULT SAA7712H BIT POSITION 9 to 0 10 11 12 14 and 13 15 Table 12 I2C_SEL register (0FFAH) NAME - bypass_pll - inv_host_ws - SIZE (BITS) 8 1 4 1 2 reserved bypass PLL used for DSP_clock (logic 1) or use PLL for DSP_clock (logic 0) reserved inverting (logic 1) or non-inverting (logic 0) word select reserved non-inverting use PLL DESCRIPTION DEFAULT BIT POSITION 7 to 0 8 12 to 9 13 15 and 14 Table 13 I2C_HOST register (0FF9H) NAME - audio_source - audio_format host_io_format en_host_io cloop_mode SIZE (BITS) 5 1 1 3 2 1 3 reserved input source is reserved format of selected input source (see Table 2) host input/output data format (see Table 4) enable (logic 1) or disable (logic 0) co-processor cloop mode (see Table 5) I2S-bus standard standard disable bypass WS I2S-bus I2S-bus I2S_IN1 or I2S_IN2 (see Table 3) I2S_IN1 DESCRIPTION DEFAULT BIT POSITION 4 to 0 5 6 9 to 7 11 and 10 12 15 to 13 1999 Aug 05 28 Philips Semiconductors Preliminary specification Sound effects DSP 10 LIMITING VALUES In accordance with the Absolute Maximum Ratings system (IEC 134). SYMBOL VDD3V VDD5V VDD IIK IO(sink/source) IDD,ISS Tamb Tstg Ves Ilu(prot) P/out Ptot Notes 1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k resistor. PARAMETER supply voltage 3.3 V analog and digital supply voltage 5 V periphery voltage difference between two VDDx pins input clamping diode current output sink or source current, output type 4 mA VDD or VSS current per supply pin ambient temperature storage temperature electrostatic handling voltage for note 1 all pins note 2 latch-up protection power dissipation per output total power dissipation CIC specification/test method Vi < -0.5 V or Vi > VDD + 0.5 V -0.5 V < Vo < VDD + 0.5 V only valid for the voltages in connection with the 5 V I/Os CONDITION MIN. -0.5 -0.5 - - - - 0 -65 -3000 -300 100 - - SAA7712H MAX. +5 +6.5 550 10 20 750 70 +150 +3000 +300 - 100 400 V V UNIT mV mA mA mA C C V V mA mW mW 2. Machine model: equivalent to discharging a 200 pF capacitor through a 2.5 H inductance and a 0 series resistor. 11 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) Note 1. Printed-circuit board mounting. PARAMETER thermal resistance from junction to ambient CONDITION in free air; note 1 VALUE 45 UNIT K/W 1999 Aug 05 29 Philips Semiconductors Preliminary specification Sound effects DSP SAA7712H 12 DC CHARACTERISTICS Digital I/O at Tamb = 0 to 70 C; VDD5V = 4.5 to 5.5 V; VDD3V = 3 to 3.6 V; unless otherwise specified. SYMBOL Supplies VDD3V VDD5V IDDD3V IDDD5V IDAC IDD_OSC Ptot Logic VIH HIGH-level input voltage of all digital inputs and I/Os on pins 24 to 29, 38, 39, 44 to 47, 57 to 60 LOW-level input voltage of all digital inputs and I/Os on pins 24 to 29, 38, 39, 44 to 47, 57 to 60 hysteresis voltage on pin 45 (SCL) HIGH-level output voltage of IO = -4 mA digital outputs on pins 20, 21, 30, 33, 36, 37, 40, 41, 47, 48 LOW-level output voltage of VDDD5V = 4.5 V; IO = 4 mA digital outputs on pins 20, 21, VDDD5V = 3.0 V; IO = 4 mA 30, 33, 36, 37, 40, 41, 47, 48 LOW-level output voltage of digital I2C-bus data output on pin 46 (SDA) output leakage current 3-state outputs on pins 21, 30, 33, 36, 37, 46 to 48 internal pull-up resistance to VDDD on pin 57 (DSP_RESET) IO = 4 mA 0.7VDDD5V - - V supply voltage 3.3 V analog and digital supply voltage 5 V periphery supply current of the 3.3 V digital core part supply current of the 5 V digital periphery part supply current of the DACs supply current of the crystal oscillator total power dissipation all VDD pins of the type VDD3 3 and APVVD referenced to VSS all VDD pins of the type VDD5 referenced to VSS at fDSP18; maximum activity of the DSP at fDSP18; maximum activity of the DSP at fDSP18; functional mode at fDSP18; maximum activity of the DSP 4.5 3.0 - - 3.3 5 3.3 33 2 4 3.5 135 3.6 5.5 3.6 80 5 7 3 400 V V V mA mA mA mA mW PARAMETER CONDITIONS MIN. TYP. MAX. UNIT at zero input and output signal - - - VIL - - 0.3VDDD5V V Vhys VOH 1 1.3 - - V V VDDD5V - 0.4 - VOL - - - - - - 0.4 0.4 0.4 V V V VOL(I2C) IO VO = 0 or VDD - - 5 A Rpu 23 50 80 k 1999 Aug 05 30 Philips Semiconductors Preliminary specification Sound effects DSP SAA7712H SYMBOL Rpd PARAMETER internal pull-down resistance to VSSD on pins 24 to 29, 38, 39, 44, 58 to 60 input rise and fall times output rise time on pins 20, 21, 30, 33, 36, 37, 40, 41, 47, 48 CONDITIONS 23 MIN. TYP. 50 80 MAX. UNIT k ti(r), ti(f) tLH5 VDDD5V = 5.5 V VDDD5V = 3.6 V VDDD5V = 5.5 V; VDDD3V = 3.6 V; Tj = -40 C; CL = 60 pF - - 5 6 6 - 200 200 - ns ns ns VDDD5V = 4.5 V; VDDD3V = 3 V; - Tj = 125 C; CL = 60 pF tLH3 output rise time on pins 20, 21, 30, 33, 36, 37, 40, 41, 47, 48 VDDD5V = 3.6 V; VDDD3V = 3.6 V; Tj = -40 C; CL = 60 pF 7.5 - - 25 - ns ns VDDD5V = 3.0 V; VDDD3V = 3 V; - Tj = 125 C; CL = 60 pF tLH(I2C5) tLH(I2C3) tHL5 output rise time on pin 46 (SDA) output rise time on pin 46 (SDA) output fall time on pins 20, 21, 30, 33, 36, 37, 40, 41, 47, 48 CL and Rpu are application specific CL and Rpu are application specific VDDD5V = 5.5 V; VDDD3V = 3.6 V; Tj = -40 C; CL = 60 pF - - 5 - - - - 30 - - - ns ns ns ns VDDD5V = 4.5 V; VDDD3V = 3 V; - Tj = 125 C; CL = 60 pF tHL3 output fall time on pins 20, 21, 30, 33, 36, 37, 40, 41, 47, 48 VDDD5V = 3.6 V; VDDD3V = 3.6 V; Tj = -40 C; CL = 60 pF 7.5 - - 25 - ns ns VDDD5V = 3.0 V; VDDD3V = 3 V; - Tj = 125 C; CL = 60 pF tHL(I2C5) output fall time on pin 46 (SDA) VDDD5V = 5.5 V; VDDD3V = 3.6 V; Tj = -40 C; CL = 200 pF 30 - - 30 - ns ns VDDD5V = 4.5 V; VDDD3V = 3 V; - Tj = 125 C; CL = 200 pF tHL(I2C3) output fall time on pin 46 (SDA) VDDD5V = 3.6 V; VDDD3V = 3.6 V; Tj = -40 C; CL = 200 pF 40 - - 300 - ns ns VDDD5V = 3.0 V; VDDD3V = 3 V; - Tj = 125 C; CL = 200 pF - 400 ns 1999 Aug 05 31 Philips Semiconductors Preliminary specification Sound effects DSP 13 ANALOG OUTPUTS CHARACTERISTICS Tamb = 25 C; VDDA2 = 3.3 V; unless otherwise specified. SYMBOL VVREFDA ZVREFDA Vo(rms) VO(AV) Ipu(POML) Ipu(POMH) PSRRDAC Io(max) PARAMETER voltage on pin VREFDA impedance on pin VREFDA AC output voltage of operational amplifiers (RMS value) average DC output voltage of operational amplifiers low pull-up current to VDDA2 on pin POM high pull-up current to VDDA2 on pin POM CONDITIONS with respect to VDDA2 - VSSA2 with respect to VDDA2 with respect to VSSA2 maximum RL > 5 k RL > 5 k voltage on pin POM < 0.6 V voltage on pin POM > 0.8 V I2S-bus signal; MIN. 47 - - 0.62 1.5 3.3 50 45 - SAA7712H TYP. 50 37 37 0.7 1.65 - - 60 - MAX. 53 - - 0.82 1.8 5 75 - 0.38 UNIT % k k V V A A dB dB power supply ripple rejection DACs fripple = 1 kHz; Vripple = 100 mV (input via I2S-bus) (peak value); CVREFDA = 22 F maximum deviation in output level (plus or minus) of the 4 DAC current outputs crosstalk between all outputs in the audio band output short-circuit current DAC resolution with respect to the average of the 4 outputs; full-scale output one output digital silence, other three maximum volume output short-circuited to ground ct Io(sc) RESDAC - - - - - 18 -75 -69 20 -60 dB mA bits dBA (THD + N)/S total harmonic f = 1 kHz; distortion-plus-noise to signal ratio Vo(ref) = 0.72 V (RMS); A-weighted DRDAC DSDAC dynamic range of DAC digital silence of DAC Vo(ref) = 0.72 V (RMS); f = 1 kHz; -60 dB; A-weighted f = 20 Hz - 17 kHz; Vo(ref) = 0.72 V (RMS); A-weighted A-weighted f = 60 Hz and 7 kHz, ratio 4 : 1 90 - 96 -107 - -102 dBA dBA Vn(o)(rms) d fs(max) BDAC CL(DAC) RL(DAC) digital silence noise level at output (RMS value) intermodulation distortion/comparator maximum sample frequency bandwidth DAC load capacitance on DAC outputs load resistance on DAC voltage outputs - - 48 3 -70 - 1 2fs 8 -55 - - 2.5 - V dB kHz kHz nF k at -3 dB DC decoupled - - 5 - - 1999 Aug 05 32 Philips Semiconductors Preliminary specification Sound effects DSP 14 OSCILLATOR CHARACTERISTICS SYMBOL fxtal fxtal(adj) fxtal(T) f Vxtal(M) gm(start) gm(oper) CL Ncy(start) Ixtal PARAMETER crystal frequency crystal frequency variation with adjustment crystal frequency variation with temperature spurious frequency attenuation voltage across the crystal (absolute peak value) transconductance at start-up transconductance when operating capacitive load of clock output number of cycles during start-up supply current depends on quality of the external crystal at start-up at oscillation in slave mode Pxtal Vi(clk) Rxtal Ro drive level external clock input voltage allowed loss resistance of the crystal output resistance at oscillation in slave mode Cp = 5 C1 = 10 pF; C2 = 10 pF; see Fig.9 at start-up; fxtal = 18.432 MHz; VDD_OSC = 3.3 V pF(1); Tamb = 25 C CONDITIONS MIN. 10.000 -30 -30 20 1.6 10.5 3.6 - - - - - - 3 - 750 - - - - 2.6 19 - 15 1000 7 0.6 0.65 0.4 3.3 20 1300 TYP. SAA7712H MAX. 19.456 +30 +30 - 3.6 32 38 - - 15 2 0.9 0.5 3.6 100 2800 UNIT MHz ppm ppm dB V mS mS pF cycles mA mA mA mW V Note 1. Cp is the parasitic parallel capacitance of the crystal. 1999 Aug 05 33 Philips Semiconductors Preliminary specification Sound effects DSP 15 I2S-BUS TIMING CHARACTERISTICS Timing of the serial digital data inputs and outputs (see Fig.17). SYMBOL Tcy tsu(D) th(D) tsu(WS) th(WS) td(D) td(WS) bit clock cycle time data set-up time (host) data set-up time (I2S-bus) data hold time (host) data hold time (I2S-bus) word select set-up time word select hold time data delay time (host) word select delay time (host) (I2S-bus) (I2S-bus) PARAMETER MIN. 70 32 10 5 10 10 10 - - - - - - - - - SAA7712H MAX. UNIT ns ns ns ns ns ns ns ns ns 20 15 handbook, full pagewidth WS OUT left WS IN right tBCK(H) tBCK(L) th(WS) td(D) tsu(WS) td(WS) tr BCK tf th(D) Tcy DATA IN LSB MSB tsu(D) DATA OUT MGS220 Fig.17 Timing definitions of the serial digital inputs and outputs. 1999 Aug 05 34 Philips Semiconductors Preliminary specification Sound effects DSP 16 I2C-BUS TIMING CHARACTERISTICS Timing of the I2C-bus (see Fig.18); all values referred to VIH and VIL (see Section 12). SYMBOL fSCL tBUF tHD;STA PARAMETER SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition; after this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock set-up time for a repeated START condition data hold time data set-up time rise time of both SDA and SCL signals fall time of both SDA and SCL signals set-up time for STOP condition capacitive load for each bus line maximum pulse width for spike suppression for standard mode system tSU;DAT > 250 ns fSCL = 400 kHz fSCL = 100 kHz I2C-bus CONDITIONS 0 1.3 0.6 MIN. - - SAA7712H MAX. 400 UNIT kHz s s tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO Cb tSP Note 1.3 0.6 0.6 0 100 20 + 0.1Cb(1) 20 + 0.1Cb(1) 20 + 0.6 - - 0.1Cb(1) - - - 0.9 - 300 1000 300 - 400 50 s s s s ns ns ns ns s pF ns 1. Cb is the bus line capacitance in pF. 1999 Aug 05 35 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 Aug 05 SDA t BUF t LOW tr tf t HD;STA t SP Philips Semiconductors Sound effects DSP Fig.18 Timing definition of the I2C-bus. handbook, full pagewidth 36 SCL t HD;STA P S t HD;DAT t HIGH t SU;DAT t SU;STA t SU;STO Sr MBC611 P Preliminary specification SAA7712H Philips Semiconductors Preliminary specification Sound effects DSP 17 APPLICATION INFORMATION SAA7712H The application diagram (see Fig.19) must be considered as one of the examples of a (limited) application of the chip e.g. in this case the I2S-bus inputs are not used. For the real application set-up the information of the application report and application support by Philips are necessary on issues such as EMC, kappa reduction of the package, DSP programming, etc. handbook, full pagewidth +3 V +5 V +5 V BLM32A07 +3 V I2S_IN1_DATA I2S_IN2_DATA I2S_IO_OUT2 I2S_IN1_BCK I2S_IN2_BCK I2S_IO_OUT1 I2S_IN1_WS I2S_IN2_WS I2S_IO_BCK I2S_IO_WS I2S_IO_IN1 I2S_IO_IN2 VDDD3V2 VDDD3V1 VDDD5V2 27 29 28 24 26 25 37 36 30 31 32 33 14 53 52 34 VDDD5V3 22 nF 22 nF 22 nF VDDA2 42 22 VDDD5V1 +5 V 22 nF 100 OUT0 HOST I/O 19 OUT0_V 18 OUT0_I I2S-BUS INPUT SWITCH 16 OUT1_V 1.8 nF 100 17 OUT1_I 1.8 nF DSP QUAD DAC 12 OUT2_V 11 OUT2_I 9 OUT3_V 1.8 nF 100 10 nF 100 OUT1 10 nF OUT2 SYS_CLK 21 10 OUT3_I 8 POM BLM32A07 +3 V 100 nF VDD_OSC 64 VSS_OSC 61 RTCB 58 SHTCB 59 TSCAN 60 62 OSC_IN OSC_OUT OUT3 10 nF 10 nF 1.8 nF 2 OSCILLATOR PLL 15 VREFDA 22 F 38 DSP_IN1 EQUALIZER I2C-BUS INTERFACE 39 DSP_IN2 40 DSP_OUT1 41 DSP_OUT2 20 EQOV 4.7 F SAA7712H 63 TEST1 47 TEST2 48 VSSD3V5 55 54 51 50 49 43 DSP_RESET VSSD3V4 VSSD3V3 VSSD3V2 VSSD3V1 VSSD5V3 57 VSSD3V6 56 VSSD5V2 35 23 VSSD5V1 VSSA2 13 SDA 46 SCL 45 A0 44 11.2896 MHz 10 pF 10 pF 1 F 4.7 k 4.7 k MGS222 +5 V Fig.19 Application diagram. 1999 Aug 05 37 Philips Semiconductors Preliminary specification Sound effects DSP 18 PACKAGE OUTLINE QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height SAA7712H SOT318-1 c y X 64 65 41 40 ZE A e E HE wM pin 1 index bp 25 1 wM D HD ZD B vM B 24 vM A Lp L detail X A A2 A1 (A 3) 80 e bp 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.3 A1 0.36 0.10 A2 2.87 2.57 A3 0.25 bp 0.45 0.30 c 0.25 0.13 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.8 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.0 0.6 1.2 0.8 7 0o o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT318-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-08-01 1999 Aug 05 38 Philips Semiconductors Preliminary specification Sound effects DSP 19 SOLDERING 19.1 Introduction to soldering surface mount packages SAA7712H If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 19.4 Manual soldering This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 19.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 19.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 1999 Aug 05 39 Philips Semiconductors Preliminary specification Sound effects DSP 19.5 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable suitable(2) recommended(3)(4) recommended(5) suitable not not suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not SAA7712H REFLOW(1) 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 1999 Aug 05 40 Philips Semiconductors Preliminary specification Sound effects DSP 20 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values SAA7712H This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 21 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 22 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1999 Aug 05 41 Philips Semiconductors Preliminary specification Sound effects DSP NOTES SAA7712H 1999 Aug 05 42 Philips Semiconductors Preliminary specification Sound effects DSP NOTES SAA7712H 1999 Aug 05 43 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999 Internet: http://www.semiconductors.philips.com SCA 67 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545004/25/01/pp44 Date of release: 1999 Aug 05 Document order number: 9397 750 04868 |
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