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VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8132
Features
* 2.488Gb/s 1:32 Demultiplexer * SONET STS-48/SDH STM-16 * HSPECL Differential Serial Data and Clock Inputs * 32-Bit TTL Parallel Data Outputs with Odd/ Even Parity Check * Frame Detect Synchronization
2.488Gb/s 1:32 SONET/SDH Demux
* 77.76, 51.84, and 38.88MHz TTL Clock Outputs * Single 3.3V supply * Loss of Clock Alarm * Loss of Data Alarm * 2.05W Max Power Dissipation * 128-Pin PQFP Package
General Description
The VSC8132 demultiplexes a 2.488Gb/s HSPECL serial input datastream (DI+) to 32-bit wide, TTL 77.76Mb/s parallel data outputs D[31:0] for SONET/SDH applications. A 2.488GHz HSPECL input clock (CLKI+) is used to time the incoming data and 3 TTL clock outputs, at frequencies of 77.76MHz, 51.84MHz, and 38.88MHz, are generated for upstream devices (DATACLK78, CLK51, CLK38). Odd or even parity is performed on the incoming high-speed data via the TTL Parity Select input (PARSEL), and a TTL Parity output (PARITY) is provided to indicate parity of the input data. Frame Detect on the incoming data is controlled via the Frame Detect Inhibit (OOFN) and Reset (RESET) TTL inputs. A frame detect monitors the incoming data steam and screens for 2 bits in A1 byte out of the 8 bits and 2 bits of A2 byte out of the 8 bits. When a Frame Detect occurs, a synchronization TTL output (SYNC) will be set. Alarm indicators are used to monitor the activity of the clock and data with TTL compatible control inputs (ALMRESET) and outputs (DTALARM, CKALARM). Only a single 3.3V power supply is required for device operation. The VSC8132 is packaged in a thermally-enhanced 128-pin, 14x20x2mm PQFP package.
VSC8132 Block DIagram
OOFN RESET PARSEL Framing and Parity DATA[3:0] SYNC PARITY
DI+ DI- CLKI+ CLKI- DTALARM Alarms ALMRESET CKALARM DATACLK78 1:32 Demux Clock Generation CLK51 CLK38
G52250-0, Rev 3.1 12/7/00
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
2.488Gb/s 1:32 SONET/SDH Demux
VSC8132
Functional Description
High-Speed Clock and Data Interface The incoming high-speed data and high-speed clock are received by high-speed inputs DI+ and CLKI+. The inputs are internally biased to accommodate AC-coupling. The data and clock inputs are internally terminated by a center-tapped resistor network. For differential input DC-coupling, the network is terminated to the appropriate termination voltage, VTERM providing a 50 to VTERM termination for both true and complement inputs. For differential input AC-coupling, the network is terminated to VTERM via a blocking capacitor. In most situations, these inputs will have high transition density and little DC offset. However, in cases where this does not hold, direct DC connection is possible. All serial data and clock inputs have the same circuit topology as shown in Figure 1. The reference voltage is created by a resistor divider as shown. If the input signal is driven differentially and DC-coupled to the part, the mid-point of the input signal swing should be centered about this reference voltage and not exceed the maximum allowable amplitude. For single-ended, DCcoupling operations, it is recommended that the user provides an external reference voltage which has better temperature and power supply noise rejection than the on-chip resistor divider. The external reference should have a nominal value equivalent to the common mode switch point of the DC-coupled signal, and can be connected to either side of the differential gate. Figure 1: High-Speed Clock and Data Inputs
Chip Boundary VCC = 3.3V
1.65V Z0 CIN 100nF 3k 3k
1.65V
CAC 100nF VTERM CIN 100nF
50
3k
II
3k
Z0
50
VEE = 0V
Page 2
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52250-0, Rev 3.1 12/7/00
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8132
2.488Gb/s 1:32 SONET/SDH Demux
Low-Speed Data Interface The 77.76Mb/s parallel data outputs D[31:0] are clocked out of the VSC8132 on the falling clock edge of the 77.76MHz output clock (DATA78CLK). The data and clock are TTL levels. The MSB (D31) bit is the first bit into the serial interface. Parity Selection The parity output bit (PARITY) is clocked out on the falling edge of the 77.76MHz clock (DATA78CLK). This bit indicates the parity of the 32 bits of data along with the frame sync bit. The parity of the output is determined by the parity select input (PARSEL). When the parity select input is LOW, the output parity is odd. When the parity select is HIGH, the output parity is even. The parity inputs and outputs are TTL levels. See Figure 2 for output timing relationship. Framing Logic Interface When a frame detect occurs and the frame detect inhibit input (OOFN) is set LOW, the frame detect output (SYNC) is set HIGH on the negative edge of the 77.76MHz clock and on the 3rd set of four A2 bytes at the 32bit data output. The frame detect mechanism is inhibited when the frame detect inhibit (OOFN) input is set HIGH. The frame detect output and frame detect inhibit are TTL levels.
NOTE: The 77.76MHz clock misses one clock cycle during a frame detect. This missed cycle occurs one clock period before the Sync pulse is set HIGH (see Figure 4). To use as a framer: Step 1: Set OOFN LOW Step 2:Wait for Sync pulse Step 3:When Sync Pulse goes HIGH, set OOFN HIGH
Chip Reset Chip reset (RESET) will reset the framing logic so that no frame detection barrel shifting is performed. Therefore, if the frame detect inhibit input is set high, the chip will act as a simple demux after reset. The reset should be set high for 16 clock cycles of the high speed clock input. The chip reset is a TTL level. Alarm Logic Interface The Loss of Clock (CKALARM) and Loss of Data (DTALARM) alarms monitor the activity of the clock and data. The Alarm Reset (ALMRESET) input controls the alarm activity. Polling of the alarms signals are initiated by toggling the Alarm Reset input HIGH and then LOW one time. To reset both alarm outputs, the Alarm Reset should be toggled HIGH to LOW two times. All alarm logic interface signals are TTL levels. Supplies The VSC8132 is specified as a HSPECL/TTL device with a single positive 3.3V supply. Normal operation is to have VCC = +3.3V and VEE = ground. Should the user desire to use the device in a ECL environment with a negative 3.3V supply, VCC will be ground and VEE will be -3.3V. If used with VEE tied to -3.3V, the TTL output signals are still referenced to VEE.
G52250-0, Rev 3.1 12/7/00
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
2.488Gb/s 1:32 SONET/SDH Demux
VSC8132
Decoupling of the power supplies is a critical element in maintaining the proper operation of the part. It is recommended that the VCC power supply be decoupled using a 0.1F and 0.01F capacitor placed in parallel on each VCC power supply pin as close to the package as possible. If room permits, a 0.001F capacitor should also be placed in parallel with the 0.1F and 0.01F capacitors mentioned above. Recommended capacitors are low-inductance ceramic SMT X7R devices. For the 0.1F capacitor, a 0603 package should be used. The 0.01F and 0.001F capacitors can be either 0603 or 0402 packages. For low frequency decoupling, 47F tantalum, low-inductance SMT caps should be sprinkled over the board's main +3.3V power supply and placed close to the C-L-C pi filter. If the device is being used in an ECL environment with a -3.3V supply, all references to decoupling VCC must be changed to VEE, and all references to decoupling 3.3V must be changed to -3.3V.
AC Characteristics
Figure 2: Output Timing
tPD1 tPD2
78MHz CLK
78MHz DATA
SYNC PULSE
PARITY
Figure 3: Data Output Timing
tSERSU DI+ Differential Serial Data Input tSERHO D0 LSB Time CLKI+ Differential Clock Input
D31 MSB
NOTE: Bit 31 (MSB) is received first, Bit 0 (LSB) is received last.
Page 4
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52250-0, Rev 3.1 12/7/00
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8132
Missed Clock Pulse(1) CLK78 (Out)(1)
2.488Gb/s 1:32 SONET/SDH Demux
Figure 4: Framing Sequence
Approximately <110s
SYNC PULSE (Out)
OOFN (In)
(asynchronous)
Set HIGH, less than 110s after SYNC goes HIGH NOTE: (1) No missing clock pulse for CLK78 when VSC8132 is working as a dumb demux. Once frame occurs and OOFN is set HIGH, the no framing will occur until OOFN is set LOW again. The VSC8132 will remain framed with SONET frame.
Table 1: AC Characteristics Parameters
tDATApd tCLKRpd tCLKFpd tDEDGE tCLKEDGE tCONEDGE tSERSU tSERHO fMAX tCLK38Rpd tCLK38Fpd tCLK51Rpd tCLK51Fpd tPD1, tPD2
Description
Data Valid From Falling Edge of 77.76MHz High-speed Clock Rising Edge to 77.76MHz Clock Rising Edge High-Speed Clock Rising Edge to 77.76MHz Clock Falling Edge D[0:31] Edge Rate (10%-90%) 77.76, 51.84, 38.88MHz Edge Rates (10%-90%) Control Signals (SYNC, PARITY, DTALARM, and CKALARM) Edge Rate (10%-90%) DI+ Setup Time with Respect to Falling Edge of CLKI+ DI+ Hold Time with Respect to Falling Edge of CLKI+ Demux Input Maximum Clock Frequency High-Speed Clock Rising Edge to 38.88MHz Clock Rising Edge. High-Speed Clock Rising Edge to 38.88MHz Clock Falling Edge High-Speed Clock Rising Edge to 51.84MHz Clock Rising Edge High-Speed Clock Rising Edge to 51.84MHz Clock Falling Edge Data Invalid Window
Min
230 2.5 2.3 100 75 2.0 2.0 2.0 2.0 0, 230
Typ
Max
1250 8.0 7.1 2.0 2.0 2.0 2.9 6.3 5.9 6.0 5.9 0, 1250
Units
ps ns ns ns ns ns ps ps GHz ns ns ns ns ps
Conditions
External load = 5pf External load = 5pf External load = 5pf External load = 5pf External load = 5pf External load = 5pf
See Figure 3 See Figure 3
External load = 5pf External load = 5pf External load = 5pf External load = 5pf
G52250-0, Rev 3.1 12/7/00
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 5
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
2.488Gb/s 1:32 SONET/SDH Demux
VSC8132
DC Characteristics
Table 2: DC Characteristics (Over recommended operating conditions) Parameters
VOHttl VOLttl VIHttl VILttl VOHpecl VOLpecl
Description
Output HIGH Voltage (TTL) Output LOW Voltage (TTL) Input HIGH Voltage (TTL) Input LOW Voltage (TTL) Output HIGH Voltage (HSPECL) Output LOW Voltage (HSPECL)
Min
2.4 -- 2.0 -- VCC1.02 VCC2.0 400
Typ
-- -- -- -- -- -- --
Max
-- 0.5 -- 0.8 VCC0.7 VCC1.62 1200
Units
V V V V V V
Conditions
IOH = -1.0mA IOL = +1.0mA IIH = 300A IIL = -50A Output tied to 50 to VCC-2.0V Output tied to 50 to VCC-2.0V AC-coupled, internally biased to VCC/2 AC-coupled, internally biased to VCC/2 3.3V +5% Outputs open, VCC = VCC max Outputs open, VCC = VCC max
Demux Clock Input Absolute Voltage VDIFF(CLKI) Differential Peak-to-Peak Swing (CLKI+) VDIFF(DI) VCC PD IDD Demux Serial Input Absolute Voltage Differential Peak-to-Peak Swing (DI+) Supply Voltage Power Dissipation Supply Current
mV
400 3.14 -- --
-- -- 1.6 489
1200 3.47 2.05 591
mV V W mA
Absolute Maximum Ratings (1)
Power Supply Voltage (VCC)...........................................................................................................-0.5V to +3.8V DC Input Voltage (differential inputs).....................................................................................-0.5V to VCC +0.5V Output Current (differential outputs)........................................................................................................... 50mA Case Temperature Under Bias ...................................................................................................... -55oC to +125oC Storage Temperature..................................................................................................................... -65oC to +150oC Maximum Input ESD (Human Body Model)............................................................................................... 1500V
NOTE: (1) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability.
Recommended Operating Conditions
Power Supply Voltage (VCC)................................................................................................................. +3.3V+5% Operating Temperature Range ............................................................. 0oC Ambient to +85oC Case Temperature
Figure 5: Parametric Measurement Information
TTL Rise and Fall Time 90% 10% tR tF
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(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52250-0, Rev 3.1 12/7/00
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8132
Package Pin Descriptions
2.488Gb/s 1:32 SONET/SDH Demux
Figure 6: Pin Diagram
VCC VEE VEE THTRIST6 DTALARM VCC VEE ALMRESET THRIST4 VEE VCC THRIST1 PARSEL THRIST5 THPAR VCC SYNC DATACLK78 VEE TH78DT0 (LSB) TH78DT1 VCC TH78DT2 TH78DT3 NC VCC NC NC NC VCC NC VEECTERM NC VCC CLKI+ CLKINC VEE DI+ DIVEEDTERM VEE VEE NC NC NC VCC NC VCC VCC VCC VEE VEE VEE VEE VEE NC NC NC RESET NC NC NC NC 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VCC TH78DT4 TH78DT5 VCC TH78DT6 TH78DT7 VEE TH78DT8 TH78DT9 VCC TH78DT10 TH78DT11 VCC TH78DT12 TH78DT13 VEE TH78DT14 TH78DT15 VCC TH78DT16 TH78DT17 VCC TH78DT18 TH78DT19 VEE TH78DT20 TH78DT21 VCC TH78DT22 TH78DT23 VCC TH78DT24 TH78DT25 VEE TH78DT26 TH78DT27 VCC NC
G52250-0, Rev 3.1 12/7/00
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
VCC VEE CKALARM VEE VCC OOFN NC NC NC CLK51CLK51+ VCC VEE CLK38CLK38+ VCC THTRIST2 THTRIST3 VEE TH78DT31 (MSB) TH78DT30 VCC TH78DT29 TH78DT28 NC VCC
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
VITESSE VSC8132
Page 7
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
2.488Gb/s 1:32 SONET/SDH Demux
Table 3: Pin Identifications Pin
1
VSC8132
Level
+3.3V GND +3.3V
Name
NC NC NC VCC NC VEECTERM NC VCC CLKI+ CLKINC VEE DI+ DIVEEDTERM VEE VEE NC NC NC VCC NC VCC VCC VCC VEE VEE VEE VEE VEE NC NC NC RESET
I/O
I I I I I/O
Description
No Connect, Leave Unconnected No Connect, Leave Unconnected No Connect, Leave Unconnected Power Supply No Connect, Leave Unconnected 50 Termination Ground for CLK No Connect, Leave Unconnected Power Supply High-Speed Clock Input, True High-Speed clock Input, Complement No Connect, Leave Unconnected Ground High-Speed Serial Data Input, True. PECL levels, AC-coupled, internally biased to VCC/2. High-Speed Serial Data Input, Complement. PECL levels, ACcoupled, internally biased to VCC/2. 50 Termination Ground for DI Ground Ground No Connect, Leave Unconnected No Connect, Leave Unconnected No Connect, Leave Unconnected Power Supply No Connect, Leave Unconnected Power Supply Power Supply Power Supply Ground Ground Ground Ground Ground No Connect, Leave Unconnected No Connect, Leave Unconnected No Connect, Leave Unconnected Resets Framing Logic and Output Clocks
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
HSPECL HSPECL 0V HSPECL HSPECL GND 0V 0V +3.3V +3.3V +3.3V +3.3V 0V 0V 0V 0V 0V TTL
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G52250-0, Rev 3.1 12/7/00
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8132
Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Name
NC NC NC NC VCC VEE CKALARM VEE VCC OOFN NC NC NC CLK51CLK51+ VCC VEE CLK38CLK38+ VCC THTRIST2 THTRIST3 VEE TH78DT31 TH78DT30 VCC TH78DT29 TH78DT28 NC VCC NC VCC TH78DT27 TH78DT26
2.488Gb/s 1:32 SONET/SDH Demux
I/O
O I O O O O I I O O O O O O
Level
+3.3V 0V TTL 0V +3.3V TTL HSPECL HSPECL +3.3V 0V HSPECL HSPECL +3.3V TTL TTL 0V TTL TTL +3.3V TTL TTL +3.3V +3.3V TTL TTL
Description
No Connect, Leave Unconnected No Connect, Leave Unconnected No Connect, Leave Unconnected No Connect, Leave Unconnected Power Supply Ground Loss of clock output. Stays HIGH when loss of clock is detected. Ground Power Supply Frame Detect Disable Input. Disables frame detection if set HIGH. No Connect, Leave Unconnected No Connect, Leave Unconnected NNo Connect, Leave Unconnected Low-Speed Clock Output (51.84MHz), Complement Low-Speed Clock Output (51.84MHz), True Power Supply Ground Low-Speed Clock Output (38.88MHz), Complement Low speed Clock Output (38.88MHz), True Power Supply Tri-State Inputs. Allows tri-stating of all output signals. Used for test only. Should be tied to VEE during normal operation. Tri-State Inputs. Allows tri-stating of all output signals. Used for test only. Should be tied to VEE during normal operation. Ground Low-Speed Parallel Data (MSB) Low-Speed Parallel Data Power Supply Low-Speed Parallel dData Low-Speed Parallel Data No connect, leave unconnected Power Supply No Connect, Leave Unconnected Power Supply Low-Speed Parallel Data Low-Speed Parallel Data
G52250-0, Rev 3.1 12/7/00
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
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VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
2.488Gb/s 1:32 SONET/SDH Demux
Pin 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Name
VEE TH78DT25 TH78DT24 VCC TH78DT23 TH78DT22 VCC TH78DT21 TH78DT20 VEE TH78DT19 TH78DT18 VCC TH78DT17 TH78DT16 VCC TH78DT15 TH78DT14 VEE TH78DT13 TH78DT12 VCC TH78DT11 TH78DT10 VCC TH78DT9 TH78DT8 VEE TH78DT7 TH78DT6 VCC TH78DT5 TH78DT4 VCC VCC NC
VSC8132
Level
0V TTL TTL +3.3V TTL TTL +3.3V TTL TTL 0V TTL TTL +3.3V TTL TTL +3.3V TTL TTL 0V TTL TTL +3.3V TTL TTL +3.3V TTL TTL 0V TTL TTL +3.3V TTL TTL +3.3V +3.3V Ground Low-Speed Parallel Data Low-Speed parallel Data Power Supply Low-Speed Parallel Data Low-Speed Parallel Data Power Supply Low-Speed Parallel Data Low-Speed Parallel Data Ground Low-Speed Parallel Data Low-Speed Parallel Data Power Supply Low-Speed Parallel Data Low-Speed Parallel Data Power Supply Low-Speed Parallel Data Low-Speed Parallel Data Ground Low-Speed Parallel Data Low-Speed Parallel Data Power Supply Low-Speed Parallel Data Low-Speed Parallel Data Power Supply Low-Speed Parallel Data Low-Speed Parallel Data Ground Low-Speed Parallel Data Low-Speed Parallel Data Power Supply Low-Speed Parallel Data Low-Speed Parallel Data Power Supply Power Supply No Connect, Leave Unconnected
I/O
O O O O O O O O O O O O O O O O O O O O O O -
Description
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(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52250-0, Rev 3.1 12/7/00
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8132
Pin 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Name
TH78DT3 TH78DT2 VCC TH78DT1 TH78DT0 VEE DATACLK78 SYNC VCC THPAR THTRIST5 PARSEL THTRIST1 VCC VEE THTRIST4 ALMRESET VEE VCC DTALARM THTRIST6 VEE VEE VCC
2.488Gb/s 1:32 SONET/SDH Demux
I/O
O O O O O O O I I I I I O I -
Level
TTL TTL +3.3V TTL TTL 0V TTL TTL +3.3V TTL TTL TTL TTL +3.3V 0V TTL TTL 0V +3.3V TTL TTL 0V 0V +3.3V Low-Speed Parallel Data Low-Speed Parallel Data Power Supply Low-Speed Parallel Data
Description
Low-Speed Parallel Data (LSB) Ground Low-Speed Clock Output (77.76MHz). A divide-by-32 version of the CLKI input clock. Frame Detect Output. Set HIGH when frame detect occurs. Power Supply Parity Output Tri-State Inputs. Allows tri-stating of all output signals. Used for test only. Should be tied to VEE during normal operation. Parity Select Input. HIGH for even; LOW for odd. Tri-State Inputs. Allow tri-stating of all output signals. Used for test only. Should be tied to VEE during normal operation. Power Supply Ground Tri-State Inputs. Allow tri-stating of all output signals. Used for test only. Should be tied to VEE during normal operation. Alarm Reset. Resets and clocks out Loss of Clock and Loss of Data alarms. Ground Power Supply Loss of Data Output. Stays HIGH when loss of data is detected. Tri-state Inputs. Allow tri-stating of all output signals. Used for test only. Should be tied to VEE during normal operation. Ground Ground Power Supply
G52250-0, Rev 3.1 12/7/00
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
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VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
2.488Gb/s 1:32 SONET/SDH Demux
VSC8132
128-Pin PQFP Package Drawing
Package Information
PIN 128 PIN 1
RAD. 2.92 .50 (2)
Key
A
E1 E
mm
2.35 0.25 2.00 17.20 14.00 23.20 20.00 .88 .50 .22 0-7 .30 .20
Tolerance
MAX MAX +.10 .20 .10 .20 .10 +.15/-.10 BASIC .05 TYP TYP
A1 A2 D
2.54 .50 EXPOSED HEATSINK EXPOSED INTRUSION 0.127 MAX.
D1 E E1 L
D1 D TOP VIEW 10 TYP.
e b R R1
A2
A
A1 10 TYP.
e
R
R1
1
STANDOFF
A
Notes: 1) 2) 3) Drawing is not to scale All dimensions in mm Package represented is also used for the 64, 80, & 100 PQFP packages. Pin count drawn does not reflect the 128 Package.
.25
A1
NOTES:
0.17
MAX.
b
LEAD COPLANARITY
L
Package #: 101-267-7 Issue #: 1
Page 12
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52250-0, Rev 3.1 12/7/00
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8132
Package Thermal Considerations
2.488Gb/s 1:32 SONET/SDH Demux
The VSC8132 has been enhanced with a copper heat slug to provide a low thermal resistance path from the die to the exposed surface of the heat spreader. The thermal resistance is shown in Table 4.
Table 4: Thermal Resistance Symbol
JC JA
Description
Thermal resistance from junction-to-case. Thermal resistance from junction-to-ambient with no airflow, including conduction through the leads.
C/W
2.2 26.8
Thermal Resistance with Airflow Thermal resistance with airflow is shown in Table 5. The thermal resistance value reflects all the thermal paths including through the leads in an environment where the leads are exposed. The temperature difference between the ambient airflow temperature and the case temperature should be the worst-case power of the device multiplied by the thermal resistance. Table 5: Thermal Resistance with Airflow Airflow
100 lfpm 200 lfpm 400 lfpm 600 lfpm
CA (oC/W)
19.8 16.7 14.6 13.0
Maximum Ambient Temperature without Heatsink The worst case ambient temperature without use of a heatsink is given by the equation:
T A ( MAX ) = T C ( MAX ) - P ( MAX ) CA
where: TA(MAX) C(MAX) P(MAX) CA Ambient air temperature Case temperature (+85oC) Power (2.05W) Theta case-to-ambient at appropriate airflow
G52250-0, Rev 3.1 12/7/00
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
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VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
2.488Gb/s 1:32 SONET/SDH Demux
The results of this calculation are listed in Table 6.
Table 6: Maximum Ambient Air Temperature without Heatsink Airflow
None 100 lfpm 200 lfpm 400 lfpm 600 lfpm Max Ambient Temperature (oC) 35.6 44.4 50.8 55.1 58.4
VSC8132
Note that ambient air temperature varies throughout the system based on the positioning and magnitude of heat sources and the direction of air flow.
Ordering Information
The order number for this product is formed by a combination of the device type and package type
VSC8132
Device Type 2.488Gb/s 1:32 Demux, 3.3V
xx
Package QR: 128-Pin PQFP, 14x20x2mm Body
Notice
Vitesse Semiconductor Corporation ("Vitesse") provides this document for informational purposes only. This document contains pre-production information about Vitesse products in their concept, development and/or testing phase. All information in this document, including descriptions of features, functions, performance, technical specifications and availabiity, is subject to change without notice at any time. Nothing contained in this document shall be construed as extending any warranty or promise, express or implied, that any Vitesse product will be available as described or will be suitable for or will accomplish any particular task.
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Vitesse Semiconductor Corporation's products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited.
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(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52250-0, Rev 3.1 12/7/00

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