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K6X0808T1D Family
Document Title
32Kx8 bit Low Power CMOS Static RAM
CMOS SRAM
Revision History
Revision No.
0.0 0.1
History
Initial draft revised - errata : corrected 28-SOP-525 to 28-SOP-450 in pakage type revised - Added commercial product. Finalized - Changed ICC from 3mA to 2mA - Changed ICC2 from 25mA to 20mA - Changed ISB from 3mA to 0.4mA - Changed ISB1 for K6X0808T1D-F from 10A to 6A - Changed ISB1 for K6X0808T1D-F from 20A to 10A - Changed IDR for K6X0808T1D-F 10A to 6A - Changed IDR for K6X0808T1D-Q 20A to 10A - Errata correction
Draft Data
October 09, 2002 November 08, 2002
Remark
Preliminary Preliminary
0.2
March 27, 2003
Preliminary
1.0
December 16, 2003
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
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Revision 1.0 December 2003
K6X0808T1D Family
FEATURES
* Process Technology: Full CMOS28* Organization: 32K x 8 * Power Supply Voltage: 2.7~3.6V * Low Data Retention Voltage: 1.5V(Min) * Three state outputs * Package Type: 28-SOP-450, 28-TSOP1-0813.4F/R
CMOS SRAM
GENERAL DESCRIPTION
The K6X0808T1D families are fabricated by SAMSUNGs advanced CMOS process technology. The families support verious operating temperature ranges and have various package types for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current.
32Kx8 bit Super Low Power and Low Voltage full CMOS Static RAM
PRODUCT FAMILY
Power Dissipation Product Family Operating Temperature Vcc Range Speed Standby (ISB1, Max) 6A K6X0808T1D-F K6X0808T1D-Q Industrial(-40~85C) Automotive(-40~125C) 2.7~3.6V 701)/85ns 10A 25mA
28-SOP-450, 28-TSOP1-0813.4F
Operating (ICC2, Max)
PKG Type
K6X0808T1D-B
Industrial(0~70C)
28-SOP-450, 28-TSOP1-0813.4F/R
1. The parameters are tested with 30pF test load
PIN DESCRIPTION
OE A11 A9 A8 VCC A13 WE WE VCC A13 A14 A12 A8 A7 A6 A9 A5 A4 A11 A3 OE A3 A4 A5 A6 I/O8 A7 I/O7 A12 A14 I/O6 VCC WE I/O5 A13 A8 I/O4 A9 A11 A10 CS OE
14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24
FUNCTIONAL BLOCK DIAGRAM
A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2
Clk gen.
Precharge circuit.
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22
28-TSOP Type1 - Forward
23 22 21 20 19 18 17 16 15
Row Addresses
Row select
Memory array
28-SOP
21 20 19 18 17 16 15
28-TSOP Type1 - Reverse
21 22 23 24 25 26 27 28
A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS A10 CS1
I/O1 I/O8
Data cont
I/O Circuit Column select
Data cont Column Addresses
Pin Name
A0~A14 WE CS OE
Function
Address Inputs Write Enable Input Chip Select Input Output Enable Input
Pin Name
I/O1~I/O8 Vcc Vss NC
Function
Data Inputs/Outputs
WE OE
Control logic
Power Ground No connect
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2
Revision 1.0 December 2003
K6X0808T1D Family
PRODUCT LIST
Commercial Temp. Products(0~70C) Part Name K6X0808T1D-GB70 K6X0808T1D-GB85 K6X0808T1D-YB70 K6X0808T1D-YB85 K6X0808T1D-NB70 K6X0808T1D-NB85 Function 28-SOP, 70ns, LL 28-SOP, 85ns, LL 28-sTSOP-F, 70ns, LL 28-sTSOP-F, 85ns, LL 28-sTSOP-R, 70ns, LL 28-sTSOP-R, 85ns, LL Industrial Temp. Products(-40~85C) Part Name K6X0808T1D-GF70 K6X0808T1D-GF85 K6X0808T1D-YF70 K6X0808T1D-YF85 K6X0808T1D-NF70 K6X0808T1D-NF85 Function 28-SOP, 70ns, LL 28-SOP, 85ns, LL 28-sTSOP-F, 70ns, LL 28-sTSOP-F, 85ns, LL 28-sTSOP-R, 70ns, LL 28-sTSOP-R, 85ns, LL
CMOS SRAM
Atomotive Temp. Products(-40~125C) Part Name K6X0808T1D-GQ70 K6X0808T1D-GQ85 K6X0808T1D-YQ70 K6X0808T1D-YQ85 Function 28-SOP, 70ns, L 28-SOP, 85ns, L 28-sTSOP-F, 70ns, L 28-sTSOP-F, 85ns, L
FUNCTIONAL DESCRIPTION
CS H L L L OE X
1)
WE X
1)
I/O High-Z High-Z Dout Din
Mode Deselected Output Disabled Read Write
Power Standby Active Active Active
H L X1)
H H L
1. X means don't care (Must be in high or low states)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT VCC PD TSTG TA Ratings -0.2 to VCC+0.3V(Max. 3.9V) -0.2 to 3.9 1.0 -65 to 150 -40 to 85 -40 to 125 Unit V V W C C C Remark K6X0808T1D-F K6X0808T1D-Q
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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Revision 1.0 December 2003
K6X0808T1D Family
RECOMMENDED DC OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Min 2.7 0 2.2 -0.2
3)
CMOS SRAM
Typ 3.0/3.3 0 -
Max 3.6 0 Vcc+0.2 0.6
2)
Unit V V V V
Note: 1. Industrial Product: TA=-40 to 85C, Otherwise specified Automotive Product: TA=-40 to 125C, Otherwise specified 2. Overshoot: Vcc+3.0V in case of pulse width30ns. 3. Undershoot: -3.0V in case of pulse width30ns. 4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25C)
Item Input capacitance Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Symbol ILI ILO ICC ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current(TTL) Standby Current(CMOS) VOL VOH ISB ISB1 VIN=Vss to Vcc CS=VIH or OE=VIH or WE=VIL, VIO=VSS to Vcc IIO=0mA, CS=VIL, VIN=VIH or VIL, Read Cycle time=1s, 100% duty, IIO=0mA, CS0.2V, VIN0.2VINVcc -0.2V Cycle time=Min,100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL IOL=2.1mA IOH=-1.0mA CS=VIH, Other inputs=VIH or VIL CSVcc-0.2V, Other inputs=0~Vcc K6X0808T1D-F K6X0808T1D-Q Test Conditions Min Typ Max Unit -1 -1 2.4 1 1 2 3 20 0.4 0.3 6 10 A A mA mA mA V V mA A A
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Revision 1.0 December 2003
K6X0808T1D Family
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage:1.5V Output load(see right): CL=100pF+1TTL CL=30pF+1TTL CL1)
CMOS SRAM
1. Including scope and jig capacitance
AC CHARACTERISTICS
(VCC=2.7~3.6V, Industrial product:TA=-40 to 85C, Automotive product:TA=-40 to 125C ) Speed Bins
Parameter List
Symbol Min
70ns Max 70 70 35 25 25 25 Min 85 10 5 0 0 15 85 70 0 70 60 0 0 35 0 5
85ns Max 85 85 40 25 25 30 -
Units
Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Read Chip Select to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z
tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW
70 10 5 0 0 10 70 60 0 60 50 0 0 25 0 5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
DATA RETENTION CHARACTERISTICS
Item Vcc for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR CS1Vcc-0.2V Vcc=3.0V, CS1Vcc-0.2V K6X0808T1D-F K6X0808T1D-Q See data retention waveform 0 5 Test Condition Min 2.0 Typ Max 3.6 6 10 Unit V A A ms
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Revision 1.0 December 2003
K6X0808T1D Family
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC Address tOH Data Out Previous Data Valid tAA
CMOS SRAM
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC Address tAA tCO CS tOE OE tOLZ tLZ Data Valid tOHZ tHZ tOH
Data out
NOTES (READ CYCLE)
High-Z
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
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Revision 1.0 December 2003
K6X0808T1D Family
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC Address tCW(2) CS tAW tWP(1) WE tAS(3) Data in tWHZ Data out Data Undefined tDW Data Valid tDH tWR(4)
CMOS SRAM
tOW
TIMING WAVEFORM OF WRITE CYCLE(2) (CS
Controlled)
tWC Address tAS(3) CS tAW tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4)
Data out
High-Z
High-Z
NOTES (WRITE CYCLE) 1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
VCC 3.0V/2.7V tSDR Data Retention Mode tRDR
2.2V VDR CSVCC - 0.2V CS GND
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Revision 1.0 December 2003
K6X0808T1D Family
PACKAGE DIMENSIONS
CMOS SRAM
Units: millimeter(inch)
28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil)
0~8 #28 #15
11.810.30 0.4650.012
8.380.20 0.3300.008
#1 18.69 MAX 0.736 18.290.20 0.7200.008
#14 2.590.20 0.1020.008 3.00 0.118 MAX
11.43 0.450
+0.10 -0.05 0.006 +0.004 -0.002
0.15
1.020.20 0.0400.008
0.10 MAX 0.004 MAX ( 0.89 ) 0.035 0.410.10 0.0160.004 1.27 0.050
0.05 MIN 0.002
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Revision 1.0 December 2003
K6X0808T1D Family
PACKAGE DIMENSIONS
28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4F)
13.400.20 0.5280.008 #28
CMOS SRAM
Units: millimeter(inch)
0.10 MAX 0.004 MAX
+0.10 -0.05 +0.004 0.008-0.002
0.20
#1
( 8.40 0.331 MAX 8.00 0.315
0.425 ) 0.017
0.55 0.0217
#14 0.25 0.010 TYP 11.800.10 0.4650.004
#15
+0.10 -0.05 0.006+0.004 -0.002
0.15
1.000.10 0.0390.004 1.20 0.047 MAX
0.05 0.002 MIN
0~8
0.45 ~0.75 0.018 ~0.030
(
0.50 ) 0.020
28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4R)
+0.10 -0.05 +0.004 0.008-0.002
0.20
13.400.20 0.5280.008 #15 ( 8.40 0.331 MAX 8.00 0.315 0.425 ) 0.017
#14
0.55 0.0217
#1
#28 1.000.10 0.0390.004 1.20 0.047 MAX 0.05 0.002 MIN
0.25 0.010 TYP
11.800.10 0.4650.004
+0.10 -0.05 0.006+0.004 -0.002
0.15
0~8
0.45 ~0.75 0.018 ~0.030
(
0.50 ) 0.020
9
0.10 MAX 0.004 MAX
Revision 1.0 December 2003

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