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| Ordering number : ENN6169 CMOS IC LC75384NE-R, 75384NW Electronic Volume and Tone Control for Car Stereo Systems Overview The LC75384NE-R and LC75384NW are electronic volume and tone control ICs that can implement volume, balance, fader, bass/treble/mid, loudness, input switching, and input gain control functions with a minimum number of external components. Features * Volume: 81 positions: from 0 dB to -79 dB in 1-dB steps and -. A balance function can be implemented by controlling the left and right volume settings independently. * Fader: Either the rear or front outputs can be attenuated over 16 positions. (16 positions: From 0 dB to -2 dB in 1-dB steps, from -2 dB to -20 dB in 2-dB steps, from -20 to -30 dB in one 10-dB step, -45 dB, -60 dB, and -.) * Bass/treble/mid: Control over 12 dB in 2-dB steps in each band. * Input gain: The input signal can be amplified by from 0 dB to +18.75 dB in 1.25-dB steps. * Input switching: The left and right channels can each be selected from one of 5 inputs. (Four are single-ended inputs and one is a differential input.) * Loudness: Taps are output from a 2-dB step volume control ladder resistor starting at the -32-dB position. A loudness function can be implemented by attaching external capacitors and resistors. * On-chip buffer amplifiers minimize the number of required external components. * Minimal switching noise when no input signals are present due to fabrication in a silicon gate CMOS process that minimizes the noise generated by internal switches. * Use of zero-cross switching circuits for internal switches minimizes switching noise when signals are present. * Built-in VDD/2 reference voltage generator circuit * All controls can be set from serial input data. * CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. www..com SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 51000TH (OT) No.6169-1/25 www..com LC75384NE-R, 75384NW Package Dimensions unit: mm 3159-QIP64E [LC75384NE-R] 17.2 14.0 1.0 48 1.0 1.0 33 1.6 1.6 0.15 1.25 48 49 3190-SQFP64 [LC75384NW] 12.0 10.0 0.5 0.18 1.25 33 32 0.15 32 49 1.25 0.8 12.0 10.0 0.5 17.2 14.0 1.0 64 1 17 16 0.8 0.35 3.0max 0.1 2.7 64 17 1 16 0.5 15.6 0.8 SANYO: QIP64E Specifications Absolute Maximum Ratings at Ta = 25C, VSS = 0 V Parameter Maximum supply voltage Maximum input voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN max Pd max Topr Tstg VDD All input pins Ta 85C, when mounted on a printed circuit board LC75384NE-R LC75384NW Conditions Ratings 11 VSS - 0.3 to VDD + 0.3 500 420 -40 to +85 -50 to +125 Unit V V mW C C Allowable Operating Ranges at Ta = 25C, VSS = 0 V Parameter Supply voltage Input high-level voltage Input low-level voltage Input voltage amplitude Input pulse width Setup time Hold time Operating frequency Symbol VDD VIH VIL VIN toW tsetup thold fopg CL CL, DI, CE CL, DI, CE CL VDD CL, DI, CE, MUTE CL, DI, CE, MUTE Conditions Ratings min 6.0 4.0 VSS VSS 1 1 1 500 typ max 10.5 VDD 1.0 VDD Unit V V V Vp-p s s s kHz 0.1 0.5 SANYO: SQFP64E 1.7max 1.25 No.6169-2/25 LC75384NE-R, 75384NW Electrical Characteristics at Ta = 25C, VDD = 9 V, VSS = 0 V Parameter [Input Block] Input resistance Minimum input gain Maximum input gain Inter-step setting error Left/right balance [Volume Block] Input resistance Inter-step setting error Left/right balance [Tone Control Block] Inter-step setting error Bass control range Mid control range Treble control range Left/right balance [Fader Block] Input resistance Rfed LFIN, RFIN 0 dB to -2 dB Inter-step setting error ATerr -2 dB to -20 dB -20 dB to -30 dB -30 dB to -60 dB Left/right balance BAL 25 50 100 0.5 1 2 3 0.5 k dB dB dB dB dB ATerr Gbass Gmid Gtre BAL max. boost/cut max. boost/cut max. boost/cut 9 9 9 12 12 12 1.0 15 15 15 0.5 dB dB dB dB dB Rvr ATerr BAL LVRIN, RVRIN, loudness off 113 226 339 0.5 0.5 k dB dB Rin Ginmin Ginmax ATerr BAL L1 to L4, R1 to R4 L1 to L4, R1 to R4 30 -1 +16.5 50 0 +18.75 70 +1 +21 0.6 0.5 k dB dB dB dB Symbol Pins Conditions Ratings min typ max Unit Overall Characteristics Parameter Symbol THD 1 THD 2 CT CT VO min 1 VO min 2 VN 1 VN 2 IDD IIH IIL VCL CMRR CL, DI, CE, VIN = 9 V CL, DI, CE, VIN = 0 V THD = 1 %, RL = 10 k, all controls flat, fIN = 1 kHz VIN = 0 dBV, f = 1 kHz -10 2.5 45 2.9 Conditions VIN = -10 dBV, f = 1 kHz VIN = -10 dBV, f = 10 kHz VIN = 1 Vrms, f = 1 kHz VIN = 1 Vrms, f = 1 kHz VIN = 1 Vrms, f = 1 kHz VIN = 1 Vrms, f = 1 kHz, INMUTE, with the fader set to - All controls flat, with the IHF-A filter All controls flat, with a 20 Hz to 20 kHz bandpass filter 80 80 80 90 Ratings min typ 0.004 0.006 88 88 88 95 5 7 33 10 15 40 10 max Unit % % dB dB dB dB V V mA A A Vrms dB Total harmonic distortion Inter-input crosstalk Left/right channel crosstalk Maximum attenuation Output noise voltage Current drain Input high-level current Input low-level current Maximum input voltage Common-mode rejection ratio No.6169-3/25 LC75384NE-R, 75384NW [LC75384NE-R] Allowable power dissipation, Pdmax -- mW 1400 [LC75384NW] Pd max -- Ta Pd max -- Ta 1.4 Mounted on the printed circuit board 1200 Allowable power dissipation, Pdmax -- W Printed circuit board: 114.3 x 76.2 x 1.5 mm3 1.2 Printed circuit board size: 114.3 x 76.1 x 1.6 mm3 Printed circuit board material: Fiberglass/epoxy Mounted on the stipulated printed circuit board 1.04 1000 1.0 800 Independent IC 0.8 600 0.6 Independent IC 0.50 0.42 400 0.4 200 0.2 0.20 0 -40 -20 0 20 40 60 80 100 0 -20 0 20 40 60 80 100 Ambient temperature, Ta -- C Ambient temperature, Ta -- C Pin Assignment LVROUT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 L5P 49 L5M 50 L4 51 L3 52 L2 53 L1 54 LVref 55 VDD 56 Vref 57 RVref 58 R1 59 R2 60 R3 61 R4 62 R5M 63 R5P 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 LTOUT 32 LFIN 31 LFOUT 30 LROUT 29 LAVSS 28 LZCLP 27 DVSS 26 CL 25 DI 24 CE 23 MUTE 22 RAVSS 21 RZCLP 20 TIM 19 RROUT 18 RFOUT 17 RFIN LSELO LF1C1 LF1C2 LF1C3 LF2C1 LF2C2 LF2C3 LF3C1 LF3C2 LC75384NE-R LC75384NW LF3C3 LVRIN LCOM LTIN LCT RVROUT RSE LO RCOM RF1C1 RVRIN RTIN R CT RF1C3 RF2 C1 RF3C1 (Top view) RTOUT RF2 C3 RF2 C2 RF3C2 RF3C3 RF1C2 No.6169-4/25 1 M 0.0033 F 0.033 F 1 F 0.01 F 0.1 F 330 pF 10 F 68 k 4.7 k 0.1 F [BASS fo = 100 Hz] [MID fo = 1000 Hz] [TREBLE fo = 10000 Hz] 220 pF 10 F 1F LTIN LVRIN LF1C1 LF1C2 LF1C3 LF2C1 LF2C2 LF2C3 LF3C1 LF3C2 LF3C3 LTOUT LVROUT LSELO 10 F LCOM LVref LCT LVref 48 32 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 F x 6 LFIN LFOUT LROUT PA L5P 10 F 49 L5M LVref 31 30 29 50 PA L4 LVref LVref LVref LVref 51 L3 LVref 52 LAVSS 28 LZCLP 27 10 F L2 53 LVref L1 54 DVSS 26 10 F LVref 55 Multiplexer ZERO CROSS DET CL 25 24 CL DI DI COM CE 23 22 VDD 56 22 F Vref 57 CONTROL CIRCUIT LOGIC CIRCUIT CCB INTERFACE CE MUTE RAVSS VDD 21 RZCLP 20 VDD 47 k Equivalent Circuit and Sample Application Circuit Diagram 10 F RVref 58 Multiplexer ZERO CROSS DET LC75384NE-R, 75384NW R1 59 RVref R2 60 RVref R3 RVref RVref RVref NO SIGNAL TIMER 1 M TIM RROUT RVref 19 61 R4 0.033 F PA 62 R5M RFOUT 10 F RVref 18 17 PA 63 * In the LC75384NW version, LZCLP (pin 28) and RZCLP (pin 21) are unused, and must be left open. RFIN 10 F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 R5P 64 RTIN RVRIN RF1C1 RF1C2 RF1C3 RF2C1 RF2C2 RF2C3 RF3C1 RF3C2 RF3C3 RSELO RTOUT RVROUT RCOM 10 F RVref RCT RVref 10 F 0.1 F 68 k 4.7 k 1 F 10 F 0.1 F 0.01 F No.6169-5/25 1 M [BASS fo = 100 Hz] [MID fo = 1000 Hz][TREBLE fo = 10000 Hz] 1 F 0.033 F 0.0033 F 330 pF 220 pF LC75384NE-R, 75384NW Pin Functions Pin No. 54 53 52 51 59 60 61 62 Pin L1 L2 L3 L4 R1 R2 R3 R4 * Single end inputs Function Notes VDD LVref RVref VDD 50 49 63 64 L5M L5P R5M R5P * Differential inputs M VDD P LVref RVref VDD 48 1 LSEL0 RSEL0 * Input selector outputs VDD 47 2 LVRIN RVRIN * Inputs for the 2-dB step volume control * These inputs must be driven from low-impedance circuits. LVref RVref * Loudness function pins. Connect the high-band compensation RC circuits between the LCT (RCT) and the LVRIN (RVRIN) pins and connect the low-band compensation RC circuits between the LCT (RCT) and LVREF (RVREF). VDD 46 3 LCT RCT 45 4 LCOM RCOM * 2-dB step volume control outputs * To reduce switching noise, each of these pins should be connected to LVREF (RVREF) through a capacitor. VDD VDD 44 5 LVROUT RVROUT * Output from the 1-dB step volume control Continued on next page. No.6169-6/25 LC75384NE-R, 75384NW Continued from preceding page. Pin No. Pin Function Equivalent circuit VDD 43 6 LTIN RTIN * Equalizer input LVref RVref 42 41 40 7 8 9 39 38 37 10 11 12 36 35 34 13 14 15 LF1C1 LF1C2 LF1C3 RF1C1 RF1C2 RF1C3 LF2C1 LF2C2 LF2C3 RF2C1 RF2C2 RF2C3 LF3C1 LF3C2 LF3C3 RF3C1 RF3C2 RF3C3 * Connections for the capacitors for the equalizer's F1 band filter. The low band compensation capacitors must be connected between the following pins: LF1C1 (RF1C1) and LF1C2 (RF1C2) LF1C2 (RF1C2) and LF1C3 (RF1C3) * Connections for the capacitors for the equalizer's F2 band filter. The low band compensation capacitors must be connected between the following pins: LF2C1 (RF2C1) and LF2C2 (RF2C2) LF2C2 (RF2C2) and LF2C3 (RF2C3) * Connections for the capacitors for the equalizer's F3 band filter. The low band compensation capacitors must be connected between the following pins: LF3C1 (RF3C1) and LF3C2 (RF3C2) LF3C2 (RF3C2) and LF3C3 (RF3C3) C2 C3 LVref RVref VDD C1 VDD 33 16 LTOUT RTOUT * Equalizer output VDD 32 17 LFIN RFIN * Fader block inputs * These inputs must be driven from low-impedance circuits. 31 30 18 19 LFOUT LROUT RFOUT RROUT * Fader block outputs. The front and rear outputs can be attenuated independently. The attenuation is the same in the left and right channels. VDD 57 Vref * VDD/2 voltage generator block. A capacitor with a value of about 10 F must be inserted between Vref and AVSS (VSS) to reduce power supply ripple. VDD 55 58 LVref RVref * Internal analog system ground * These pins must be handled as shown in the sample application circuit. LVref RVref Continued on next page. No.6169-7/25 LC75384NE-R, 75384NW Continued from preceding page. Pin No. 56 Pin VDD * Power supply Function Equivalent circuit 27 29 22 DVSS LAVSS RAVSS * Logic system ground * Analog system ground LC75384NE-R * Band limiting for the zero cross detection circuit 28 21 LZCLP RZCLP * These pins are normally left open. * These pins are unused in the LC75384NW version and must be left open. VDD LVref RVref VDD * External muting control 23 MUTE * When this pin is set to the VSS level, the fader volume block is forcibly set to -. * Used for the zero cross circuit no-signal timer function. 20 TIM If a zero cross signal does not occur between the point when data is loaded and the point when the timer times out, the data will be stored forcibly when the timer times out. VDD 26 25 CL DI * Serial data and clock inputs used for device control VDD 24 CE * Chip enable input. Data is written to the internal latch when this pin goes from high to low. The analog switches then operate. Data transfers are enabled when this pin is high. No.6169-8/25 LC75384NE-R, 75384NW Internal Equivalent Circuits Selector Block Equivalent Circuit R3 = 22.65 k R4 = 25 k LVref L5M R1 = 22.65 k L4 50 k 3.75dB LVref L3 50 k 6.25dB LVref L2 50 k 8.75dB LVref L1 50 k 11.25dB LVref INMUTE SW 1.835 k 12.5dB 1.589 k 13.75dB LVref Total resistance: 50 k L5P LSELO 0dB R2 = 25 k 1.25dB 5.804 k 2.50dB 5.026 k 4.532 k 5.00dB 3.769 k 3.264 k 7.50dB 2.826 k 2.447 k 10.0dB 2.119 k 6.702 k 1.376 k 15.0dB 1.192 k 16.25dB 1.032 k 17.5dB 0.894 k 18.75dB 5.774 k LVref The right channel is identical. Unit (Resistance: ) No.6169-9/25 LC75384NE-R, 75384NW 2-dB Step Volume Control Block Equivalent Circuit LVRIN 41.139 k 32.678 k 25.957 k 20.618 k 16.378 k * The total resistance above the tap is 195 k 0dB -2dB -4dB -6dB -8dB -10dB -12dB -14dB -16dB -18dB -20dB -22dB -24dB -26dB -28dB -30dB -32dB -34dB -36dB -38dB -40dB -42dB -44dB -46dB -48dB -50dB -52dB -54dB -56dB -58dB -60dB -62dB -64dB -66dB -68dB -70dB -72dB -74dB -76dB -78dB - dB To the left channel 1-dB step block 13.009 k 10.334 k 8.208 k 6.520 k 5.179 k 4.114 k 3.268 k 2.596 k 2.062 k 1.638 k 1.301 k 6.344 k 5.040 k LCT The right channel is identical. Unit (Resistance: ) 5.750 k 4.003 k 3.180 k 2.526 k 2.006 k 1.594 k 1.266 k 1.006 k 0.799 k 0.634 k 0.504 k 0.400 k 0.318 k 0.253 k 0.201 k 0.159 k 0.127 k 0.101 k 0.080 k 0.063 k 0.050 k 0.040 k 0.154 k LVref * The total resistance below the tap is 30.847 k No.6169-10/25 LC75384NE-R, 75384NW 1-dB Step Volume Control Block Equivalent Circuit From the left channel 2-dB volume control block 5.438 k Switch used for initial setup 0 dB -1 dB LVROUT 44.564 k - dB Vref Switch used for initial setup Unit: (Resistance : ) Total resistance: 50 k The right channel is identical. LCOM Three-Band Graphic Equalizer Block Equivalent Circuit Diagram LTIN 50 k LVref 5.1 k 5.1 k LTOUT 0.711 k 0.648 k 1.015 k 1.751 k 3.595 k 10.977 k 12 dB 10 dB 8 dB 6 dB 4 dB 0.711 k 0.648 k 1.015 k 1.751 k 3.595 k 10.977 k 12 dB 10 dB 8 dB 6 dB 4 dB 0.711 k 0.648 k 1.015 k 1.751 k 3.595 k 10.977 k 12 dB 10 dB 8 dB 6 dB 4 dB 68 k 68 k LVref LVref LVref 1k 1k LVref LVref 1k LF1C1 LF1C2 LF1C3 Unit: (Resistance : ) LF2C1 LF2C2 LF2C3 LF3C1 LF3C2 LF3C3 No.6169-11/25 LVref 68 k LC75384NE-R, 75384NW The external capacitors C1 and C2 used with the LC75384W form the structural element of the simulated inductor implemented by the IC. This section present the equivalent circuit and the method for calculating the constants required to obtain the desired center frequency. (A) Simulated inductor equivalent circuit R3 + - CUT R3 BOOST R4 C1 C2 R2 R1 - + R1 = 1 k R2 = 68 k R3 = 5.1 k Zo: Impedance at resonance Zo (B) Calculation Specifications: 1. Center frequency: F0 = 100 Hz 2. Q at maximum boost: Q+12dB = 0.9 1. Determine the sharpness, Q0, of the simulated inductor itself. Q0 = (R1 + R4) x Q+12dB 1.5399 R1 2. Determine C1. C1 = 1/2F0R1Q0 1 (F) 3. Determine C2. C2 = Q0/2F0R2 0.036 (F) Note: * See the equivalent circuit diagram for the tone control block on page 11 for details on the internal resistor. No.6169-12/25 LC75384NE-R, 75384NW Fader Volume Control Block Equivalent Circuit S1 LFIN 5.437 k 4.846 k -2dB 8.169 k -4dB 6.489 k -6dB 5.154 k -8dB 4.094 k -10dB 3.252 k -12dB 2.583 k -14dB 2.052 k -16dB 1.630 k -18dB 1.295 k -20dB 3.419 k -30dB 1.300 k -45dB 0.231 k -60dB 0.050 k - dB LVref If data that sets the main volume control 1-dB step circuit to - is sent to the device, switches S1 and S2 will be opened (off) and switches S3 and S4 will be closed (on). Unit: (Resistance : ) Total resistance: 50 k When FADER is set to 1, S2 and S3 will be turned on. When FADER is set to 0, S1 and S4 will be turned on. 0dB -1dB S3 LFOUT S2 S4 LROUT No.6169-13/25 LC75384NE-R, 75384NW Control System Timing and Data Format The LC75384NE-R/NW are controlled by applying the stipulated data to the CL, DI, and CE pins. The data consists of a total of 52 bits, of which 8 bits are the device address and 44 bits are the actual control data. CE DI CL B0 B1 B2 B3 A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D38 D39 D40 D41 D42 D43 CE 1 s min 1 s 1 s 1 s min min min 1 s min CL DI 1 s TDEST * Address code (B0 to A3) The LC75384NE-R/NW have an 8-bit address codes, and can be used along with other ICs that support the Sanyo CCB serial bus. Address code (LSB) B0 1 B1 0 B2 0 B3 0 A0 0 A1 0 A2 0 A3 1 (81HEX) * Control code allocation Input switching control D0 0 1 0 1 0 0 1 D3 D1 0 0 1 1 0 1 1 D2 0 0 0 0 1 1 1 L1 (R1) L2 (R2) L3 (R3) L4 (R4) L5 (R5) IC test values. These values must not be used during normal operation. Setting IC test bit. This bit must be set to 0 during normal operation. No.6169-14/25 LC75384NE-R, 75384NW Input gain control D4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 dB +1.25 dB +2.50 dB +3.75 dB +5.00 dB +6.25 dB +7.50 dB +8.75 dB +10.0 dB +11.25 dB +12.5 dB +13.75 dB +15.0 dB +16.25 dB +17.5 dB +18.75 dB Operation No.6169-15/25 LC75384NE-R, 75384NW Volume Control D8 D9 D10 D11 D12 D13 D14 D15 Operation 1-dB step 0 1 0 dB -1 dB 2-dB step 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dB -2 dB -4 dB -6 dB -8 dB -10 dB -12 dB -14 dB -16 dB -18 dB -20 dB -22 dB -24 dB -26 dB -28 dB -30 dB -32 dB -34 dB -36 dB -38 dB -40 dB -42 dB -44 dB -46 dB -48 dB -50 dB -52 dB -54 dB -56 dB -58 dB -60 dB -62 dB -64 dB -66 dB -68 dB -70 dB -72 dB -74 dB -76 dB -78 dB Mute 1 1 1 1 1 1 0 - No.6169-16/25 LC75384NE-R, 75384NW Three-band equalizer control D16 D20 D24 0 1 0 1 0 1 0 1 0 1 0 1 0 D17 D21 D25 1 0 0 1 1 0 0 0 1 1 0 0 1 D18 D22 D26 1 1 1 0 0 0 0 0 0 0 1 1 1 D19 D23 D27 0 0 0 0 0 0 0 1 1 1 1 1 1 f1 band f2 band f3 band +12 dB +10 dB +8 dB +6 dB +4 dB +2 dB 0 dB -2 dB -4 dB -6 dB -8 dB -10 dB -12 dB Fader Volume Control D28 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D29 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D30 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D31 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 dB -1 dB -2 dB -4 dB -6 dB -8 dB -10 dB -12 dB -14 dB -16 dB -18 dB -20 dB -30 dB -45 dB -60 dB - Operation Channel Selection Control D32 0 1 0 1 D33 0 0 1 1 Setting Left and right together. This is the mode set up initially RCH LCH Left and right together Fader Rear/Front Control D34 0 1 Rear Front Setting No.6169-17/25 LC75384NE-R, 75384NW Loudness Control D35 0 1 Off On Setting Zero Cross Control D36 0 1 D37 0 1 Data is written when a zero cross is detected The zero cross detection operation is disabled and data is written on the falling edge of the CE signal Setting Zero Cross Signal Detection Block Control D38 0 1 0 1 D39 0 0 1 1 D40 0 0 0 0 D41 0 0 0 0 Selector Volume Tone Fader Setting Test Mode Control D42 0 D43 0 Setting These IC test mode control bits must be set to 0 No.6169-18/25 LC75384NE-R, 75384NW Usage Notes Data Transmission after Power Is First Applied * When power is first applied, the state of the internal analog switches will be undefined. Applications that use this IC must include external circuits to provide muting until control data has been transferred to the IC. * After power is first applied, applications should send initial setup data to stabilize the bias levels in each of the IC circuit blocks in a short time. 1. The time between initial setup mode and the first actual data settings * Applications should send the initial setup data as soon as VDD rises above 6 V. * After the LCOM and RCOM pins have stabilized at the Vref level, applications should set the initial data. The time required for the capacitors connected to the LCOM and RCOM pins to be charged to the Vref level The 1/2 VDD level VREF VDD = 6 V VDD = 9 V (TYP) VDD Data Initial setup mode First data for the left channel First data for the right channel These operations clear initial setup mode 2. Procedure for setting up initial setup mode * When D32 and D33 are set to 00, the IC's internal initial setup switch is turned on and the IC goes to quick charge mode. At this time the other data (D0 to D31 and D34 to D43) will also be set up for the left and right channels at the same time. This means that applications can set up the states of the various blocks at the same time as specifying initial setup mode. 3. Procedure for clearing initial setup mode * Initial setup mode is cleared by setting D32 and D33 to any value other than 00. In other words, any normal left or right channel specification will turn the internal initial setup switch off and clear quick charge mode. No.6169-19/25 LC75384NE-R, 75384NW Zero Cross Switching Circuit Operating Principles * The LC75384NE-R/NW include functions for switching the place where the zero cross comparator operates and thus allows applications to select the optimal detection location for the block for which the control data is updated. Basically, switching noise will be minimized if the signal immediately following the block for which the control data is updated is input to the zero cross comparator. Thus the detection location must be changed for each data update operation. Another issue is the point that if the signal amplitude is lower than the detection sensitivity (a few mV rms) of the zero cross comparator (for example if the volume is set to a low level), the switching noise can be minimized further by selecting a point before the volume control block, namely the selector block output, as the zero cross detection point than by simply waiting for the data write to occur due to the overflow of the zero cross timer. For example, if the volume block input is 1 V rms, and the volume is set to -40 dB or lower, the output will be under 10 mV rms. In this case, detecting at the selector output block will result in lower switching noise. Selector Volume Tone Fader Switch Zero cross comparator Zero Cross Detection Circuit Zero Cross Switching Control Procedure * The zero cross switching control procedure consists of first setting the zero cross detection mode with the zero cross control bits (D36 and D37 = 0) and then, after specifying the detection block (with bits D38, D39, D40, and D41), sending the control data. Since these control bits are latched first immediately after the data is sent, i.e. on the falling edge of the CE signal, it is possible to both set the IC mode as well as specify zero cross switching operation in a single data transfer, even when updating the volume and other data. The following presents an example of the control operation when updating the volume block data. D36 0 D37 0 D38 1 D39 0 D40 0 D41 0 Zero cross detection mode specification Volume block setting Zero Cross Timer Setting * When the input signal has a level lower than the detecting sensitivity of the zero cross comparator, or consists only of extremely low frequencies, the zero cross detection circuit will remain in the state in which it cannot detect a zero cross and the data will not be latched during that period. The zero cross timer specifies a time after which the data will be latched forcibly in states where a zero crossing cannot be detected. The time is determined by the lowest frequency for which a zero cross can be detected reliably. For example, if the timer is set to 25 ms: T = 0.69 CR If C is taken to be 0.033 F, then R will be: R= 25 x 10-3 0.69 x 0.033 x 10-6 1.1 M No.6169-20/25 LC75384NE-R, 75384NW Notes on Serial Data Transfer 1. The CL, DI, and CE pin signal lines must be covered (and thus shielded) by the ground pattern or formed from shielded cable to prevent the high-frequency digital signals on those lines from entering the analog system. 2. The LC75384NE-R/NW data formats consist of 8 bits of address and 44 bits of data. When the data is sent in units of 8 bits each (i.e. 48 bits are actually sent), use the data transfer technique shown in figure 1. LC75384NE-R/NW data receptions in 8-bit units X X X X D0 D1 D2 D3 ....... D36 D37 D38 D39 D40 D41 D42 D43 Test mode control X: don't care Dummy data Input switching control 3. During CCB transfers, this IC detects address matches on the rising edge of the CE signal. Therefore, applications must set the CL signal low and then set it high at this time. No.6169-21/25 LC75384NE-R, 75384NW Output Level Characteristics 20 10 VDD = 9 V, VSS = 0 V, VIN = 0 dBV Flat overall Input = L1, Output = LFOUT Settings: the 0 dB to -54 dB positions (in -2 dB steps) 0 -10 -20 -30 -40 -50 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 -26 -28 -30 -32 -34 -36 -38 -40 -42 -44 -46 -48 -50 -52 -54 Level -- dB -60 10 2 3 5 7 100 2 3 5 7 1k 2 3 5 7 10 k 2 3 5 7 100 k Frequency, f -- Hz Loudness Characteristics 20 VDD = 9 V, VSS = 0 V, VIN = 0 dBV Flat overall Input = L1, Output = LFOUT Settings: the 0 dB to -54 dB positions (in -2 dB steps) 10 0 -10 -20 -30 -40 -50 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 -26 -28 -30 -32 -34 -36 -38 -40 -42 -44 -46 -48 -50 -52 -54 Output level -- dBV -60 10 2 3 5 7 100 2 3 5 7 1k 2 3 5 7 10 k 2 3 5 7 100 k Frequency, f -- Hz No.6169-22/25 LC75384NE-R, 75384NW Main Volume Step Characteristics 0 -10 -20 20 18 16 14 Gain Step Characteristics VDD = 9 V VSS = 0 V VIN = -20 dBV f = 1 kHz VDD = 9 V VSS = 0 V VIN = 0 dBV f = 1 kHz Output level -- dB Attenuation -- dB -30 -40 -50 -60 -70 -80 -90 12 10 8 6 4 2 - -70 -60 -50 -40 -30 -20 -10 0 0 0 2 4 6 8 10 12 14 16 18 20 Step -- dB Graphic equalizer block Step -- dB Graphic equalizer block Main volume block Main volume block Input gain block Input gain block Fader block V Fader block V Fader Volume Step Characteristics 0 THD - Frequency Characteristics Total harmonic distortion, THD -- % 1.0 7 5 3 2 0.1 7 5 3 2 0.01 7 5 3 2 23 5 7100 23 5 71 k 23 5 7 10 k 2 3 5 7 100 k -10 Fader volume attenuation -- dB -20 -30 -40 -50 -60 -70 -80 VDD = 9 V VSS = 0 V VIN = 0 dBV f = 1 kHz VDD = 9 V, VSS = 0 V, VIN = -10 dBV Input = L1, Output = LFOUT 80-kHz low pass weighting - -70 -60 -50 -40 -30 -20 -10 0 0.001 10 Step -- dB Frequency, f -- Hz Graphic equalizer block Graphic equalizer block Main volume block Main volume block Input gain block Input gain block Fader block V Fader block THD METER No.6169-23/25 LC75384NE-R, 75384NW THD - Input Level Characteristics Total harmonic distortion, THD -- % Total harmonic distortion, THD -- % 1.0 7 5 3 2 0.1 7 5 3 2 0.01 7 5 3 2 -35 -30 -25 -20 -15 -10 -5 0 5 10 THD - Supply Voltage Characteristics 1.0 7 5 3 2 0.1 7 5 3 2 VDD = 9 V, VSS = 0 V 80-kHz low pass weighting With VR set to the 0 dB position VSS = 0 V 80-kHz low pass weighting f= f= 20 1k kH z Hz 0.01 7 5 3 2 4 VI N=0 dBV V ,f= IN = VI 20 k N = -1 Hz 0d 0 dB BV V, f V = 20 ,f IN = kHz =1 -10 kH z dB V, f= 1k Hz 5 6 7 8 9 10 11 12 13 0.001 -40 0.001 Input level, VIN -- dBV Supply voltage -- V Graphic equalizer block Main volume block Main volume block Input gain block Input gain block F1 Band Characteristics 0 -5 -10 Fader block F2 Band Characteristics 0 -5 -10 VDD = 9V,VSS = 0V,VIN = -20dBV Input = L1, Output = LF OUT VDD = 9V,VSS = 0V,VIN = -20dBV Input = L1, Output = LF OUT Level -- dB -20 -25 -30 -35 -40 10 Level -- dB -15 -15 -20 -25 -30 -35 -40 10 23 5 7100 23 5 7 1k 23 5 7 10k 23 5 7100k 23 5 7100 23 5 7 1k 23 5 7 10k Fader block THD METER Graphic equalizer block THD METER 23 5 7100k Frequency -- Hz Frequency -- Hz F3 Band characteristics 0 -5 -10 VDD = 9V,VSS = 0V,VIN = -20dBV Input = L1, Output = LF OUT Level -- dB -15 -20 -25 -30 -35 -40 10 23 5 7100 23 5 7 1k 23 5 710k 23 57 100k Frequency -- Hz No.6169-24/25 LC75384NE-R, 75384NW Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of May, 2000. Specifications and information herein are subject to change without notice. PS No.6169-25/25 |
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