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| T S M44C510 Keyboard Application TELEFUNKEN Semiconductors 06.96 T S Table of Contents Introduction.................................................................................................................................... 1 TEMIC Semiconductors............................................................................................................... 1 TEMIC - a Microcontroller Specialist......................................................................................... 1 The History of MARC4 ............................................................................................................... 1 The MARC4 Family .................................................................................................................... 1 Members of the MARC4 Family .................................................................................................. 3 M43C505 - Low-Current 3- and 5-V Solution for Consumer Applications ............................... 3 M44C090/092 - Low-Current Solution for Wireless Communication........................................ 4 M44C260 - Perfect Solution for Security and Access Control ................................................... 5 M44C510 - Flexible and Powerful Solution for Embedded Control .......................................... 6 M44C588 - Versatile High-End Controller for General Purposes .............................................. 7 M44C636 - Perfect Solution for Low-Current Applications....................................................... 8 Key Application Chart ................................................................................................................. 9 M44C510 Keyboard Application................................................................................................ 10 Keyboard Scanning and Code Generation ................................................................................. 10 Program Description for Keypad Handling and Code Generation ............................................ 11 Make/Break/Typematic Timing Control.................................................................................... 12 Communication between PC and Keyboard .............................................................................. 14 Command Protocol..................................................................................................................... 14 Appendix....................................................................................................................................... 17 MARC4 Product Overview........................................................................................................ 17 Development Tools .................................................................................................................... 18 Data Sheet M44C510....................................................................................................................19 TELEFUNKEN Semiconductors 06.96 T S Introduction TEMIC Semiconductors TEMIC is the microelectronics enterprise of Daimler-Benz. TEMIC's Semiconductor division is a leading manufacturer of applicationspecific, value-adding integrated circuits for communication equipment, automotive and industrial systems, computers and broadcast media. Discrete semiconductors and optoelectronic devices make the product range complete. With a technology portfolio which includes bipolar, BiCMOS, GaAs, CMOS and DMOS processes, TEMIC Semiconductors provides a unique set of components and solutions. The History of MARC4 TEMIC Semiconductors started developing the MARC4 in 1986, based on experience with the former 4-m CMOS core e3101. The aim was to design an easy-to-use, high-performance, 4-bit controller by selecting a high-level language for programming and to provide highly advanced and efficient development tools. Special effort was spent to realize a modular concept with a very small core design. After developing MARC4 products in 3-m and even 1.5-m technologies, TEMIC started working with external foundries in 1989. Since 1993, the MARC4 family has been based completely on external foundries using 2-m down to 0.6-m technologies (volatile/non-volatile). TEMIC - a Microcontroller Specialist TEMIC is since twenty years a technology leader in applications requiring minimum current consumption such as watches and clocks, and has ten years of experience regarding the design of low-power microcontrollers. TEMIC offers 4-bit, 8-bit, extended 8-bit and 32-bit controllers. Our MARC4 products are high-sophisticated and wellexperienced as they have been adapted to ten different technologies up to now. Choosing TEMIC as a partner means, you will have one independent source for components - transistors, diodes, optoelectronic devices including LEDs and IrDA components, integrated circuits and smart-power devices. Due to our state-of-the-art facilities worldwide, TEMIC's production resources are more than sufficient. TEMIC guarantees excellent application support which will reduce your time-tomarket. The available software library for programming as well as the detailed documentation (see appendix) are free of charge. The MARC4 Family TEMIC offers a complete family of cost-effective, single-chip CMOS microcontrollers, based on a 4-bit CPU core designed for 1.5-, 3- and 5-V applications. The modular MARC4 architecture is HARVARD-like, high-level language oriented and best designed to realize high-integrated microcontrollers with a variety of application- or customer-specific, on-chip peripheral combinations. The MARC4 controller's low voltage and low power consumption is perfect for hand-held and battery-operated applications. The standard members of the MARC4 family have selected peripheral combinations for a broad range of applications. Programming is supported by an easy-to-use, PC-based software development system with a high-level language qFORTH compiler and an emulator board. The stack-oriented microcontroller concept enables the qFORTH compiler to generate compact and efficient MARC4 program codes. TELEFUNKEN Semiconductors 06.96 1 T S Applications The very small 4-bit core combined with a versatile peripheral cell library enables the design of application-specific microcontrollers. * * * * * * * * * * * * * * * * 32-kHz sub-clock A/D converter Comparator EEPROM External interrupts High-current ports LCD drivers Low battery detection Power-on-reset Prescaler Programmable I/Os Reset input Serial I/O Timers/counters Various system oscillators Watchdog timer 256 x 4-bit of RAM directly addressable Up to 9 KBytes of ROM Low-voltage operating range Low power consumption Hardware optimized to fit with high-level language qFORTH * Programming and debugging is supported by an integrated software development system Programming in the high-level language qFORTH is simple, easy to understand and advantageous. From the hardware side, the expression and return stack have a user-programmable size, the qFORTH instructions correspond directly to the machine words and therefore, the program executes fast. The software code is compact and the sub-routine nesting is nearly unlimited. In addition, programming is easy and safe due to the possibility of combining existing software modules. Clock Sleep Reset * * * * * MARC4 CORE Features * Very small 4-bit core combined with versatile peripheral cell library * Various on-chip peripheral combinations available * HARVARD structure - 3 parallel-operating buses (pipelining) enhance computing power (2 clock cycles per instruction only) * 72 RISC-like 8-bit instructions * Stack architecture offers customized stack size and 'unlimited' subroutine nesting * Unique 8 level interrupt controller leads to a very short (3 cycle) interrupt response time * 'Brown-out' function and internal PowerOn-Reset (POR) make external components unnecessary * Small 4-bit periphery bus offers extraordinary flexibility ROM X PC Y SP RP RAM 256 x 4 bit Instruction bus Instruction decoder Memory bus TOS Interrupt controller CCR I/O bus ALU I/O ports Timer Applicationspecific peripherals Interrupt inputs On-chip peripheral modules 94 8711 MARC4 core 2 TELEFUNKEN Semiconductors 06.96 Members of the MARC4 Family M43C505 - Low-Current 3- and 5-V Solution for Consumer Applications * * * * * * * * * * Wide supply voltage range (2.4 V to 5.5 V) Very low current consumption 4096 x 8 ROM, 253 x 4 RAM 16 programmable I/Os 2-MHz fast system clock (1 MIPS) 32-kHz crystal oscillator 20 x 4 LCD temp.-compensated drivers 2 external/ 3 internal interrupt sources Prescaler/ interval timer Internal POR and brown-out T S Existing software modules for time keeping, calendar, stop watches, display drivers for various multiplex rates, accurate dual-slope temperature measurement and interface software for TEMIC's radio-controlled clock receivers are part of the comprehensive qFORTH software library. A power-saving sleep- and stop mode increases significantly battery life time in hand-held applications while offering 1 MIPS computing power during active time. Internal POR, oscillator and pull-up/-down resistors simplify PCB layout and minimize system costs. Software is free of charge for these applications which increases the confidence level and reduces the time-to-market for new developments. RST VDD V SS Existing applications comprise temperature measurement and -control, battery charging, bicycle computers, timers, radio-controlled clocks and CD players. TST1 TST2 TCL Clock generation Sleep RAM address registers X Y SP RP Power-on reset ROM 4096 x 8 bit Program counter RAM 256 x 4 bit Instruction bus Interrupt controller Memory bus Instruction decoder I/O bus CCR TOS ALU I/O I/O + strobes I/O 4 4 4 Port 0 +NST, OD Port 4 Inputs External interrupts LCD driver Osc./ prescaler 4 Port 5 INT7 INT2 Buzzer COM0...3 S1...S20 32 kHz Port 1 M43C505 TELEFUNKEN Semiconductors 06.96 3 T S - Low-Current M44C090/092 Solution for Wireless Communication * 4 mask-selectable system-clock sources, crystal oscillator, external clock, RC oscillator with/ without external resistor * Wide supply voltage range (1.8 V to 6.2 V) * Very low sleep current * 2/4 + 0.5 KByte ROM, 128 x 4 bit RAM * 512-bit EEPROM optional * 12/20 programmable I/Os * 32-kHz crystal oscillator (C092 only) * Up to 5 external/ 6 internal interrupt sources * Prescaler/ interval timer * 2-wire serial interface * Multi-functional timers/ counters incl. IR/ RF remote control carrier generation * Watchdog, POR and brown-out function * OTP M48C092 * SO8 package (M44C090) The two MARC4 products M44C090 and M44C092 offer highest integration for IR and VDD VSS RF data communication and remote control. These controllers are optimized for the requirements of the transmitter as well as the receiver side. TEMIC's system know-how was used to integrate the modulator into the M44C090 and the modulator as well as the demodulator for commonly-used wireless protocols into the M44C092. Both controllers perfectly match the RF front end device U2740B and the IR driver chip U426B. This - along with the very small SSO package and the approach to minimize the number of external components - leads to extremely compact remote control units, e.g., for electronic keys. Finally, the very low current consumption and the extended supply voltage range optimizes battery life time. Development is supported with the OTP M48C092 which covers the features of the M44C092 and both includes the performance of the M44C090. OSC1 OSC2 Brown-out protection, reset Voltage monitor External input VMI BP00 BP10 BP20 BP21/TE BP22 BP23 Port 0 Port 1 RC osc. Crystal 32-kHz osc. cryst. osc. Clock managment Timer 1 watchdog timer Timer 2 - 4+8 bit Modulator 2 ROM 2/4 k x 8 bit RAM 128 x 4 bit T2O SD Serial interface SC Data dir. Port 2 MARC4 4-bit CPU Core Modulator 3 demodulator T3O Timer 3 - 8 bit Timer/counter T3I I/O-Bus Data dir. + alt. function Port 4 Data dir. + interrupt control Port 5 Data dir. + alt. funct. Port 6 M4xC092/ M4xC090 BP40/VMI BP41/SC BP42/ T2O BP43/SD BP50/INT BP51/INT BP53/INT BP52/INT M44C090/092 4 TELEFUNKEN Semiconductors 06.96 BP60/T3I BP63/T3O M44C260 - Perfect Solution for Security and Access Control * Wide supply voltage range (2.4 V to 6.2 V) * Very low sleep current * 4 KByte ROM, 256 x 4 bit RAM * 128 bit EEPROM on board * 18 programmable I/Os * 4.2-MHz fast system clock (FLL) * 32-kHz crystal oscillator * 6 interrupt sources * Prescaler/ interval timer * Multi-functional timers/ counters incl. IR remote control carrier generation * Watchdog and POR * OTP M48C260 The M44C260 is specially optimized for IR remote control and security and access control applications, e.g., for automotive and industrial applications. The on-board 128-bit EEPROM offers the capability to store and change identifiers as well as security codes. Any application which requires the ability to store a small amount of data will also benefit. The multi-function timer/counter modules which are also on-board include modes to directly generate the signal for an IR transmitter device such as TEMIC's U426B. The wide supply voltage range combined with the very small current consumption increases battery life time in mobile applications. The OTP M48C260 simplifies and reduces the development time. For detailed information please refer to TEMIC's "Automotive Safety and Convenience Data Book". T S NWP VSS VDD NRST TE TCL OSCIN OSCOUT 94 9038 Reset Test Sleep Clock ROM or EEPROM EEPROM 16 x 8 bit 4K x 8 bit RAM 256 x 4 bit Timer 1 Timer 2 Timer B Watchdog Intervall timer MARC4 4-bit CPU core Timer A I/O bus I/O I/O I/O I/O Interrupt inputs Input Port 4 INT6 Port 0 Port 1 Port 2 Port 3 IP40 IP43 TA TB M44C260 TELEFUNKEN Semiconductors 06.96 5 T S and Powerful M44C510 - Flexible Solution for Embedded Control * 4 mask-selectable system-clock sources, crystal oscillator, ceramic resonator, RC oscillator with/ without external resistor * Wide supply voltage range (2.4 V to 6.2 V) * Very low current consumption * 4 KByte ROM, 256 x 4 bit RAM * 32 bitwise-programmable I/Os * High-current outputs * 32-kHz crystal oscillator * 10 external and 4 internal interrupt sources * Prescaler/ interval timer * Two 8-bit multi-functional timers/ counters * Watchdog timer, internal POR and brown-out * Minimum external components * Very small package (SSO44) The M44C510 presents a solution for embedded control applications. Various mask options provide an optimum price-performance ratio for the system. Due to the pull-up/-down, push-pull and opendrain functions of the bit-wise programmable I/Os, external components become unneccessary. LEDs and relays can directly be connected to the M44C510 by using up to eight I/Os driving 20 mA each. Mask selectable clock sources cover a wide range of application requirements. Watchdog, POR and brown-out function supervise correct operation. More than ten timer/counter modes offer D/A conversion, event counting, 16-bit modes and even melody modes. The wide supply voltage range along with the very small current consumption supports battery-powered systems. Software modules available include keyboard software, LCD and LED display driver, serial port protocols, radio-controlled clock decoders and timer as well as temperature measurement modules. V SS VDD TE SCLIN SCLOUT NRST OSCIN OSCOUT AVDD TIM1 Test Sleep System clock Master reset Real-time clock ROM 5 K x 8 bit RAM 256 x 4 bit Timer/ counter Watchdog Prescaler Timer 1 Timer 0 Melody & buzzer MARC4 4-bit CPU core I/O bus I/O I/O I/O I/O I/O Interrupt & reset I/O Interrupt I/O I/O Interrupt I/O 96 11515 Port 0 Port 1 Port 5 Port 7 Port A Port B Port C Port 6 Port 4 M44C510 6 TELEFUNKEN Semiconductors 06.96 M44C588 - Versatile High-End Controller for General Purposes * Various mask-selectable system clock sources to define application-specific system price/ performance ratio * Dual clock mode for minimum current consumption * Wide supply voltage range (1.8 to 6.2 V) * 9 KByte ROM, 512 x 4 bit RAM * Up to 32 I/Os incl. high-current ports * 32-kHz crystal oscillator * Up to 32 x 4 LCD segments * Prescaler * 8 external and 5 internal interrupts * Watchdog, POR and low battery detection for enhanced system security * Synchronous 8-bit serial port * Multi-function timer/ counter incl. IR/ RF remote control carrier generation 4 MHz XOUT XIN High-end, battery-powered consumer applications such as bicycle computers, feature watches, diver computers and high-end, radiocontrolled clocks/watches which all require both computing power and low current consumption will benefit from the M44C588. The dual clock mode and core frequencies of 4 MHz (2 MIPS) on the one hand and 32 kHz slow operation/ sleep mode (consuming only micro-amps) on the other hand make the M44C588 the best solution for these tough requirements. The programmable I/Os with pull-up/-down options, integrated oscillators, 20-mA drive capability, internal watchdog, POR and low battery detection minimize the number of system components, resulting in reduced system costs and PCB size. The integrated temperature-compensated display drivers for up to 128 LCD segments enable even sophisticated display solutions. Data transfer to external storage devices such as serial EEPROMs is simplified by the serial port. RST VDD VSS T S TE Clock generation Sleep Power-on reset 1024 x 8 bit Test ROM RAM address registers X ROM Y 9216 x 8 bit SP RP Program counter Memory bus Instruction decoder I/O bus CCR TOS RAM 256 x 4 bit Instruction bus Interrupt controller ALU I/O Watchdog I/O I/O Mot. Timer/ Key int. driver counter 4 Port 0 Port 1 Port 5 4 Port 4 T1 COM0...3 INT7 INT2 S1...(S20-S32) 32 kHz Ext. interrupts LCD driver Base timer Sub-osc. AVDD 4 4 256 x 4 bit peripheral RAM M44C588 TELEFUNKEN Semiconductors 06.96 7 T S Solution for LowM44C636 - Perfect Current Applications * 1.2 V to 2.2 V/ 1.8 V to 3.6 V (mask opt.) * < 1 A sleep mode current, 200 A active current * On-chip RC system clock oscillator * 4 KByte ROM, 253 x 4 bit RAM * 16 programmable I/Os * 32-kHz crystal oscillator * 20 x 4 temperature-compensated LCD driver segments * Prescaler/ interval timer * Two independent 8-bit timers/ counters * Watchdog and POR The M44C636 is pushing the limits of lowcurrent consumption to the values of the dis TST1 TST2 TCL charge of batteries. Combining sleep and active periods, system currents of less than 2 A can be designed. The M44C636 therefore fits exactly to applications such as feature watches, radio-controlled clocks/watches, timers powered by back-up capacitors and even telecom applications such as telephone-rate counters directly powered by transmission lines. Mask options adjust the extended supply voltage range of the M44C636 to 1.5-V or 3-V batteries. For 3-V applications, an internal voltage regulator powers the core, reducing the active current down to 200 A. Two multi-function timers/counters and motor output drivers support 3-V watch applications even including motor-pulse chopping. Internal watchdog, brown-out function and POR supervise correct operation. VDD VSS NRST Clock generation ROM 4096 x 8 bit Program counter Instruction bus Interrupt controller I/O + strobe Sleep Power-on reset WD_OUT RAM address registers X RAM Y 253 x 4 bit SP RP Memory bus CCR Instruction decoder I/O bus TOS ALU I/O WD_OUT Watchdog 4 4 Inputs key int. 4 I/O 4 PORT 4 Timer/ counter External interrupts Interval timer LCD driver PORT 1 PORT 0 PORT 5 OD TIM1 INT7 INT2, BUZZER S01...20COM0... 32 kHz M44C636 8 TELEFUNKEN Semiconductors 06.96 Key Application Chart MARC4 Product M43C505 Key Applications Temperature measurement Altitude and distance meter Battery charger/ shaver Remote control Access control/ security T S M44C090/092 M44C260 M44C510 White goods, industrial control RC clocks/ feature watches Keyboard controller Bicycle computer, diver computer high-end RC clocks/ watches Telecom applications Timer/ blind control RC clocks/ feature watches M44C588 M44C636 TELEFUNKEN Semiconductors 06.96 9 T S 10 F Scroll Shift M44C510 Keyboard Application 6 12 24 23 22 21 29 30 31 32 20 19 18 17 10 9 8 7 5 4 3 2 40 39 38 37 ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 COL0 COL1 COL2 COL3 COL4 COL5 COL6 COL7 COL8 COL9 COL10 COL11 COL12 COL13 COL14 COL15 SYSCL [MHz] 2.75 2.70 2.65 2.60 2.55 2.50 2.45 2.40 2.35 2.30 2.25 0 10 20 30 40 50 60 70 80 90 13 Num 14 +5 V PC connector Clock 34 Data GND 33 200 k +/- 1% R ext = 200 k 1% VDD = 5.5 V VDD = 5,0 V VDD = 4.5 V M44C510 1 36 T [oC] Figure 1. M44C510-P40 as keyboard controller Each key has an associated Make/ Break code which is transmitted serially to the host PC. This code signals the activation or release of that particular key. The codes consist of single or multiple byte sequences. There are three different scan code sets (XT, AT, PS2) which can all be supported by the TEMIC microcontroller. The release/activation of a key is only accepted by the controller after the matrix inputs have remained stable for two consecutive scan cycles (anti-bounce guard period). All keys operate in a Typematic mode. When a key is pressed and held, the keyboard repeatedly transmits the corresponding Make code after a defined delay (Typematic Delay) with a pre-defined repetition rate (Typematic Rate). Keyboard Scanning and Code Generation A key matrix is scanned every 4 milliseconds. Scanning is performed by sequentially pulling each of the 16 column outputs in turn to a low level while the other column outputs remain high. For each column, the eight row inputs are monitored for activated keys. Each key is defined by a matrix number , a row and a column number (see figure 2). The current software handles up to eight simultaneously activated keys. If more than eight keypads are pressed, the others are ignored. The M44C510 hardware supports up to 12 simultaneously-activated keys. 10 TELEFUNKEN Semiconductors 06.96 T S ROW0 ROW1 108 106 79 126 83 107 80 81 103 101 105 100 104 102 85 86 72 75 89 95 99 97 75 123 93 91 84 90 94 92 76 122 44 57 40 26 55 42 41 27 12 11 38 24 56 53 117 28 13 9 34 20 50 49 35 21 6 5 46 110 16 1 2 31 17 37 23 51 52 36 22 7 8 118 119 10 54 39 25 29 14 61 43 116 15 120 121 32 18 134 47 45 30 112 3 48 115 114 113 4 58 124 64 60 33 19 109 125 62 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 COL0 COL1 COL2 COL3 COL4 COL5 COL6 COL7 COL8 COL9 COL10 COL11COL12COL13COL14COL15 Figure 2. Keyboard matrix Program Description for Keypad Handling and Code Generation The controller keeps track of the incoming keys using eight working register pairs. There is one pair for each of the 8 keys that can be activated at any time. Each pair consists of an 8-bit key data register for storing the key matrix row/column address, and a 4-bit key bounce register which stores the present key status and controls the anti-bounce protection. For a detailed description, see figures 3 and 4. During every scan cycle, the controller monitors the keypad matrix inputs and stores the row and column addresses of all pressed keys in a temporary scan buffer. At the end of the cycle, the monitored addresses are compared with the key addresses of active keys in the 8 key data registers. Those addresses which can not be found, (i.e., newly activated keys) are stored in an empty key data register, and the corresponding bounce state is set to 2. The associated bounce state of all matching key addresses (already activated keys) are updated to either 4 or 7 depending on whether the key was detected for the first time in the preceding TELEFUNKEN Semiconductors 06.96 scan cycle or whether it has been activated for a longer time. Finally, after this comparison phase, all bounce values are decremented and the next scan cycle is resumed. If the resultant decremented bounce state is 3, the Make code for that key is generated and stored. If, on the other hand, the bounce state decrements to 4, the corresponding Break code is similarly generated. Thus, a newly activated/ released key will generate a Make/Break code after two scan cycles. Scan-in pressed keypads Compare scan buffer with key data register. If a matching key is found, change the key bounce. Decrement all those key bounces which are different from 0 If the key bounce is 3 or 4, generate the Make and Break code and set key bounce to 6 or 0 return Figure 3. Bounce handling 11 T S bounce = 0 key detected once no key detection bounce = 2 decremented after scanning bounce = 1 key detected twice bounce = 4 decremented after scanning bounce = 3 data is sent decremented after scanning bounce = 6 key detected bounce = 7 key detected bounce = 5 no key detection bounce = 4 data is sent no key detection three, as shown in figure 5. A situation as described above can be detected by the M44C510 and a ghost key code is then generated. Case keys (Shift, Alt, Ctrl or Num Lock) also have their own Make/Break codes. Normal keys, when activated together with one or more Case keys, cause modified Make/Break codes. To handle such multi-key combinations, the controller always stores and updates the present status (active/non active) of each Case key. These are updated whenever a case key Make/Break occurs. Only certain keys can be used together with a case key and only the codes for these keys are modified in the case of a simultaneous Case key activation. All Make/Break codes are stored in an output FIFO keyboard buffer. After loading a new key code into the FIFO, the key address is stored in a Typematic pointer register and the Typematic Delay value is loaded into a Typematic counter. This then proceeds to count down unless disabled by a Break code. When time out occurs, the counter reloads with the Typematic Rate period and sets the last code, addressed by the Typematic pointer, again into the FIFO. This is repeated until the key is released and the key bounce state 4 is reached (see figure 4), whereby the Typematic Pointer is reset, the Break code put into the FIFO and the bounce state set to 0 (i.e., empty key data). A reset of the Typematic pointer disables the Typematic counter and thus the key repeat function. Figure 4. Make/Break Code generation Make/Break/Typematic Timing Control After every complete matrix scan, the controller checks detected key arrangements for so-called ghost keys. Due to the arrangement of single contact keys in the standard key matrixes, activating three keys on two orthogonal axis causes an indirect connection between two row lines. This might cause a controller to detect a further, fourth, non-activated ghost key. If this were the case, the controller would see four pressed keys instead of ROW0 ROW1 ROW2 108 106 79 103 101 105 72 75 89 93 91 84 40 26 55 38 24 56 34 20 50 depressed keys ghost key Figure 5. Generation of a ghost key 12 TELEFUNKEN Semiconductors 06.96 Keyboard scanning and 8 keys buffering No T S Key detected? Yes Ghost key? No Yes Ghost code generation Compare detected keys with key data register Return Decrement key bounces Bounce = 3 ? Yes Make code generation No Bounce = 4 ? Yes Break code generation No Delay time seting set repetition pointer set bounce = 6 No Clear repetition pointer set bounce = 0 Repeats for n detected keys Typematic case? Yes Delay + rate counting No Time to generate? Yes Make code generation Return Figure 6. Make/Break/Typematic timing state diagram TELEFUNKEN Semiconductors 06.96 13 T S Communication between PC and Keyboard The following subsection describes the interfacing of the microcontroller to the PC. After power-up, the microcontroller sets the clock and data lines to a high level and checks the current line status. There are three line status modes possible: * PC forces clock line low (communication interrupted/inhibited by PC) * PC forces data line low (request to send data from PC to keyboard) * Data and clock line high (scan code transmission by keyboard) The clock line is always driven by the microcontroller, except when the PC inhibits communication. If the clock line is high, the controller checks the data line. When it is low (forced by the PC), the PC signals a request to send serial data to the keyboard. In this case, the controller supplies a serial clock burst to fetch the data packet from the PC. When data and clock lines are high, the serial channel is free for the controller to transmit the scanned key codes to the PC. Data transmit keyboard >> PC Clock (keyboard) Each serial data packet normally consists of an 11-bit data stream, including a start bit, 8 data bits, a parity bit and stop bit (see figure 7). In transmit mode, the data sent by the controller to the PC is valid during the low level of the clock signal. Data changes during the high clock phase. The data transfer can be interrupted by the PC at any time up until the rising edge of the 10th clock pulse (parity bit). In receive mode, the received PC data is valid during the high level of the clock signal and changes during the low level. After detecting the stop bit, the controller forces the data line to a low level for a one-bit period (line control bit). The start bit is always low and the stop bit high. Command Protocol The controller must handle different types of data - both commands and data to and from the PC, acknowledge signaling and key scan codes from the keyboard FIFO buffer. All commands and data are organized in serial packets as described above. Commands coming from the PC always have priority and a new command always overrides a preceding one. To initiate a command, the PC forces the data line low and the M44C510 supplies eleven clock pulses and reads in the command. 4 10 1 2 3 5 6 7 8 9 11 Start Data (keyboard) bit BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 parity Stop bit Data transmit PC >> keyboard 10 Clock (keyboard) 1 2 3 4 5 6 7 8 9 Start Data (PC) bit BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 Parity Stop bit 11 Line control bit Forced by keyboard Figure 7. Data communication format 14 TELEFUNKEN Semiconductors 06.96 Some of these PC commands request either data from the keyboard, or prepare the keyboard to receive the following data words. After receiving a command, the controller returns an acknowledge word (FA hex). If the command involves data transmission from/to the PC, the acknowledge is followed by the transmission of the data. The M44C510 sends only the key scan codes from the FIFO buffer when there is no request from the PC. Whenever there is a request from the PC, the controller reads in the data (see figure 8). The data is checked to see whether it is a new command. A new command is stored in a Command Register. The command is decoded and the number of associated data bytes to be handled is stored in a Command Status register. The acknowledge word (FA hex) is stored in the command output buffer and transmitted, whereupon the Command Status register dec- rements and tests for zero. If it is zero, this command communication is terminated and the controller is free to process other commands or return to key scanning (see figure 9). If it is not zero, the controller remains active to process further command-associated data. While the controller is involved with command communication, all keyboard scanning is suspended. T S The multiple scan codes are stored into a 16byte First-In-First-Out (FIFO) buffer until the PC is ready to receive them. If the FIFO is full and further scan codes appear, an overrun code is generated and stored into the 17th byte of the last occupied buffer register location. All further key activities will be ignored. The keyboard buffer contains only the scan codes and does not include any commands from the PC or optional data during command communication. Request from PC Load command status register and store command disable scan No New command? Yes Return Waiting for a byte from PC? No Yes Receive byte Return Transmit data/ACK No End of communication? Yes Execute each command No Return Return Figure 8. Command communication state diagram TELEFUNKEN Semiconductors 06.96 15 T S Communication/ scan inhibit? Yes Yes Reset? No Yes Transmit last data Resend mode? No Return Request from system? No Yes While communication? No Yes Send scan code Send? No Return Scan keyboard Return Adapt command Yes Return Reset keyboard No Return Return Figure 9. Communication state diagram 16 TELEFUNKEN Semiconductors 06.96 Appendix MARC4 Product Overview M43C505 ROM x 8 Test ROM x 8 RAM x 4 EEPROM x 8 IN/OUT (bidirectional) IN Prescaler 8-bit timer Watchdog Batt. low High I out Serial I/O LCD Analog I/O Interrupts Peripheral clock System clock 4096 253 - 12 + 1 4 2 - - - - - 20 x 4 - 32 kHz 2 MHz (RC) M44C090 2048 512 128 (64) 12 - 1 1 yes yes - 8 bit sync. - - - 4 MHz (Q,(R)C) M44C092 4096 512 128 (64) 20 - 1 2 yes yes - 8 bit sync. - 1 comparator 32 kHz 4 MHz (Q,(R)C) M44C260 4096 1024 256 16 16 2 1 2 yes - - - - - 32 kHz 4.2 MHz M44C510 4096 1024 256 - 32 2 2 yes - 8 x 20 mA - - - 32 kHz 4 MHz (Q,(R)C) T S M44C588 9216 1024 256+256 - 16 + 16 - 2 2 yes yes 4 x4 mA @ 2.4 V 8 bit sync. 32 x 4 - 32 kHz 4 MHz (Q,(R)C) M44C636 4096 253 - 12 + 1 4 2 2 yes - 2 x 1 mA - 20 x 4 - 32 kHz 1 MHz (1.5 V) 500 kHz (3 V) 2 int., 3 ext. 3 int., 4 ext. 6 int., 5 ext. 3 int., 3 ext 4 int., 10 ext. 5 int., 8 ext. 4 int., 3 ext. Inst. cycle IDD active 1 s 1.4 mA 0.5 s 1 mA 0.5 s 1 mA 1 s 4 mA 0.5 s 1 mA 0.5 s 1.4 mA 4 s 400 A (1.5 V) 180 A (3 V) I sleep (3 V) 3 A 10 A 1.8 - 6.2 V DIT SO8 SO16 1 A 1.8 - 6.2 V DIT SO28 DIP28 0,8 A 2.4 - 6.2 V DIT SO28 SSO20 3 A 2.4 - 6.2 V DIT PDIL24,40 SO28 SSO44 4 A 2.4 - 6.2 V DIT QFP100 0.8 A 1.2 - 2.2 V 1.8 V-3.6 V DIT QFP64 PLCC44 M40C636 (Piggyback) Suppl. voltage 2.4 - 5.5 V Package DIT QFP64 PLCC44 Eval. type M45C535 (metalROM) M48C092 M48C092 M48C260 M40C510 (EEPROM) (EEPROM) (EEPROM) (Piggyback) TELEFUNKEN Semiconductors 06.96 17 T S Development Tools Integrated Software Package SDS2 * Free-of-charge qFORTH software library * Integrated environment with text editor and pull-down menus running on any IBM-compatible PC under MS-DOS, Windows, OS/2 * Software simulator * Highly optimizing qFORTH compiler * Comprehensive documentation (qFORTH, Programmer's Guide, User's Guide) Emulator Card * * * * Full-sized PC/AT plug-in card 4 k x 32 bit instruction trace buffer Up to 4 PC, 4 RAM and 2 I/O breakpoints for real-time triggering Stack overflow and interrupt supervisor Target Application Board * * * * * Level shifter logic for real-time emulation even < 1.2 V VG96 interface connector to an additional wire-wrap board or LCD demo board Interface connector to emulator card Stand-alone operation possible from a single, external 9-V supply Standard 27C64 CMOS EPROM socket on board for stand-alone mode M40C505/636 Piggyback * * * * 64-pin DIL-sized hybrid chip, compatible to the emulation device's pin out Supply voltage 2.8 V to 5.5 V All external components are integrated Standard 27C64 on top side M44C510 Piggyback * 40-pin DIL-sized hybrid chip M48C260 OTP with Programming Adapter * Available in SS028 or PDIL28 package * Programmer attached to parallel/ printer port 18 TELEFUNKEN Semiconductors 06.96 M44C510 MARC4 - 4-bit Universal Microcontroller The M44C510 is a member of the TEMIC family of 4-bit single-chip microcontrollers. It contains ROM, RAM, up to 32 digital I/O pins, up to 10 maskable external interrupt sources, 6 maskable internal interrupts, a watchdog timer, 32-kHz oscillator with programmable watch timer, 2 x 8-bit multifunction timer/counter module and a versatile on-chip system clock generation module. Features Benefits D D D D D D D D 4 K x 8-bit application ROM 256 x 4-bit RAM 8 hardware and software interrupt priority levels Bitwise maskable prioritized interrupts Up to 10 external and 4 internal interrupts Up to 32 I/O lines High drive ports (20 mA, VDD = 5 V) I/O ports - bitwise configurable with combined interrupt handling (for serial I/O applications) D Extremely low-power consumption D Minimal external components D Coded reset and watchdog timer ** D Power-on reset, "brown out" function D Power-down mode D 2.4 V to 6.2 V supply voltage D Data retention down to 2 V in SLEEP mode D Efficient, hardware-controlled interrupt handling D High-level programming language in qFORTH D Comprehensive library of useful routines D PC based development tools (** mask option) D 2 x 8-bit multifunction timer/counters D 32-kHz on chip oscillator with programmable prescaler/interval timer D User definable on-chip system clock generation D 4-MHz crystal, 4-MHz ceramic resonator or fully integrated RC oscillator ** V SS VDD TE SCLIN SCLOUT NRST OSCIN OSCOUT AVDD TIM1 Test Sleep System clock Master reset Real time clock ROM 5K x 8bit RAM 256 x 4bit Timer/ counter Watch- dog Prescaler Timer 1 Timer 0 Melody & buzzer MARC4 4-bit CPU core I/O bus I/O I/O I/O I/O I/O Interrupt & reset I/O Interrupt I/O I/O Interrupt I/O Port 0 Port 1 Port 5 Port 7 Port A Port B Port C Port 6 Port 4 96 11515 Figure 1. Block diagram TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 19 Preliminary Information M44C510 BP61 [INTy] BP60 [INTx] SCLOUT OscOut SCLIN AVDD NRST BPA0 BPA1 23 18 BP12 BPA2 22 19 BP11 BPA3 BP10 20 21 BPB3 BPB2 BPB1 BPB0 29 OscIn 27 BP70 BP71 39 BP72 38 BP73 37 40 36 35 34 33 32 31 30 28 26 TIM1 15 25 16 TE M44C510-P40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 BP53 BP52 BP51 BP50 BP43 BP42 BP41 BP40 BP03 BP02 BP01 BP00 BP13 VDD VSS 17 24 96 11516 Figure 2. Pin connections Table 1. Pin description A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA (*) For mask options, please see the order information. 20 Function Power supply voltage +2.4 V to +6.2 V Analog power supply voltage +2.4 V to +6.2V Circuit ground 4 bidirectional I/O lines of Port 0 - automatic nibblewise configurable I/O 4 bidirectional I/O lines of Port 1(*) - automatic nibblewise configurable I/O 4 bidirectional I/O lines of high current Port 5(*) - bitwise configurable I/O 4 bidirectional I/O lines of high current Port 7(*) - bitwise configurable I/O 4 bidirectional I/O lines of Port A(*) - bitwise configurable I/O and as inputs to a port monitor module. Optional coded reset inputs (*) BPB0 - BPB3 4 bidirectional I/O lines of Port B(*) - bitwise configurable I/O and as inputs to a port monitor module BPC0 - BPC1 2 bidirectional I/O lines of Port C (*) - bitwise configurable I/O BP60 - BP61 2 bidirectional I/O lines of Port 6 (*) - bitwise configurable I/O or as 2 external programmable interrupts BP40-T0OUT0 I/O line BP40 of Port 4(*) - configurable I/O or timer/counter 0 I/O T0OUT0 BP41-T0OUT1 I/O line BP41 of Port 4(*) - configurable I/O or timer/counter 0 I/O T0OUT1 BP42-BUZ High current I/O line BP42 of Port 4(*) - configurable I/O or buzzer output BUZ BP43-NBUZ High current I/O line BP43 of Port 4(*) - configurable I/O or buzzer output NBUZ TIM1 Dedicated bidirectional I/O for Timer 1 SCLIN 4-MHz quartz crystal/ceramic resonator or trimming resistor pin (mask-option dependent) SCLOUT 4-MHz quartz crystal/ceramic resonator pin (mask-option dependent) OSCIN 32-kHz quartz crystal pin (mask-option dependent) OSCOUT 32-kHz quartz crystal pin (mask-option dependent) TE Testmode input. This input is used to control the test modes (internal pull-down) NRST Reset input (/output), a logic low on this pin resets the device. An internal watchdog or coded reset is indicated by a low pulse on this pin. Name VDD AVDD VSS BP00 - BP03 BP10 - BP13 BP50 - BP53 BP70 - BP73 BPA0 - BPA3 Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 M44C510 Contents 1 MARC4 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Components of MARC4 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.4 ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.5 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.6 I/O Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2 Software Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.1 Clock Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Addressing Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Bidirectional Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Port 0, Port 1 - Bidirectional Ports Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Port 5, Port 7, Port C - Bidirectional Ports Type 2 . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Port A, Port B - Bidirectional Ports Type 3 - and Port Monitor Function . . . . . . . 2.2.4 Port 6 - Bidirectional Port Type 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5 Port 4 - Bidirectional Port Type 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.6 TIM1 - Bidirectional Pin Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Interval Timers / Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 Interval Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Timer/Counter Module (TCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 General Timer/Counter Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 Timer/Counter in 16-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.3 Timer 0 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.4 Timer 1 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Buzzer Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 DC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 22 22 22 23 23 26 26 26 26 28 28 29 30 31 31 31 31 34 35 36 36 38 40 41 41 42 43 43 45 48 48 58 61 63 64 64 64 66 69 70 71 2 3 4 5 6 TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 21 Preliminary Information M44C510 1 MARC4 Architecture Reset Reset Clock System clock Sleep 1.1 General Description The MARC4 microcontroller consists of an advanced stack based 4-bit CPU core and on-chip peripherals. The CPU is based on the HARVARD architecture with physically separate program memory (ROM) and data memory (RAM). Three independent buses, the instruction bus, the memory bus and the I/O bus are used for parallel communication between ROM, RAM and peripherals. This enhances program execution speed by allowing both instruction prefetching, and a simultaneous communication to the on-chip peripheral circuitry. The extremely powerful integrated interrupt controller with associated eight prioritized interrupt levels supports fast and efficient processing of hardware events. The MARC4 is designed for the high-level programming language qFORTH. The core includes an expression and a return stack. This architecture allows high-level language programming without any loss in efficiency or code density. 22 IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII MARC4 CORE PC X Y SP RP Program memory RAM 256 x 4-bit Instruction bus Instruction decoder Interrupt controller Memory bus TOS CCR ALU I/O bus On-chip peripheral modules Figure 3. MARC4 core 94 8973 1.2 Components of MARC4 Core The core contains ROM, RAM, ALU, a program counter, RAM address registers, an instruction decoder and an interrupt controller. The following sections describe each functional block in more detail: 1.2.1 ROM The program memory (ROM) is mask programmed with the customer application program during the fabrication of the microcontroller. The ROM is addressed by a 12-bit wide program counter, thus predefining a maximum program bank size of 4 Kbytes. An additional 1 Kbyte of ROM exists which is used partly for a quality control selftest program. The remaining space is available for the application program. The access to this additional ROM section is done by using a ROM-bank switch. Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 M44C510 FFFh FFFh ROM BANK 0 (2K x 8 bit) 7FFh (not available) BFFh 1F8h 1F0h 1E8h 1E0h 1E0h 1C0h 180h INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 BANK 1 (1K x 8 bit) 7FFh SCALL addresses Z ero p age 140h 100h 0C0h 080h Basebank 1FFh Common base bank address area Zero page 000h 020h 018h 010h 008h 000h 040h 008h 000h $RESET $AUTOSLEEP 96 11517 Figure 4. ROM map of M44C510 The lowest user ROM address segment is taken up by a 512-byte zero page which contains predefined start addresses for interrupt service routines and special subroutines accessible with single-byte instructions (SCALL). The corresponding memory map is shown in figure 4. Look-up tables of constants can also be held in ROM and are accessed via the MARC4's built-in TABLE instruction. ROM Banking Bank switching is fully supported by the compiler for customers programming with qFORTH. The MARC4 switches from one ROM bank to another by writing the new bank number to the ROM Bank Register (RBR). Conventional program space (power-up bank) resides in ROM bank 0. Each ROM bank consists of a 4-KByte address space whereby the lowest 2 KByte is common to all banks, so that addresses between 000h and 7FFh always accesses the same ROM data (see figure 4). When ROM banking is used, the compiler will, if necessary, insert the program code to save and restore the condition of the RBR on bank switching. MARC4 performs the operations with the top of stack items (TOS and TOS-1). The TOS register contains the top element of the expression stack and works in the same way as an accumulator. This stack is also used for passing parameters between subroutines and as a scratch pad area for temporary storage of data. Return Stack The 12-bit wide return stack is addressed by the return stack pointer (RP). It is used for storing return addresses of subroutines, interrupt routines and for keeping loop index counts. The return stack can also be used as a temporary storage area. The MARC4 instruction set supports the exchange of data between the top elements of the expression stack and the return stack. The two stacks within the RAM have a userdefinable location and maximum depth. 1.2.3 Registers 1.2.2 RAM The MARC4 controller has seven programmable registers and one condition code register. They are shown in figure 6. Program Counter (PC) The program counter (PC) is a 12-bit register that contains the address of the next instruction to be fetched from the ROM. Instructions currently being executed are decoded in the instruction decoder to determine the internal micro operations. For linear code (no calls or branches) the program counter is incremented with every instruction cycle. If a branch, call, return instruction or an interrupt is executed, the program counter is loaded with a new address. The program counter is also used with the TABLE instruction to fetch 8-bit wide ROM constants. The MARC4 contains 256 x 4-bit wide static random access memory (RAM). It is used for the expression stack, the return stack and data memory for variables and arrays. The RAM is addressed by any of the four 8-bit wide RAM address registers SP, RP, X and Y. Expression Stack The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All arithmetic, I/O and memory reference operations take their operands from, and return their result to the expression stack. The TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 23 Preliminary Information M44C510 FCh FFh Global variables X RAM address register: Y SP RP 04h 00h Return stack Global v 07h variables 03h Figure 5. RAM map ROM Banking Register (RBR) The ROM banking register is a 4-bit register whereby in the M44C510, only bit 2 is used. This indicates which ROM bank is presently being addressed. The RBR is accessed with a standard qFORTH peripheral read or write instruction (IN or OUT, port address `D' hex). RAM Address Registers The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y. These registers allow access to any of the 256 RAM nibbles. Expression Stack Pointer (SP) The stack pointer (SP) contains the address of the next-totop 4-bit item (TOS-1) of the expression stack. The pointer is automatically preincremented if a nibble is moved onto the stack, or postdecremented if a nibble is removed from the stack. Every postdecrement operation moves the item (TOS-1) to the TOS register before the SP is decremented. After a reset the stack pointer has to be initialized with " >SP S0 " to allocate the start address of the expression stack area. Return Stack Pointer (RP) The return stack pointer points to the top element of the 12-bit wide return stack. The pointer automatically preincrements if an element is moved onto the stack or it postdecrements if an element is removed from the stack. The return stack pointer increments and decrements in steps of 4. This means that every time a 12-bit element is stacked, a 4-bit RAM location is left unwritten. These locations are used by the qFORTH compiler to allocate 4-bit variables. After a reset, the return stack pointer has to be initialized with ">RP FCh ". RAM Address Register ( X and Y ) The X and Y registers are used to address any 4-bit item in the RAM. A fetch operation moves the addressed nibble onto the TOS. A store operation moves the TOS to the addressed RAM location. By using either the preincrement or postdecrement, addressing mode arrays in the RAM can be compared, filled or moved. Top Of Stack ( TOS ) The top of stack register is the accumulator of the MARC4. All arithmetic/logic, memory reference and I/O operations use this register. The TOS register receives data from the ALU, ROM, RAM or I/O bus. Condition Code Register ( CCR ) The 4-bit wide condition code register contains the branch, the carry and the interrupt-enable flag. These bits indicate the current state of the CPU. The CCR flags are set or reset by ALU operations. The instructions SET_BCF, TOG_BF, CCR! and DI allow direct manipulation of the condition code register. Carry/Borrow ( C ) The carry/borrow flag indicates that borrow or carry out of arithmetic logic unit ( ALU ) occurred during the last arithmetic operation. During shift and rotate operations, this bit is used as a fifth bit. Boolean operations have no affect on the C flag. Branch ( B ) The branch flag controls the conditional program branching. Should the branch flag have been set by a previous 24 Preliminary Information IIIII IIIII TOS-1 Expression stack Return stack 11 0 RP III III 4-bit 12-bit (256 x 4-bit) Autosleep RAM Expression stack 3 0 TOS TOS-1 TOS-2 SP IIIII IIIII IIIII IIIIIII I IIIIIII IIIIIII I IIIIIII IIII IIIIIII IIII IIIII IIIII 94 8975 TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 M44C510 instruction, a conditional branch will cause a jump. This flag is affected by arithmetical, logical, shift, and rotate operations. Interrupt Enable ( I ) The interrupt-enable flag globally enables or disables the triggering of all interrupt routines with the exception of the non-maskable reset. After a reset, or on executing the DI instruction, the interrupt-enable flag is reset, thus disabling all interrupts. The core will not accept any further interrupt requests until the interrupt-enable flag has been set again either by executing an EI, RTI or SLEEP instruction. 11 0 PC 0 Program counter RBR 7 bank -- -- 0 ROM bank register Return stack pointer Expression stack pointer RP 7 0 0 0 SP 7 0 X 7 0 RAM address register (X) RAM address register (Y) 3 0 Y TOS 3 0 Top of stack register C -- B I Condition code register Interrupt enable Branch Reserved Carry / borrow CCR 96 11518 Figure 6. Programming model TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 25 Preliminary Information M44C510 The 4-bit ALU performs all the arithmetical, logical, shift and rotate operations with the top two elements of the expression stack (TOS and TOS-1) and returns the result to the TOS. The ALU operations affect the carry/borrow and branch flag in the condition code register (CCR). 1.2.5 Instruction Set The MARC4 instruction set is optimized for the highlevel programming language qFORTH. Many MARC4 instructions are qFORTH words. This enables the compiler to generate a fast and compact program code. The CPU has an instruction pipeline which allows the controller to prefetch an instruction from ROM at the same time as the present instruction is being executed. The MARC4 is a zero-address machine. The instructions contain only the operation to be performed and no source or destination address fields. The operations are implicitly performed on the data placed on the stack. There are one and two byte instructions which are executed within 1 to 4 machine cycles. A MARC4 machine cycle is made up of two system clock (SYSCL) cycles. Most of the instructions are only one byte long and are executed in a single machine cycle. 1.2.6 I/O Bus The I/O ports and the registers of the peripheral modules (Timer 0, Timer 1, Interval timer, Watchdog etc.) are I/O 26 IIIII IIII IIIII III IIII IIIIIIIII IIII IIII IIIIIIIII IIII IIII III I II IIIIIIIIIIIIII IIII III I I II IIIII IIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIII I IIIIIIII I IIIIIIIIIIIIII I IIIII IIII RAM SP TOS-1 TOS-2 TOS-3 TOS-4 TOS ALU CCR Figure 7. ALU zero-address operations 1.2.4 ALU 94 8977 mapped. All communication between the core and the onchip peripherals takes place via the I/O bus and the associated I/O control. With the MARC4 IN and OUT instructions, the I/O bus enables a direct read or write access to one of the 16 primary I/O addresses. More about the I/O access to the on-chip peripherals is described in the "Peripheral Modules". The I/O bus is internal and is not accessible by the customer on the final microcontroller device, but is used as the interface for the MARC4 emulation (see also the section "Emulation"). 1.3 Interrupt Structure The MARC4 can handle interrupts with eight different priority levels. They can be generated from the internal and external interrupt sources or by a software interrupt from the CPU itself. Each interrupt level has a hard-wired priority and an associated vector for the service routine in the ROM (see table 2, page 10). The programmer can postpone the processing of interrupts by resetting the interrupt enable flag (I) in the CCR. An interrupt occurrence will still be registered but the interrupt routine is only started after the I flag is set. All interrupts can be masked, and the priority individually software configured by programming the appropriate control register of the interrupting module (see section "Peripheral Modules"). Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 M44C510 INT7 7 6 Priority level 5 4 3 2 1 0 Interrupt Processing For processing the eight interrupt levels, the MARC4 includes an interrupt controller with two 8-bit wide "interrupt pending" and "interrupt active" registers. The interrupt controller samples all interrupt requests during every non-I/O instruction cycle and latches these in the interrupt pending register. Whenever an interrupt request is detected, the CPU interrupts the program currently being execution, on condition that no higher priority interrupt is present in the interrupt active register. If the interrupt-enable bit is set, the processor enters an interrupt acknowledge cycle. During this cycle a short call (SCALL) instruction is executed to the service routine and the current PC is saved on the return stack. An interrupt service routine is finished with the RTI instruction. This instruction sets the interrupt-enable flag, resets the corresponding bits in the interrupt pending/active register and fetches the return address from the return stack to the program counter. When the interrupt-enable flag is reset (triggering of interrupt routines is disabled), the TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 AAAA AAAAA AAAA AAAAA AAIIIIII AA AAIIIIII AA AAIIIIIII AA AAAA AAIIAAAA AA A AIIIII AAAA AAAA AAA AAAA AAA AAAA AAAA AAAA INT7 active INT5 RTI INT5 active INT3 RTI INT2 INT3 active RTI INT2 pending INT2 active RTI SWI0 INT0 pending INT0 active RTI Main / Autosleep Main / Autosleep Time 94 8978 Figure 8. Interrupt handling execution of new interrupt service routines is inhibited, but not the logging of the interrupt requests in the interrupt pending register. The execution of the interrupt is be delayed until the interrupt-enable flag is set again. Note that interrupts are only lost if an interrupt request occurs while the corresponding bit in the pending register is still set (i.e., the interrupt service routine is not yet finished). It should also be realized that automatic stacking of the RBR is not carried out by the hardware and so if ROM banking is used, the RBR must be stacked on the expression stack by the application program and restored before the RTI. After a master reset (power-on, external or watchdog reset), the interrupt-enable flag and the interrupt pending and interrupt active registers are all reset. Interrupt Latency The interrupt latency is the time from the occurrence of the interrupt to the interrupt service routine being activated. In the MARC4, this is extremely short and takes between 3 to 5 machine cycles depending on the state of the core. 27 Preliminary Information M44C510 Table 2. Interrupt priority table AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAA AA C8h (SCALL 040h) D0h (SCALL 080h) D8h (SCALL 0C0h) E8h (SCALL 100h) E8h (SCALL 140h) F0h (SCALL 180h) F8h (SCALL 1C0h) FCh (SCALL 1E0h) Interrupt INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 Priority lowest | | | | | highest ROM Address 040h 080h 0C0h 100h 140h 180h 1C0h 1E0h Maskable Yes Yes Yes Yes Yes Yes Yes Yes Interrupt Opcode 1.3.1 Hardware Interrupts Table 3. Hardware interrupts A A A A AAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AA A A AAAAAAA AA AA A A A AAAAAAAAAAAAAAAA A AAAAAAAAA A A AAAAAAAAAAAAAAAA A A A AAAAAA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAA AA A A A A AAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAA A A AAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAA AA X # # * * * * * * * * * * * * * * * * * * Interval timer INTB Timer 0 Timer 1 * * ITIPR T0CR T1CR * * * * * * *AA* low level active 1/2 - 2 sec. time out level any inputs any edge, any input any edge, any input any edge any edge 1 of 8 frequencies (1 - 128 Hz) 1 1 of 8 frequencies (8 - 8192 Hz) 0 overflow/compare/ end measurement 0AAAAAAAAA compare X = hardwired (neither optional or software configurable) # = customer mask option (see "Ordering Information") * = software configurable (see "Peripheral Modules" section for further details) In the M44C510, there are eleven hardware interrupt sources which can be programmed to occupy a variety of priority levels. Each source can be individually masked by mask bits in the corresponding control registers. An overview of the possible hardware configurations is shown in table 3. The software triggered interrupt operates in exactly the same way as any hardware triggered interrupt. The SWI instruction takes the top two elements from the expression stack and writes the corresponding bits via the I/O bus to the interrupt pending register. Thus, by using the SWI instruction, interrupts can be re-prioritized or lower priority processes scheduled for later execution. Interrupt Source NRST external Watchdog Port A coded reset Port A monitor Port B monitor Port 60 external Port 61 external Interval timer INTA 0 Possible Interrupt Priorities 1234567 RST Interrupt Mask Register Bit - - - - - - PAIPR 3 PBIPR 3 P6CR 1,0 P6CR 3,2 ITIPR 0 Function 1.3.2 Software Interrupts The programmer can generate interrupts using the software interrupt instruction (SWI) which is supported in qFORTH by predefined macros named SWI0...SWI7. 28 Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 M44C510 1.4 Hardware Reset Coded Reset (Port A) The coded reset circuit is connected directly to the Port A terminals. By using a mask option, the user can define a hardwired code combination (e.g., all pins low) which, if occurring on the Port A, will generate a reset in the same way as the NRST pin. Table 4. Multiple key reset options The master reset forces the CPU into a well-defined condition, is unmaskable and is activated independent of the current program state. It can be triggered by either initial supply power-up, a short collapse of the power supply, a watchdog time out, activation of the NRST input or the occurrence of a coded reset on Port A (see figure 9). A master reset activation will reset the interrupt enable flag, the interrupt pending register and the interrupt active register. During the reset phase, the I/O bus control signals are set to 'reset mode' thereby initializing all on-chip peripherals. Releasing the reset results in a short call instruction (opcode C1h) to the ROM address 008h. This activates the initialization routine $RESET which in turn initializes all necessary RAM variables, stack pointers and peripheral configuration registers. Power-on Reset The fully integrated power-on reset circuit ensures that the core is held in a reset state until the minimum operating supply voltage has been reached. A reset condition is also generated should the supply voltage drop momentarily below the minimum operating supply. External Reset (NRST) An external reset can be triggered with the NRST pin. To activate an external reset, the pin should be low for a minimum of two machine cycles. VDD Pull-up NRST NO_RST RST2 RST3 RST4 Not used (default) BPA0 & BPA1 BPA0 & BPA1 & BPA2 BPA0 & BPA1 & BPA2 & BPA3 Note, that if this option is used, the reset is not maskable and will also trigger if the predefined code is written on to the Port A by the CPU itself. Care should also be taken not to generate an unwanted reset by inadvertently passing through the reset code on input transitions. This applies especially if the pins have a high capacitive load. Watchdog Reset The watchdog's function can be enabled via a mask option and triggers a reset with every watchdog counter overflow. To suppress the watchdog reset, the counter must be regularly reset by reading the watchdog register address (WDRES). The CPU reacts in exactly the same manner as a reset stimulus from any of the above sources. * = Mask option CPU reset VSS V DD Power-on reset reset code CODE * time out Port A I/O Watchdog * rst WD reset Port A CPU 96 11519 Figure 9. Reset configuration TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 29 Preliminary Information M44C510 1.5 Clock Generation 2 MHz, for example, can be obtained by connecting a 220 kW resistor (see figures 44, 48 and 49). Some applications require only long-term time keeping or low resolution timing. In this case, an on-chip, lowpower 32-kHz crystal oscillator can be used to generate the SUBCL. This allows the core to go into SLEEP mode when not used, and therefore greatly reduces power consumption. If the full 2-MHz timing resolution is required, then either the crystal or resonator oscillator should be used for SYSCL generation. Should a suitable external 1...4-MHz or 32-kHz clock source be available, then SCLIN (Crystal oscillator configuration) or OSCIN respectively can be used as the input. Note: A SYSCL frequency of 2 MHz leads an instruction cycle time of 1 ms. The M44C510 has a dual clock system, a 2-MHz system clock (SYSCL) for the core and a 32-kHz subclock (SUBCL) for the time-keeping peripheral modules (see figure 10). Each clock can be generated from independent on-chip oscillators or they can both be derived from the same high frequency SYSCL oscillator. This is mask selectable - allowing a choice of either an 4-MHz crystal, 4-MHz ceramic resonator or a RC oscillator. All the necessary oscillator circuitry, with the exception of the actual crystal or resonator, are integrated on chip. Therefore, if no exact timing is required, for example, it is possible to use the fully integrated RC oscillator, thus operating without any external components. An additional mask option enables a high resolution trimmable RC oscillator whereby the SYSCL can be trimmed with an external resistor between SCLIN and VDD. In this configuration, the SYSCL frequency can be maintained stable to within a tolerance of 10% over the full operating temperature range. A SYSCL frequency of SCLIN * * Crystal oscillator Oscin Out Oscout Oscout Ceramic resonator oscillator Oscin Out RCoscillator R Trim Out Toggle SCLOUT * * Osc. select Osc. select SYSCL to CPU OSCIN to timer/counter * OSCOUT 32kHz crystal oscillator Oscin Out Oscout Divide by 64 * SUBCL to watchdog to prescaler * * = mask option to buzzer to timer/counter 96 11520 Figure 10. Clock module 30 Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 M44C510 1.5.1 NRST TE SYSCL clocks BP10 SUBCL clocks Clock Monitor Mode BP11 96 11521 Oscillator test mode Normal operation Figure 11. Clock monitoring For trimming purposes, the M44C510 can be put into a clock monitor mode. The test input (TE) must therefore be pulsed high once, whereupon the SYSCL clock will appear on BP10 (Port 1, bit 0) and SUBCL clock on Port BP11 (Port 1, bit 1). To put BP10 and BP11 back into normal operation, the reset must be reapplied (see figure 11). IDD depends on VDD and fsyscl. Using a 32-kHz crystal, the SLEEP current (ISleep) is typically less than 1 A. The active time of the core and the total emulation time are displayed in a separate window of the MARC4 emulator software. 1.6 Sleep Mode 2 2.1 Peripheral Modules Addressing Peripherals The sleep mode is a shutdown condition which is used to reduce the average system power consumption in applications where the C is not fully utilized. In this mode, the system clock is stopped. The sleep mode is entered with the SLEEP instruction. This instruction sets the condition code register interrupt enable bit (I) to enable all interrupts and stops the core. During the sleep mode, the peripheral modules remain active and are able to generate interrupts. The C exits the sleep mode with any interrupt or a reset. The sleep mode can only be maintained when no interrupt pending or active register bits are set. The application of the $AUTOSLEEP routine ensures the correct function of the sleep mode. The total power consumption is directly proportional to the active time of the C. For a rough estimation of the expected average system current consumption, the following formula should be used: Itotal (VDD,fsyscl) = ISleep + (IDD * Tactive /Ttotal) Accessing the peripheral modules takes place via the I/O bus (see figure 12). The IN or OUT instructions allow direct addressing of up to 16 I/O modules. A dual register addressing scheme has been adopted which addresses the "primary register" directly. To address the "auxiliary register", the access must be switched with an "auxiliary switching module". Thus, a single IN (or OUT) to the module address will read (or write) into the module primary register. Accessing the auxiliary register is performed with the same instruction preceded by writing the module address into the auxiliary switching module. Byte-wide registers are accessed by multiple IN (or OUT) instructions. Extended addressing is used for more complex peripheral modules, with a larger number of registers. In this case, a bank of up to 16 subport registers are indirectly addressed with the subport address being initially written into the auxiliary register. TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 31 Preliminary Information M44C510 Module ASW Module M1 (Address Pointer) Aux. Reg. Bank of Primary Regs. Subport Fh Subport Eh Aux. Reg. 6 Module M2 Module M3 2 Auxiliary Switch Module Subport 1 Primary Reg. Subport 0 3 1 5 Primary Reg. 4 7 Primary Reg. I/O bus to other modules Indirect Subport Access (Subport Register Write) 1 2 Dual Register Access (Primary Register Write) 4 Single Register Access (Primary Register Write) 7 Addr.(M1) SPort_Data Addr.(ASW) OUT OUT OUT Addr.(M1) Prim._Data Address(M2) OUT Prim._Data Address(M3) OUT Addr.(SPort) Addr.(M1) 3 ( Auxiliary Register Write ) 5 6 Address(M2) Address(ASW) OUT Aux._Data Address(M2) OUT 7 (Prima ry Register Read) Address(M3) IN (Subport Register Read) 1 2 3 Addr.(M1) Addr.(ASW) OUT OUT IN Addr.(SPort) Addr.(M1) Addr.(M1) (Primary Register Read) 4 Address(M2) (Auxiliary Register Rea d) IN Example of qFORTH Program Code (Subport Register Write Byte) 1 2 3 Addr.(M1) Addr.(ASW) OUT OUT 5 Addr.(SPort) Addr.(M1) SPort_Data(lo) Addr.(M1) OUT SPort_Data(hi) Addr.(M1) OUT (Subport Register Rea d Byte) 6 Address(M2) Address(ASW) OUT Address(M 2) IN (Auxiliary Register Write Byte) 3 5 6 6 Address(M2) Address(ASW) OUT Aux._Data(lo) Address(M2) OUT Aux._Data(hi) Address(M2) OUT Addr.(ASW) = Auxiliary Switch Module Address Addr.(Mx) = Module Mx Addr ess Addr.(SPort) = Subport Address Prim._Data = data to be written into Primary Register. Aux._Data = data to be written into Auxiliary Register Aux._Data (lo)= data to be written into Auxiliary Register (low nibble) Aux._Data (hi) = da ta to be written into Auxiliary Register(high nibble) SPort_Data(lo) = data to be written into SubP ort (low nibble) SPort_Data(hi) = data to be written into Subport (high nibble) 96 11522 1 2 3 3 Addr.(M1) Addr.(ASW) OUT OUT IN IN Addr.(M1) Addr.(M1) Addr.(SPort) Addr.(M1) (Auxiliary Register Rea d) 1 2 Address(M1) Address(ASW) OUT Address(M1) IN Figure 12. Example of I/O addressing 32 Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 AAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AA AAAAAAAAAAAAAAAAAA A AAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAA A A AA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A AA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAAAA A A AA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AA AAAAAAAAAAAAAAAAAA A AAAAAAAA AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAA A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAA A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAA A AA Table 5. M44C510 Peripheral addresses TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 D E F A C B 8 9 7 6 5 4 3 0 1 2 Address P0DAT P1DAT PAIPR Aux. PAICR PBIPR WDRES Aux. PBICR P4DAT Aux. P4DDR P5DAT Aux. P5DDR P6DAT Aux P6CR P7DAT Aux. P7DDR ASW TCM Aux. T0SR TCX Subport address 0 T0MO 1 T0CR 2 T1MO 3 T1CR 4 TCMO 5 TCIO 6 TCCR 7 TCIP 8 T1CP T1CA 9 T0CP T0CA A BZCR B-F PADAT Aux. PADDR PBDAT Aux. PBDDR PCDAT Aux. PCDDR RBR - ITFSR Aux. ITIPR Name Preliminary Information Write /Read W/R W/R W W W R W W/R W W/R W W/R W W/R W W W/R R W W/R W W/R W W/R W W - W W W W W W W W W W W R W R W Timer 0 mode register Timer 0 control register Timer 1 mode register Timer 1 control register Timer/counter mode register Timer/counter I/O control register Timer/counter control register Timer/counter interrupt priority Timer 1 compare register (byte) Timer 1 capture register (byte) Timer 0 compare register (byte) Timer 0 capture register (byte) Buzzer control register Reserved Port A - data register/pin data Port A - data direction register Port B - data register/pin data Port B - data direction register Port C - data register/pin data Port C - data direction register Rom bank switch register Reserved Interval timer frequency select register Interval timer interrupt priority register Port 0 - data register/input data Port 1 - data register/input data Port A - interrupt priority register Port A - interrupt control register Port B - interrupt priority register Watchdog reset Port B - interrupt control register Port 4 - data register/pin data Port 4 - data direction register Port 5 - data register/pin data Port 5 - data direction register Port 6 - data register/pin data Port 6 - control register (byte) Port 7 - data register/pin data Port 7 - data direction register Auxiliary switch register Data to/from subport addressed by TCX Timer 0 interrupt status register Timer/counter subport address pointer Function M44C510 33 M44C510 2.2 Bidirectional Ports With the exception of Port 6 and Port C, all other ports (0, 1, 4, 5, 7, A and B) are 4 bits wide. Port 6 and Port C have a data width of 2 bits (bit 0 and bit 1). All these ports may be used for data input or output. All ports are equipped with Schmitt-trigger inputs and a variety of mask options Port Data Register (PxDAT) Primary register address: 'Port address'hex for open drain, open source and full complementary outputs and pull-up and pull-down transistors. All Port Data Registers (PxDAT) are I/O mapped to the primary address register of the respective port address, and the Port Data Direction Register (PxDDR) to the corresponding auxiliary register. AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A A AA Bit 3* Bit 2 Bit 1 Bit 0 PxDAT PxDAT3 PxDAT2 PxDAT1 PxDAT0 Reset value: 1111b * Bit 3 MSB, bit 0 LSB Port Data Direction Register (PxDDR) A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA A A A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA Bit 3 Bit 2 Bit 1 Bit 0 PxDDR PxDDR3 PxDDR2 PxDDR1 PxDDR0 Reset value: 1111b Value: 1111b means all pins in input mode Table 6. Port Data Direction Register (PxDDR) Auxiliary register address: 'Port address'hex Code 3210 xxx1 xxx0 xx1x xx0x x1xx x0xx 1xxx 0xxx Function BPx0 in input mode BPx0 in output mode BPx1 in input mode BPx1 in output mode BPx2 in input mode BPx2 in output mode BPx3 in input mode BPx3 in output mode There are five different types of bidirectional ports: D Type 1 (Ports 0 and 1) - 4-bit wide, bidirectional ports with automatic full bus width direction switching. D Type 4 (Port 6) - 2-bit wide, bitwise programmable bidirectional ports with optional bus pullups and programmable interrupt logic. D Type 2 (Ports 5 and 7) - 4-bit wide, Port C is a 2-bit wide, bitwise programmable high drive I/O port. D Type 5 (Port 4) - 4-bit wide, bitwise programmable bidirectional port also provides the I/O interface to Timer 0 and the Buzzer. D Type 3 (Ports A and B) - 4-bit wide, bitwise programmable bidirectional ports with optional keyboard pull-ups. 34 Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 M44C510 2.2.1 Port 0, Port 1 - Bidirectional Ports Type 1 may cause the CPU to read the contents of the output data register rather than the external input state. This can be avoided by using either of the following programming techniques: In this port type, the data direction register is not independently software programmable because the direction of the complete port is switched automatically when an I/O instruction occurs (see figure 13). The port can be switched to output mode with an OUT instruction and to input with an IN instruction. The data written to a port will be stored into the output data latches and appears immediately at the port pin following the OUT instruction. After RESET, all output latches are set to '1' and the ports are switched to input mode. An IN instruction reads the condition of the associated pins. Note Care must be taken when switching these bidirectional ports from output to input. The capacitive pin loading at this port, in conjunction with the high resistance pull-ups, D Use two IN instructions and DROP the first data nibble. The first IN switches the port from output to input and the DROP removes the first invalid nibble. The second IN reads the valid pin state. D Use an OUT instruction followed by an IN instruction. With the OUT instruction, the capacitive load is charged or discharged depending on the optional pull-up /pull-down configuration. Write a "1" for pins with pull-up resistors, and a "0" for pins with pulldown resistors. VDD I/O Bus * VDD (Data out) D Q * Pull-up PxDATy R Reset (Direction) OUT S IN R Master reset NQ Q BPxy * * *) Mask options Port 1 only Pull-down 96 11523 Figure 13. Bidirectional Ports 0 and 1 TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 35 Preliminary Information M44C510 2.2.2 Port 5, Port 7, Port C - Bidirectional Ports Type 2 Both type 2 and type 3 bidirectional ports have the same I/O logic. Type 2, however, has an increased drive capability and type 3, an additional low resistance pull-up as customer mask option. These, and all other bidirectional ports include a bitwiseprogrammable Data Direction Register (PxDDR) which allows the individual programming of each port bit as input or output. It also enables the reading of the pin condition in output mode. This is a useful feature for self testing and for serial bus applications. I/O Bus Pull-up * (Data out) I/O Bus D Q PxDATy S Master reset I/O Bus DSQ PxDDRy (Direction) DD Static Pull-up * (Ports A, B) V * BPxy * * * Mask options Pull-down 96 11524 Figure 14. Bidirectional Ports 5, 7, A, B and C 2.2.3 Port A, Port B - Bidirectional Ports Type 3 - and Port Monitor Function PRx1 PRx2 Connected to Ports A and B (x = A or B) PxICR ENx3 ENx2 ENx1 ENx0 PxIPR IMAx ITRx PRx1 PRx2 Decoder BPx3 BPx2 BPx1 BPx0 INT7 INT5 INT3 INT1 0 0 1 1 0 1 0 1 INT7 INT5 INT3 INT1 96 11529 Figure 15. Port monitor module In addition to the standard I/O functions described in section 2.2.2, both Port A (BPA3 - BPA0) and Port B (BPB3 - BPB0) are equipped with port monitor modules. This module is connected across all four port pins (see figure 19) and generates an interrupt should a preprogrammed transition occur on any of the selected pins. This allows interrupt driven port scanning without the power consuming task of continuously polling the port inputs. Using the Port Interrupt Control Register (PxICR), pins can be individually selected. A non-selected pin cannot generate an interrupt. The Port Interrupt Priority Register (PxIPR) allows masking of each interrupt, definition of the interrupt edge and programming of the interrupt priority levels. Port A can also be used for a mask programmable coded reset. For more information see section 1.4 Hardware Reset. The Port Interrupt Priority Registers PAIPR and PBIPR are I/O mapped to the the primary address registers of the Port Monitor Module addresses '2'h and '3'h respectively. The Port Interrupt Control Registers PAICR and PBICR are mapped to the corresponding auxiliary registers. 36 Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA Bit 0 can generate an interrupt Bit 0 cannot generate an interrupt Bit 1 can generate an interrupt Bit 1 cannot generate an interrupt Bit 2 can generate an interrupt Bit 2 cannot generate an interrupt Bit 3 can generate an interrupt Bit 3 cannot generate an interrupt Bit 3 ENx3 Bit 2 ENx2 Bit 1 ENx1 Function Bit 0 ENx0 Reset value: 1111b AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA Port Monitor Interrupt Control Register (PxICR) Table 7. Port Monitor Interrupt Priority Register (PxIPR) AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A x = 'A' (Port A) or 'B' (Port B) Port Monitor Interrupt Priority Register (PxIPR) ITRx IMx PxIPR - Interrupt Transition - Interrupt Mask Bit 3 IMx ITRx Bit 2 PRx2 Bit 1 PRx1 Bit 0 (Port A) Primary register address: '2'hex (Port B) Primary register address: '3'hex TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 x = 'A' (Port A) or 'B' (Port B) PRx2..1 - Interrupt Priority code PxICR Code 3210 xxx0 xxx1 xx0x xx1x x0xx x1xx 0xxx 1xxx Code 3210 xx00 xx01 xx10 xx11 x0xx x1xx 0xxx 1xxx Table 8. Port Monitor Interrupt Control Register (PxICR) ENx3 ... 0 port monitor input ENable code Port monitor interrupt priority 7 Port monitor interrupt priority 5 Port monitor interrupt priority 3 Port monitor interrupt priority 1 Port monitor interrupt on falling edge Port monitor interrupt on rising edge Port monitor interrupt enabled Port monitor interrupt disabled Preliminary Information Function (Port A) Auxiliary register address: '2'hex (Port B) Auxiliary register address: '3'hex M44C510 Reset value: 1111b 37 M44C510 2.2.4 Port 6 - Bidirectional Port Type 4 V I/O Bus DD Pull-up V DD Static Pull-up * VDD (Data out) I/O Bus D Q P6DATy S Master reset IN enable * * BP6y * y = 0 or 1 * * Mask options Pull-down 96 11525 Figure 16. Bidirectional Port 6 This 2-bit bidirectional port can be used as bitwise-programmable I/O. The data is LSB aligned so that the two MSB's will not appear on the port pins when written. The port pins can also be used as external interrupt inputs (see figures 15 and 16). Both interrupts can be masked or independently configured to trigger on either edge. The interrupt priority levels are also configurable. The interrupt configuration and port direction is controlled by the Port 6 Control Register (P6CR). An additional low resistance pull-up transistor (mask option) provides an internal bus pull-up for serial bus applications. In output mode (PxDDR bit = 0), the respective Port Data Register (PxDAT) bit appears on the port pin, driven by an output port driver stage which can be mask programmed as open drain, or full complementary CMOS. With an IN instruction the actual pin state can be read back into the controller at any time without changing the port directional mode. If the output port is mask configured as an open drain driver, the controller is able to receive the external data on this pin without switching into input mode as long as the output transistor is switched off. In input mode (PxDDR bit = 1), the output driver stage is deactivated, so that an IN instruction will directly read the pin state which can be driven from an external source. In this case, the state of the Port Data Register (PxDAT), although not appearing at the pin itself, remains unchanged. High resistance mask selectable pull-up or pull-down transistors are automatically switched onto the port pin in input mode. The Port Data Register is written to the respective port address with an OUT instruction. The Port 6 Data Register (P6DAT) is I/O mapped to the primary address register of address '6'hex and the Port 6 Control Register (P6CR) to the corresponding auxiliary register. The P6CR is a byte wide register and is written by writing the low nibble first and then the high nibble (see section 2.1 "Addressing peripherals"). 38 Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 M44C510 Port 6 Data Register (P6DAT) Primary register address: '6'hex AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A Bit 3 Bit 2 Bit 1 Bit 0 P6DAT not used not used P6DAT1 P6DAT0 Reset value: xx11b The unused bits 2 and 3 are '0', if read. Port 6 Control Register (P6CR) Auxiliary register address: '6'hex AAAAAAAAA A A A A A A AAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAA A A A A A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA A Bit 3 Bit 7 Bit 2 Bit 6 Bit 1 Bit 5 Bit 0 Bit 4 P6CR First write cycle P61IM2 P61IM1 P60IM2 P60IM1 Reset value: 1111b Reset value: 1111b Second write cycle P61PR2 P61PR1 P60PR2 P60PR1 P6xIM2, P6xIM1 - Port 6x Interrupt mode/direction code P6xPR2, P6xPR1 - BP6x Interrupt priority code Table 9. Port 6 control register (P6CR) AAAAAAAAAA A AA A AAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAA A AA A A AAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA A A A TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 39 Auxiliary Address: '6'hex First Write Cycle Code Function 3210 x x 1 1 BP60 in input mode - interrupt disabled x x 0 1 BP60 in input mode - rising edge interrupt x x 1 0 BP60 in input mode - falling edge interrupt x x 0 0 BP60 in output mode - interrupt disabled 1 1 x x BP61 in input mode - interrupt disabled 0 1 x x BP61 in input mode - rising edge interrupt 1 0 x x BP61 in input mode - falling edge interrupt 0 0 x x BP61 in output mode - interrupt disabled Second Write Cycle Code Function 3210 x x 1 1 BP60 set to priority 1 x x 1 0 BP60 set to priority 3 x x 0 1 BP60 set to priority 5 x x 0 0 BP60 set to priority 7 1 1 x x BP61 set to priority 0 1 0 x xAAAAAAAAAA BP61 set to priority 2 0 1 x x BP61 set to priority 4 0 0 x x BP61 set to priority 6 Preliminary Information M44C510 INT6 INT4 INT2 INT0 INT7 INT5 INT3 INT1 Mask Edge Data in Dir. BP61 Bidir. Port IN_Enable Mask Edge Data in Dir. BP60 Bidir. Port IN_Enable decode P6CR: CR7 CR6 decode CR5 CR4 decode CR3 decode I/O bus CR2 CR1 CR0 CR1 CR7 CR6 CR5 INT6 INT4 INT2 INT0 CR4 CR3 INT7 INT5 INT3 INT1 CR0 CR2 Dir. INT edge INT disabled 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 out in in in - - yes no no yes 96 11526 Figure 17. Port 6 external interrupts 2.2.5 Port 4 - Bidirectional Port Type 5 The type 5 bidirectional port is both a bitwise configurable I/O port and provides the external pins for both the Timer 0 and the internal buzzer generator. As a normal port, it performs in exactly the same way as bidirectional port type 2 (see figure 14). Two additional multiplexers allow data and port direction control to be passed over to other internal modules (Timer 0 or Buzzer). Each of the four Port 4 pins can be individually switched by the Timer/Counter I/O Register (TCIO). Figure 17 shows the internal interfaces to Port 4. V DD Pull-up I/O Bus T0In T0Out I/O Bus D S Master reset I/O Bus D (Direction) S Q Q P4DATy (Data out) TCIOy VDD * * BP4y * * Pull-down P4DDRy TDir * Mask options Figure 18. Bidirectional Port 4 96 11527 40 Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 M44C510 2.2.6 TIM1 - Bidirectional Pin Timer 1 V T1IN (Timer 1 input) DD Pull-up * VDD * TIM1 * T1Dir (direction control) T1OUT (Timer 1 output) * * Mask options Figure 19. Bidirectional pin TIM1 Pull-down 96 11528 TIM1 is a dedicated bidirectional I/O stage for signal communication to and from the Timer 1 in the timer/ counter module (see figure 18). It has no I/O bus interface and is not directly accessible from the CPU. The direction control is performed from the timer/counter configuration registers. 2.3 Interval Timers / Prescaler ure 10) and consists of a 15-stage binary divider and two programmable multiplexers for selecting the appropriate interrupt frequencies for each interrupt source (see figure 20). Each multiplexer is completely independent and is controlled by the common Interval Timer Frequency Select Register (ITFSR). Buffer registers store the respective frequency select codes and ensure complete programming independence of each interrupt channel. Interrupt masking and programming of the interrupt priority levels is performed with the aid of the Interval Timer Interrupt Priority Register (ITIPR). FS3 FS2 FS1 FS0 The interval timers are based on a frequency divider for generating two independent time base interrupts. It is driven by SUBCL generated by the clock module (see figITIPR INT5 INT1 Buffer PRB PRA MIB MIA ITFSR Buffer INT6 INT2 Fh Eh Dh INTB Ch 8:1 Bh Mux Ah 9h 8h 8092Hz 2048Hz 4096Hz 8192Hz 4096Hz 2048Hz 1024Hz 256Hz 64Hz 16Hz 8Hz 128Hz 7h 6h 5h INTA 4h 8:1 3h Mux 2h 1h 0h 32Hz 8Hz 16Hz 4Hz 128Hz 64Hz 32Hz 16Hz 8Hz 4Hz 2Hz 1Hz 2Hz 1Hz 1024Hz 256Hz 64Hz R SUBCL CK 2 2 2 3 2 4 2 5 2 6 27 2 8 29 210 2 11 212 213 214 2 15 15-stage binary counter Figure 20. Interval timers / prescaler 96 11530 (e.g. SUBCL = 32 kHz) TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 41 Preliminary Information M44C510 2.3.1 Interval Timer Registers The Interval Timer Frequency Select Register (ITFSR) is I/O mapped to the primary address register of the prescaler/ interval timer address ('F'hex) and the Interval Timer Interrupt Priority Register (ITIPR) to the correInterval Timer Interrupt Priority Register (ITIPR) sponding auxiliary register. The interrupt masks MIA and MIB enable interrupt masking of INTA and INTB respectively. Each interrupt source can be programmed with PRA and PRB to one of two interrupt priority levels. Disabling both interrupts resets the watch timer. AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A Bit 3 Bit 2 Bit 1 Bit 0 ITIPR PRB PRA MIB MIA Reset value: 1111b PRB - Priority select Interval Timer Interrupt INTB PRA - Priority select Interval Timer Interrupt INTA MIB - Mask Interval Timer Interrupt INTB MIA - Mask Interval Timer Interrupt INTA Table 10. Interval Timer Interrupt Priority Register (ITIPR) Auxiliary register address (write only): 'F'hex Code 3210 xx11 xxx1 xxx0 xx1x xx0x x1xx x0xx 1xxx 0xxx Function Reset prescaler and halt Interrupt A disabled Interrupt A enabled Interrupt B disabled Interrupt B enabled Interrupt A => priority 1 Interrupt A => priority 5 Interrupt B => priority 2 Interrupt B => priority 6 Interval Timer Frequency Select Register (ITFSR) Primary register address (write only): 'F'hex Reset value: 1111b Bit 3 FS3 Bit 2 FS2 Bit 1 FS1 Bit 0 FS0 ITFSR FS3 ... 0 - Frequency select code Table 11. Interval Timer Frequency Select Register (ITFSR) AAAAAAA A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAA AAAAAAA A A AA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AA A A AA AAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA A AA AAA INTA INTB The control bit FS3 determines whether the INTA or the INTB buffer register is loaded with the select code (FS2-FS0). This allows independent programming of interval times for INTA and INTB. 42 Code 3210 0000 0001 0010 0011 0100 0101 0110 0111 Function SUBCL divide by 215 214 213 212 211 210 29 28 SUBCL = 32 kHz Select 1 Hz Select 2 Hz Select 4 Hz Select 8 Hz Select 16 Hz Select 32 Hz Select 64 Hz Select 128 Hz Code 3210 1000 1001 1010 1011 1100 1101 1110 1111 Function SUBCL divide by 212 211 29 27 25 24 23 22 SUBCL = 32 kHz Select 8 Hz Select 16 Hz Select 64 Hz Select 256 Hz Select 1024 Hz Select 2048 Hz Select 4096 Hz Select 8192 Hz Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 M44C510 2.4 Watchdog Timer NRST CK R R R R 2 14 2 15 2 16 * 17-stage binary counter R R R R R R R R R R * R R R * SUBCL Read WDRES Master Reset * Watchdog enable VDD Figure 21. Watchdog timer * Mask option 96 11531 The Watchdog timer is a 17-stage binary divider clocked by SUBCL generated within the clock module (see figures 10 and 21). It can only be enabled as a mask option whereby it must be periodically reset from the application program. The program cannot disable the watchdog. If the CPU find itself for an extended length of time in SLEEP mode or in a section of program that includes no watchdog reset, then the watchdog will overflow, thus forcing the NRST pin low. This initiates a master reset. The timeout period can be set to 0.5, 1 or 2 seconds (if SUBCL = 32 kHz) by using a mask option. To reset the watchdog, the program must perform an INinstruction on the address WDRES ('3'hex). No relevant data is received. The operation is therefore normally followed by a DROP to flush the data from the stack. 2.5 Timer/Counter Module (TCM) Timer 1 Control Register (T1CR). Capture and compare registers (T0CA,T1CA,T0CP and T1CP) not only allow event counting, but also the generation of various timed output waveforms including programmable frequencies, modulated melody tones, Pulse Width Modulated (PWM) and Pulse Density Modulated (PDM) output signals. When in one of these signal generation modes, the capture register acts as timer shadow register, the current timer state is freezed whenever read by the CPU. The Timer 0 is further equipped for performing a variety of time measurement operations. In this mode the capture register is used together with the gating logic for performing asynchronous, externally triggered snapshot measurements. These measurements include single input pulse width and period measurements and also dual input phase and positional measurement. The mode configuration is set in the Timer 0 and Timer 1 Mode Registers (T0MO and T1MO). Each timer represents a single maskable interrupt source (T0INT and T1INT), the priority of which can be configured under program control. A Timer 0 interrupt can be caused by any of three conditions (overflow, compare or end-of-measurement). The associated status register (T0SR) differentiates between these. A status register is not necessary in the Timer 1 as an interrupt is caused only on a compare condition. The TCM consists of two timer/counter blocks (Timer 0 and Timer 1) which can be used separately, or together as a single 16-bit counter/timer (see figure 22). Each timer can be supplied by various internal or external clock sources. These can be selected and divided under program control using the Timer/Counter Control Register (TCCR), the Timer 0 Control Register (T0CR) and the TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 43 Preliminary Information M44C510 T0IN1 T0IN0 SYSCL SUBCL Mux 4:1 ck Prescaler rst Gating Control up/down Capture Register T0CA Status Register T0SR TIMER 0 Mux 8:1 T0CR T0MO T1OUT TCMO T0OUT0 16 bit mode Int. Enable Compare Register T1CP T1INT Int T1OUT TCCR Mux 8:1 Mux 2:1 SUBCL SYSCL T1IN Mux 4:1 rst Prescaler ck <= CPU Read/Write Registers Figure 22. Timer/counter module 44 Preliminary Information II II II IIIIIIII II IIIIIIII II IIIIIIII IIIIIIII II IIIIIIII II IIIIIIII IIIIIIII II II II III I II II II II II II T1CR IIIIIIIIII IIIIIIIIII IIIIIIIIII II IIIIIIIIII II IIIIIIIIII II IIIIIIIIII II IIIIIIIIII II IIIIIIIIII II IIIIIIIIII IIIIIIIIII II IIIIIIIIII II Clock Control up/down Counter overflow reset Reload Control Compare T0CP I I I I I I I II I II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II end-of- measurement Output Control Int T0OUT1 T0OUT0 T0INT Compare Register Int. Enable T1MO Output Control carry Reload Control Compare reset Clock Control Up Counter overflow T1CA Capture Register TIMER 1 96 11532 TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 M44C510 2.5.1 General Timer/Counter Control Registers Timer/Counter auxiliary register (TCX) holds the subport address of the particular register about to be accessed. Care has to be taken to ensure that this subport access sequence is not interrupted. With the exception of the Timer 0 Interrupt Status Register (T0SR), all the timer/counter registers are indirectly addressed using extended addressing as described in the section "Addressing peripherals". An overview of all register and subport addresses is shown in table 4. The Timer/Counter Clock Control Register (TCCR) Subport address (indirect write access): '6'hex AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A Bit 3 Bit 2 Bit 1 Bit 0 TCCR T1CL2 T1CL1 T0CL2 T0CL1 Reset value: 1111b T0CL2, T0CL1 - Timer 0 Clock source select T1CL2, T1CL1 - Timer 1 Clock source select Table 12. Timer/Counter Clock Control Register (TCCR) AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A Timer 0 clock = SUBCL Timer 0 clock = SYSCL Timer 0 clock = Timer1 output (T1OUT connected internally) Timer 0 clock = T0IN0 ( BP40*) Timer 1 clock = SUBCL Timer 1 clock = SYSCL Timer 1 clock = Timer 0 output (T0OUT0 connected internally) Timer 1 clock = TIM1 * if TCIO0 = low (connects Timer 0 to Port 4) The Timer/Counter Clock Control Register (TCCR) controls the clock source to both Timer 0 and Timer 1 prescalers. If an external clock source (on BP40 or TIM1) is selected, then the corresponding port direction is automatically switched to input mode (see figure 23). Note: The TCIO0 bit must be set low for the BP40 external timer/counter access. TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 45 Code 3210 xx00 xx01 xx10 xx11 00xx 01xx 10xx 11xx Timer/Counter Subport Pointer (TCX) Address: '9' hex Function Direction (TDir) BP40* TIM1 out x out x out x in x x out x out x out x in Preliminary Information M44C510 Timer/Counter Interrupt Priority Register (TCIP) The Timer/Counter Interrupt Priority register (TCIP) is used to configure the Timer 0 and Timer 1 interrupt priority levels. AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A By using the Timer/Counter I/O Control Register (TCIOR) the program can configure the respective Port 4 pins as either standard data I/O ports or as external signal ports for the Timer 0 and Buzzer. The Timer 1 uses a dedicated I/O pin TIM1, whose direction is controlled solely by the TCCR (see figure 23). It should be noted that if a 46 AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A TCIP Bit 3 T1IP2 Bit 2 T1IP11 Bit 1 T0IP2 Bit 0 T0IP1 Reset value: 1111b T0IP2, T0IP1 - Timer 0 Interrupt Priority code T1IP2, T1IP1 - Timer 1 Interrupt Priority code Table 13. Timer/Counter Interrupt Priority Register (TCIP) Subport address (indirect write access): '7'hex Code 3210 xx11 xx10 xx01 xx00 11xx 10xx 01xx 00xx Timer/Counter Subport Pointer (TCX) Address: '9'hex Function Timer 0 interrupt priority 1 Timer 0 interrupt priority 3 Timer 0 interrupt priority 5 Timer 0 interrupt priority 7 Timer 1 interrupt priority 0 Timer 1 interrupt priority 2 Timer 1 interrupt priority 4 Timer 1 interrupt priority 6 Timer/Counter I/O Control Register (TCIOR) Subport address (indirect write access): '5'hex AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA A A A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA TCIOR Bit 3 TCIO3 Bit 2 TCIO2 Bit 1 TCIO1 Bit 0 TCIO0 Reset value: 1111b TCIO3...0 - Timer / Counter I/0 mode select Table 14. Timer/Counter I/O Control Register (TCIOR) Code 3210 xxx1 xxx0 xx1x xx0x x1xx x0xx 1xxx 0xxx Timer/Counter Subport Pointer (TCX) Address: '9'hex Function BP40 - standard port mode BP40 - Timer 0 clock input (T0IN0) or Timer 0 output (T0OUT0) BP41 - standard port mode BP41 - Timer 0 gate input (T0IN1) or Timer 0 output (T0OUT1) BP42 - standard port mode BP42 - Buzzer output (BUZ) BP43 - standard port mode BP43 - Buzzer output (NBUZ) TCIOR bit is set low, then the corresponding port data direction register (P4DDR) bit no longer influences the port direction. In the case of BP40 and BP41, the port direction is then controlled entirely by the timer/counter configuration registers (TCCR,T0MO), while pins BP42 and BP43 become unidirectional buzzer outputs. Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 M44C510 TIMER 0 T0IN0 P4DAT0 T0OUT0 BP40 to CPU TCIO0 TCCR Select Ext. Clock T0IN1 P4DDR0 P4DAT1 T0OUT1 BP41 to CPU BP42 to CPU T0MO PWM,PDM Melody,Counter TCIO1 P4DDR1 P4DAT2 BUZZER BUZ TCIO2 P4DDR2 '0' P4DAT3 NBUZ BP43 to CPU TCIO3 P4DDR3 TIMER 1 T1IN T1OUT '0' TIM1 TCCR Select Ext. Clock 96 11533 Figure 23. Timer/counter and buzzer external interface Timer/Counter Mode Register (TCMO) AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A TCMO Bit 3 T0NINV Bit 2 TC8 Bit 1 T1RST Bit 0 T0RST Reset value: 1111b T0NINV TC8 - Timer 0 output (BP41) appears non-inverted at BP40 - Timer/Counter in 8-/16-bit mode - Timer 1 Reset/Run - Timer 0 Reset/Run T1RST T0RST Table 15. Timer/Counter Mode Register (TCMO) Subport address (indirect write access): '4'hex Code 3210 xxx0 xxx1 xx0x xx1x x0xx x1xx 0xxx 1xxx Timer/Counter Subport Pointer (TCX) Address: '9'hex Function Timer 0 running Timer 0 reset and halted Timer 1 running Timer 1 reset and halted Timer/counter in 16-bit mode Timer/counter in 8-bit mode Inverted output BP41 appears on BP40 (BP40 = NOT BP41) Non-inverted output BP41 appears on BP40 (BP40 = BP41) TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 47 Preliminary Information M44C510 2.5.2 Timer/Counter in 16-bit Mode Compare Register Compare Register Comparator Carry 8bit/16bit Comparator Compare Interrupt Prescaler Counter Prescaler MUX Counter to TIM1 Overflow/compare Figure 24. 16-bit mode 96 11549 In 16-bit mode, Timer 0 and Timer 1 are cascaded thus forming a 16-bit counter (see figure 24) whereby, irrespective of the state of Timer 0 interrupt mask bit (T0IM), the Timer 1 counts both Timer 0 overflow and compares interrupt events. These are generated according to the state of the Timer 0 Mode Register as described in the T0MO table. The comparators are also cascaded so that when both Timer 0 and Timer 1 match their respective compare registers, the Timer 1 generates both an output signal and a compare interrupt (if unmasked). In measurement modes, only Timer 0 capture register is loaded with Timer 0's contents on an end-of-measurement event. Timer 1 capture register operates solely as a shadow register. There is no 16-bit capture operation, so the user program must check if Timer 1 has incremented between reading the lower and higher byte. Likewise, there is no automatic suppression of spurious interrupts which could conceivably be generated between writing Timer 0 and Timer 1 compare registers. 2.5.3 Timer 0 Modes The Timer 0 mode configuration is defined in the Timer 0 Mode Register (T0MO). The available modes and the effect on the Timer 0 interrupt and interrupt flags is shown below. In all modes except the position measurement mode, Timer 0 acts as an up-counter, the related clock frequency being defined by the selected clock source and the prescaler division factor. The counter can be reset and halted at any time by the T0RST bit of the TCMO register which also resets all the interrupt status flags and capture registers. Whenever Port 4 BP40 and BP41 pins are required for Timer 0 I/O, then the appropriate TCIOR enable bit must be set low. In this case, the port direction switching is handled automatically by the hardware. In modes where the BP40 is not used as a timer clock input or as a melody envelope output, the BP40 outputs the same signal as that appearing on BP41. With the help of the T0NINV bit of the Timer/Counter Mode Register (TCMO), the BP41 output can be inverted so that BP40 and BP41 form a differential output stage which can be used for directly driving piezo buzzers or small stepper motors. 48 Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 M44C510 Timer 0 Mode Register (T0MO) AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A T0MO Bit 3 T0MO3 Bit 2 T0MO2 Bit 1 T0MO1 Bit 0 T0MO0 Reset value: 1111b T0MO3 ... 0 - Timer 0 Mode Code Table 16. Timer 0 Mode Register (T0MO) Subport address (indirect write access): '0'hex Code 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Timer/Counter Subport Pointer (TCX) Address: '9'hex Function Assuming TCIOR1=TCIOR0=low AAAAAAAAAAAA A A A A A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A AAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A reserved reserved Modulated melody mode Melody mode Counter-auto reload (50% duty cycle) Counter-free running (50% duty cycle) Pulse density modulation Pulse width modulation Phase measurement Position measurement Low pulse width measurement High pulse width measurement Counter- auto reload (strobe) Counter-free running (strobe) Period measurement (rising edge) Period measurement (falling edge) *1 Note: *2 Note: *3 Note: The compare interrupt/status flag can only be set when counting up. The overflow interrupt/status flag is set on both an overflow or an underflow. The BP40 signals can be inverted if T0NINV=0 (TCMO register) Timer 0 Interrupt Status Register (T0SR) Auxiliary register address (read access): '9'hex Bit 3 Bit 2 Bit 1 Bit 0 T0SR not used T0EOM T0OFL T0CMP Reset value: x000b Note: The status register is reset automatically when read and also when Timer 0 is reset. T0EOM- Timer 0 End Of Measurement status flag T0OFL - Timer 0 OverFLow status flag T0CMP - Timer 0 CoMPare status flag TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 49 Interrupt set / T0SR affected BP40 (*3) BP41 cmp ofl eom - - - - - - Envelope (out) Tone (out) y/y y/y n/n Tone (out) Tone (out) y/y y/y n/n Toggle (out) /Clock (in) Toggle (out) y/y y/y n/n Toggle (out) /Clock (in) Toggle (out) n/y y/y n/n PDM (out) /Clock (in) PDM (out)AAA y/y n/y n/n PWM (out) /Clock (in) PWM (out) n/y y/y n/n Signal 1 (in) Signal 2 (in) n/n y/y y/y Signal 1 (in) Signal 2 (in) (*1) (*2) n/n Clock (in) Signal (in) n/y y/y y/y Clock (in) Signal (in) n/y y/y y/y Strobe (out) /Clock (in) Strobe (out) y/y y/y n/y Strobe (out) /Clock (in) Strobe (out) n/y y/y n/y Clock (in) Signal (in) n/y y/y y/y Clock (in) Signal (in) n/y y/y y/y Preliminary Information M44C510 Table 17. Timer 0 Interrupt Status Register (T0SR) Code 3210 xxx1 xx1x x1xx Function Timer 0 compare has occurred (Timer 0 = T0CP) Timer 0 overflow or underflow has occurred Timer 0 measurement completed AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA The interrupt flags will be set whenever the associated condition occurs irrespective of whether the corresponding interrupt is triggered. Therefore, the status flags are still set if the interrupt condition occurs when the interrupt is masked. To see exactly when the flags are set, see T0MO control code table 16, page 31. Reading from the timer/counter auxiliary register will access the Timer 0 Interrupt Status Register (T0SR). Timer 0 Control Register (T0CR) The T0CR is responsible for the predivision of the selected Timer 0 input clock (see TCCR). It can be divided or used directly as clock for the up/down counter. Bit 0 is the mask bit for the Timer 0 interrupt. Subport address (indirect write access): '1'hex AAAAAAAAAAAA A A A A A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A T0CR Bit 3 T0FS3 Bit 2 T0FS2 Bit 1 T0FS1 Bit 0 T0IM Reset value: 1111b T0FS3 ... 1 - Timer 0 prescaler division factor code T0IM - Timer 0 Interrupt Mask Table 18. Timer 0 Control Register (T0CR) Code 3210 xxx1 xxx0 000x 001x 010x 011x 100x 101x 110x 111x Timer/Counter Subport Pointer (TCX) Address: '9'hex Function Timer 0 interrupt disabled Timer 0 interrupt enabled Timer 0 prescaler divide by 256 Timer 0 prescaler divide by 128 Timer 0 prescaler divide by 64 Timer 0 prescaler divide by 32 Timer 0 prescaler divide by 16 Timer 0 prescaler divide by 8 Timer 0 prescaler divide by 4 * Timer 0 prescaler bypassed *) Note: Emulation devices marked with C510 - 00x, with x = 4 ... 9, use a prescaler divide by 2. 50 Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 M44C510 Timer 0 Compare Register (T0CP) - Byte Write A AAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAA A A A A A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA A A A A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA Bit 3 Bit 7 Bit 2 Bit 6 Bit 1 Bit 5 Bit 0 Bit 4 T0CP First write cycle T0CP3 T0CP7 T0CP2 T0CP6 T0CP1 T0CP5 T0CP0 T0CP4 Reset value: xxxxb Reset value: xxxxb Second write cycle T0CP3 ... T0CP0 - Timer 0 Compare Register Data (low nibble) - first write cycle T0CP7 ... T0CP4 - Timer 0 Compare Register Data (high nibble) - second write cycle The compare register T0CP is 8-bit wide and must be accessed as byte wide subport (see section "Addressing Peripherals). First of all, the data is written low nibble and is then followed by the high nibble. Any timer interrupts are automatically suppressed until the complete compare value has been transferred. Timer 0 Capture Register (T0CA) - Byte Read Subport address (indirect read access): '9'hex Subport address (indirect write access): '9'hex AAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA A Bit 7 Bit 3 Bit 6 Bit 2 Bit 5 Bit 1 Bit 4 Bit 0 T0CA First read cycle T0CA7 T0CA3 T0CA6 T0CA2 T0CA5 T0CA1 T0CA4 T0CA0 Reset value: 0000b Reset value: 0000b Second read cycle T0CA7. .. T0CA4 - Timer 0 Capture Register Data (high nibble) - first read cycle T0CA3 ... T0CA0 - Timer 0 Capture Register Data (low nibble) - second read cycle Note: If the timer is read (in PDM mode only) the bit order will appear reversed, so that T0CA0 =MSB, T0CA1=MSB-1 .... T0CA6=LSB+1, T0CA7 = LSB. The 8-bit capture register T0CA is read as byte wide subport. Note, however, unlike the writing to the compare register, the high nibble is read first followed by the low nibble. The 8-bit timer state is captured on reading the first nibble and held until the complete byte has been read. During this transfer, the timer is free to continue counting. TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 51 Preliminary Information M44C510 Timer 0 Free Running Counter Modes (Strobe and 50% Duty Cycle) In the free running counter mode, Timer 0 can be used as an event counter for summing external event pulses on BP40, or as a timer with an internal time-based clock. When enabled, the counter will count up generating an output signal on BP41 whenever the counter contents match the compare register (see figure 25). This signal can appear either as a strobe pulse or as a simple toggling of the output state (50% duty cycle) depending on the timer mode. Interrupts (if not masked) are generated every 256 clocks on the overflow condition. The current counter state can be read at any time by reading the capture register,. The compare register has no effect on the counter cycle time and will not influence interrupts. Overflow Interrupt strobe T0OUT1 (BP41) 50% duty cycle Timer Clock Timer resets on overflow Timer = compare register (= 4) Figure 25. Timer 0 free running counter mode Timer 0 Counter Reload Modes (Strobe and 50% Duty Cycle) As in the free running mode, the counter can also be clocked from either an external signal on BP40 or from an internal clock source. In this mode, the counter repetition period is completely defined by the contents of the compare register (T0CP) (see figure 26). The counter counts up with the selected clock frequency. When it reaches the value held in the compare register, the counter then returns to the zero state. At the same time, depending on the selected timer mode, the BP41 either toggles or generates a strobe pulse. If the Timer 0 interrupt is unmasked, a compare interrupt is also generated. The resultant output frequency fOUT = fIN/2*(n+1) where n = compare value (n = 1 - 255). Compare Interrupt strobe T0OUT1 (BP41) 50% duty cycle Timer Clock Timer = compare register (= 7) Resets timer Figure 26. Timer 0 counter reload mode 52 Preliminary Information I I II II I I Timer State 0 1 23 4567 0 123 4567 0 123 4567 0 TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 I 96 11534 96 11535 II II Timer State 255 0 1 2 3 4 56 255 0 1 2 3 4 56 255 0 1 2 3 4 56 M44C510 Motor Chopping and Mask Options In the counter auto reload mode (50% duty cycle), mask options are available for generating a 1 kHz or 2 kHz frequency with duty cycles of 1/2, 3/8, 5/8 and 3/4. The resultant waveform is used as the chopping frequency for so called "motor chopping". This technique allows the use of low cost, low voltage clock motors in applications where only higher supply voltages are available. The resultant voltage waveforms are shown in figure 27. To obtain the required motor driver waveforms on BP40 and BP41 as shown in figure 28, the user program must modulate the Timer 0 chopping frequency. This is performed by preloading Port 4 data latches (P4DAT0 and P4DAT1) with '0' which sets the normal Port 4 direction register bits to output mode (P4DDR0 = P4DDR1 = '0') and switches the TCIO0 and TCIO1 register bits alternately to '0' on every chopping burst. The timer chopping signals are thus transferred to the port outputs. In the intermediate periods between bursts both TCIO0 and TCIO1 are set to '1' and the preloaded Port 4 data latch outputs appear on the port outputs. Timer Clock 3/8* 1/2 T0OUT1 (BP41) 5/8* 3/4* * = Mask Option Timer 0 configuration reload mode, 50% duty cycle, Comparator value = '3'hex (1 kHz) or '7'hex (2 kHz) Timer clock = 32 kHz (prescaler bypassed) Figure 27. Motor chopping waveforms Chopping burst BP41 96 11536 BP40 96 11537 Figure 28. Motor driver output waveforms Melody Mode (with/without Modulation) The non-modulated melody mode is identical to the auto- reload counter (50% duty cycle) mode. The melody tone frequency appearing on BP41 and/or BP40 is determined in exactly the same way as the value written into the comparator register. In the modulated melody mode, the M44C510 generates two output signals, a melody tone and an envelope pulse (see figure 29). The tone frequency output on BP41 is generated in exactly the same way as in the simple melody mode. While the envelope pulse on BP40 is a single pulse, of a clock period in duration which appears shortly after loading the compare value into the compare register. In this mode, an analog switch is activated between the BP40 and BP41 outputs (see figure 30). With the external capacitor connected, the resultant signal on BP41 exhibits a melody chime effect with an exponential decay. TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 53 Preliminary Information M44C510 Timer State Compare Interrupt T0OUT0 (BP40) 01 2 3 4 5 6 01 2 3 4 5 6 01 2 3 4 5 6 0 1 2 3 4 5 6 0246 7 7 7 71357 T0OUT1 (BP41) Timer Clock New value (=7) loaded into compare register Timer = compare register resets timer Figure 29. Modulated melody mode 96 11538 V DD T0OUT0 (melody output) Modulated melody mode T0OUT1 (envelope) V SS T0OUT1 T0OUT0 BP41 BP40 Figure 30. Modulated melody output circuit V DD BP40 R (optional) Analog switch 10...47uF Piezo buzzer VSS BP41 96 11539 54 Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 M44C510 Timer 0 Pulse Width Modulation Mode A pulse width modulated (PWM) signal exhibits a fixed repetition frequency and a variable mark space ratio. It is often used as a simple method for D/A conversion, where the high period is proportional to the digital value to be converted. Therefore by connecting a simple low-pass RC network to the PWM signal, the DC analog value can be gained. Timer 0 generates the PWM signal by comparing the state of the free running up counter with the contents of the compare register (see figure 31). If the result is less than the compare register value, then the BP41 output is high. If the result is greater or equal to the compare register value, then the BP41 output is set low. Thus, the high phase of the PWM signal is directly proportional to the compare register contents. A total of 256 possible discrete mark space ratios can be generated ranging from a continuous low signal over a variable pulse width signal to a continuous high signal. The PWM signal has a repetition period of 256 clock periods, an interrupt (if unmasked) being generated on every overflow event. Care should be taken if the SYSCL clock is used as the PWM clock source because it may stop if the CPU goes into SLEEP mode (see mask options). Overflow Interrupt t_hi T0OUT1 (BP41) Timer Clock t_low Timer = compare register (= 4) t_hi = (comparator value)*clock period t_low = (255-comparator value)*clock period Figure 31. Timer 0 pulse width modulation 96 11540 Pulse Density Modulation Mode Pulse density modulation (PDM) is also used for simple D/A conversion. Unlike the PWM signal,where the high and low signal phases are always continuous during a single repetition cycle, the PDM distributes these evenly as a series of pulses (see figure 32). This has the advantage that, if used together with an RC smoothing filter for D/A conversion, either the ripple is less than the PWM, or, for a corresponding ripple error, the filter components can be smaller or the clock frequency lower. To generate the PDM output on BP41, the pulse density is controlled by the contents of the compare register in the same way as the PWM generation. Each of the pulses has a width equal to the counter clock period. Repetition period PWM=0.25 PWM=0.75 PDM=0.25 PDM=0.75 96 11541 Figure 32. An example 4-bit PWM/PDM comparison TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 Preliminary Information II 55 II II Timer State 255 0 1 2 3 4 255 0 1 3 4 255 0 1 3 4 M44C510 Period Measurement Modes (Rising and Falling Edge) During the period measurement mode, the counter counts the number of either internal or external clocks in one period of the BP41 input signal (see figure 33). Dependent on the mode chosen, this will be from rising edge to the next rising edge or conversely, falling edge to the following falling edge. On the trigger edge, the counter state is loaded into the capture register and subsequently reset. The measured value remains in the capture register until overwritten by the following measured value. Interrupts can be generated by either an overflow condition or an end-of-measurement (eom) event. An 'eom' event signals the CPU that a new measured value is present in the capture register and can be read, if required. Captures and resets timer "eom" Interrupt t_period t_period T0IN1 (BP41) Falling edge triggered Figure 33. Period measurement Rising edge triggered 96 11542 Pulse Width Measurement Modes (High and Low) In this mode, the selected clock source is gated to the counter for the duration of each input pulse received on BP41 (see figure 34). Whether the measurement takes place during the high or low phase depends on the selected mode. At the end of each pulse, the counter state is loaded into the capture register and subsequently reset. Interrupts can be generated by either an overflow condition or an end-of-measurement (eom) event. An 'eom' event signals the CPU that a new measured value is present in the capture register can be read, if required. Captures and resets timer "eom" Interrupt t_low T0IN1 (BP41) 96 11543 t_high Figure 34. Pulse width measurement 56 Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 M44C510 Phase Measurement Mode This mode allows the Timer 0 to measure the phase misalignment between two 1:1 mark space ratio input signals connected to the BP40 and BP41 pins (see figure 35). The counter clock is gated with the phase misalignment period (tp), during which time the counter increments with the selected clock frequency. This misalignment period is defined as the period during which BP40 is high and BP41 is low. Capturing and resetting of the counter always takes place on the rising edge of BP41. The measured value remains in the capture register until overwritten by the next measurement. Interrupts can be generated by either an overflow condition or an end-of-measurement ('eom') event. An 'eom' event signals the CPU that a new measured value is present in the capture register and can be read, if required. Captures & resets timer "eom" Interrupt tp tp tp T0IN0 (BP40) T0IN1 (BP41) Figure 35. Phase measurement 96 11544 Position Measurement Mode This mode is intended for the evaluation of positional sensors with biphase output signals. Figure 36 illustrates a typical positional sensor system which delivers both incremental positional stepping signals and also directional information. The direction can be deduced from the relative phase of the two signals. Therefore if BP40 is high on the rising edge of BP41, the moving mask travels to the left and if it is low then it travels to the right. The direction (left/right) information is used to set the direction of the up/down counter which enables the BP40 pulses to be counted. Assuming that the system has been reset on a reference position, the counter will always hold the absolute current position of the moving mask. This can be read by the CPU if necessary. This mode is the only one in which the counter is allowed to decrement. Therefore, in this case it is possible for both an underflow or an overflow to occur. The overflow interrupt (if unmasked) will trigger on either of these conditions while the compare interrupt on the other hand will only trigger if the counter is counting upwards. To differentiate between an overflow or underflow, the compare value can be set to '0' hex, for example. An overflow would then set both the overflow and compare status flags while an underflow sets the overflow status flag only. T0IN0 T0IN1 Timer T0IN0 (BP40) T0IN1 (BP41) N TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 AAAAAAAA AAAA AAAAAA light light left movement N+1 N+2 N+3 N right movement N-1 N-2 Typical sensor Moving mask Static mask N-3 96 11545 Figure 36. Position measurement mode 57 Preliminary Information M44C510 2.5.4 Timer 1 Modes The Timer 1 is aimed at performing event counting and timing functions (see figure 22). It has, unlike the Timer 0, no gated clock or externally triggered capture modes. The counter counts up with an internal or external clock, depending on the state of the Timer 1 Control Register (T1CR) and the Timer/Counter Clock Control Register (TCCR) and generates a compare interrupt whenever the counter matches the Timer 1 compare regisTimer 1 Mode Register (T1MO) Subport address (indirect write address): '2'hex ter. This is the only Timer 1 interrupt source. Masking can be performed using the mask bit in the Timer 1 Control Register (T1CR) and priority can be defined in the Timer/ Counter Interrupt Priority Register (TCIP). The TIM1 pin is used by the Timer 1 either as clock/event input or timer output. I/O control of the Timer 1 pin TIM1 is controlled entirely by the hardware, therefore if the TIM1 is selected as an external clock or event source (in the TCCR), there can be no Timer 1 signal output. In this case, the timer would be used solely to generate interrupts. AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A T1MO Bit 3 T1MO3 Bit 2 T1MO2 Bit 1 T1MO1 Bit 0 T1MO0 Reset value: 1111b T1MO3 ... 0 - Timer 1 Mode Control Table 19. Timer 1 Mode Register (T1MO) AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A Counter free running (50% duty cycle) Counter auto reload (50% duty cycle) Pulse width modulation Counter auto-reload (strobe output) Increment on falling edge of clock Increment on rising edge of clock reserved Timer 1 Control Register (T1CR) The T1CR is responsible for the predivision of the selected Timer 1 input clock (see TCCR). It can be divided or used directly as clock for the up counter. Bit 0 is the mask bit for the Timer 1 interrupt. Subport address (indirect write access): '3'hex T1CR Bit 3 T1FS3 Bit 2 T1FS2 Bit 1 T1FS1 Bit 0 T1IM Reset value: 1111b T1FS3 ... 1 - Timer 1 Prescaler Division Factor Code T1IM - Timer 1 Interrupt Mask 58 Code 3210 1x00 1x01 1x10 1x11 x0xx x1xx 0xxx Timer/Counter Subport Pointer (TCX) Address: '9'hex Function Compare Interrupt yes yes yes yes - - - Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 M44C510 Table 20. Timer 1 Control Register (T1CR) AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA Timer 1 interrupt disabled Timer 1 interrupt enabled Timer 1 prescaler divide by 256 Timer 1 prescaler divide by 128 Timer 1 prescaler divide by 64 Timer 1 prescaler divide by 32 Timer 1 prescaler divide by 16 Timer 1 prescaler divide by 8 Timer 1 prescaler divide by 4 Timer 1 prescaler bypassed Timer 1 Compare Register (T1CP) - Byte Write Code 3210 xxx1 xxx0 000x 001x 010x 011x 100x 101x 110x 111x Timer/Counter Subport Pointer (TCX) Address: '9'hex Function A AA A A A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA Bit 3 Bit 7 Bit 2 Bit 6 Bit 1 Bit 5 Bit 0 Bit 4 T1CP First write cycle T1CP3 T1CP7 T1CP2 T1CP6 T1CP1 T1CP5 T1CP0 T1CP4 Reset value: xxxxb Reset value: xxxxb Second write cycle T1CP3 ... T1CP0 - Timer 1 Compare Register Data (low nibble) - first write cycle T1CP7. .. T1CP4 - Timer 1 Compare Register Data (high nibble) - second write cycle The compare register T1CP is 8 bits wide and must be accessed as byte wide subport (see section "Addressing Peripherals"). The data is written low nibble first, followed by high nibble. Any timer interrupts are automatically suppressed until the complete compare value has been transferred. Timer 1 Capture Register (T1CA) - Byte Read Subport address (indirect write access): '8'hex AAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA A Bit 7 Bit 3 Bit 6 Bit 2 Bit 5 Bit 1 Bit 4 Bit 0 T1CA First read cycle T1CA7 T1CA3 T1CA6 T1CA2 T1CA5 T1CA1 T1CA4 T1CA0 Reset value: 0000b Reset value: 0000b Second read cycle T1CA7 ... T1CA4 - Timer 1 Capture Register Data (high nibble) - first read cycle T1CA3 ... T1CA0 - Timer 1 Capture Register Data (low nibble) - second read cycle The 8-bit capture register T1CA is read as byte-wide subport. Note, however, unlike the writing to the compare register, the high nibble is read first followed by low nibble. The 8-bit timer state is captured on reading the first nibble and held until the complete byte has been read. During this transfer, the timer is free to continue counting. TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 59 Subport address (indirect read access): '8'hex Preliminary Information M44C510 Timer 1 Counter Free Running (50% Duty Cycle) In the free running counter mode, the counter counts up with either an internal or external clock and cycles through all 256 timer states. On the clock following a match between the compare register (T1CR) and the counter, a compare interrupt (if unmasked) is generated and the TIM1 pin is toggled (see figure 37). 0 2 4 0 2 4 0 2 4 Compare Interrupt T1OUT (TIM1) Timer Clock 50% duty cycle (clock set to rising edge) Timer = compare register (= 4) Figure 37. Timer 1 counter free running (50% duty cycle) Timer 1 Counter Auto Reload (Strobe and 50% Duty Cycle) In the auto-reload mode, the counter counts up with either an internal or external clock. On the clock cycle following a match between the compare register (T1CR) and the counter, a compare interrupt (if unmasked) is generated. The TIM1 output is either strobed or toggled and the counter reset (see figure 38). Therefore, the counter cycle period is defined by the contents of the compare register. In 50% duty cycle mode the frequency of TIM1 is: fTIM1 = fin/2(n+1) where the compare value (n) =1 ... 255. Timer State Compare Interrupt strobe T1OUT (TIM1) 50% duty cycle Timer Clock 0 123 4567 0 123 4567 0 123 4567 0 (clock set to neg. edge) Timer = compare register (= 7) Resets timer Figure 38. Timer 1 counter auto reload 60 Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 II 96 11546 96 11547 I II II I I Timer State 255 1 3 56 255 1 3 56 255 1 3 56 M44C510 Timer 1 Pulse Width Modulation The Timer 1 generates the PWM signal by comparing the state of the free running up counter with the contents of the compare register (see figure 39). If the result is less or equal to the compare register value, then the TIM1 output is high. If the result is greater than the compare register value, then the TIM1 output is set low. Thus, the high phase of the PWM signal is directly proportional to the compare register contents. A total of 256 possible discrete mark space ratios can be generated ranging from a continuous low signal over a variable pulse width signal to a continuous high signal. The PWM signal has a repetition period of 256 clock periods, an interrupt (if unmasked) being generated on every compare event. Care should be taken if the SYSCL clock is used as the PWM clock source because it will stop if the CPU goes into SLEEP. Timer State 0 2 4 0 2 4 0 2 4 255 1 3 255 1 3 255 1 Compare Interrupt t_hi T1OUT (TIM1) Timer Clock t_hi = (comparator value)*clock period t_low = (255-comparator value)*clock period t_low Timer = compare register (=4) 96 11548 Figure 39. Timer 1 pulse width modulation 2.6 Buzzer Module The buzzer is a 4 stage frequency divider which divides the SUBCL and depending on the state of the Buzzer Control Register (BZCR) can output one of four frequencies. An external piezo or buzzer can be driven by the complementary buzzer outputs (BUZ and NBUZ) which are directed to Port 4 (BP42 and BP43) under control of the Timer/Counter I/O Register (TCIOR) as shown in figure 23. When the buzzer is switched off, both of the buzzer outputs take up the same logical state. This is controlled by the BZOP bit of the BZCR. BZCR BZFS2 BZFS1 BZOP BZOF NBUZ SUBCL (32 kHz) SUBCL / 4 (8 kHz) SUBCL / 8 (4 kHz) SUBCL / 16 (2kHz) 4 :1 MUX BUZ SUBCL CK 4 stage divider R R R 96 11550 R Figure 40. Buzzer module TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 Preliminary Information II II 3 II II I I 61 M44C510 BUZ BZOP=1 NBUZ BUZZER Off BUZ BZOP=0 NBUZ 96 11551 Figure 41. Buzzer waveform Buzzer Control Register (BZCR) Subport address (indirect write access): 'A'hex AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A BZCR Bit 3 BZFS2 Bit 2 BZFS1 Bit 1 BZOP Bit 0 BZOF Reset value: 1111b BZFS2, BZFS2 BZOP BZOF - Buzzer Frequency Select code - Buzzer Output Stop State - Buzzer off/on Table 21. Buzzer Control Register (BZCR) Code 3210 xxx0 xxx1 xx0x xx1x 00xx 01xx 10xx 11xx Timer/Counter Subport Pointer (TCX) Address: '9'hex Function Buzzer on Buzzer off Buzzer output stop state: BP42 = BP43 = low Buzzer output stop state: BP42 = BP43 = high Buzzer frequency: 32 kHz (= SUBCL) Buzzer frequency: 8 kHz (= SUBCL / 4) Buzzer frequency: 4 kHz (= SUBCL / 8) Buzzer frequency: 2 kHz (= SUBCL / 16) 62 Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 M44C510 2.7 Emulation emulator contains a special emulation CPU with a MARC4 core and additional breakpoint logic and takes over the core function. The basic function of the emulator is to evaluate the customer's program and hardware in real time. All MARC4 controllers have a special emulation mode. It is activated by setting the TE pin to logic HIGH level after reset. In this mode, the internal CPU core is inactive and the I/O bus is available via port 0 and port 1 to allow the emulator the access to the on-chip peripherals. The EVC I/O-Bus Data EPROM Address TCL Target Chip Port 0 I/O-Controlbus TCL Port 0 TCL RST Port 1 TE RST C lock Mode R eset NRST Application 96 11552 Figure 42. Emulation TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 Port 1 CORE CORE 63 Preliminary Information M44C510 3 3.1 Electrical Characteristics Absolute Maximum Ratings Parameters Symbol VDD VIN tshort Tamb Tstg RthJA Tsld Value -0.3 to + 6.5 indefinite -40 to +85 -40 to +130 110 260 Unit V V s C C K/W C Voltages are given relative to VSS . AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A AAAAA A AAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA Supply voltage Input voltage (on any pin) Output short circuit duration Operating temperature range Storage temperature range Thermal resistance (DIP40) Soldering temperature (t 10 s) VSS -0.3 VIN VDD +0.3 Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any condition above those indicated in the operational section of these specification is not implied. Exposure to absolute maximum rating condition for an extended period may affect device reliability. All inputs and outputs are protected against high electrostatic voltages or electric fields. However, precautions to minimize the build-up of electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g. VDD). 3.2 DC Operating Characteristics Test Conditions / Pins fSYSCL = 2 MHz VDD = 2.4 V VDD = 5.0 V VDD = 6.2 V fSYSCL = 2 MHz VDD = 2.4 V VDD = 5.0 V VDD = 6.2 V VDD = 2.4 V VDD = 6.2 V Symbol Min. Typ. Max. Unit Supply voltage VDD = 5 V, VSS = 0 V, Tamb = 25C unless otherwise specified. Parameters Power supply Active current (CPU active, RC osc. with ext. R 200 kW) Power down current (CPU sleep, RC oscillator active, no 32 kHz osc.) Sleep current (CPU sleep, SYSCL stopped, 32 kHz osc. active) IDD 0.35 1.0 1.25 10 20 25 2 3 mA mA mA A A A A A IPD ISleep 1 4 6 Parameters Test Conditions / Pins Power-on reset threshold voltage POR threshold voltage POR hysteresis Schmitt-trigger input voltage: Negative-going threshold VDD = 2.4 to 6.2 V voltage Positive-going threshold VDD = 2.4 to 6.2 V voltage Hysteresis (VT+ - VT-) VDD = 2.4 to 6.2 V Symbol VPOR VPOR VT- Min. Typ. 2.1 Max. 2.4 Unit V V V V 0.5 VSS 0.3*VDD VDD VT+ VH 0.7*VDD 0.1*VDD 64 Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 AAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAA AAAA A A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A Bidirectional Port BP60 and BP61 (INTx, INTy) Bidirectional Port BPA0...BPA3, BPB0...BPB3 Parameters Input LOW current (2 k pull-up) Parameters Input LOW current (30 k pull-up) Test Conditions / Pins VDD = 2.4 V, VIL= VSS VDD = 5.0 V Test Conditions / Pins VDD = 2.4 V, VIL= VSS VDD = 5.0 V Symbol IIL Symbol IIL -16.5 Min. -20 -120 Min. -0.2 -1.4 Typ. -0.35 -1.7 -20.5 Typ. -27 -160 Max. -0.65 -2.5 -24.7 Max. -40 -200 Unit mA mA Unit A A mA 65 AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAA A AA A AAAA A A A A AAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA A A A A AAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAA A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A All Bidirectional Ports and TIM1 Output HIGH current DR = 12 Output HIGH current DR = 4 Output HIGH current DR = 1 Output LOW current DR = 12 Output LOW current DR = 4 Parameters Input voltage LOW Input voltage HIGH Input LOW current (pull-up) Input HIGH current (pull-down) Output LOW current DR = 1 Test Conditions / Pins VDD = 2.4 to 6.2 V VDD = 2.4 to 6.2 V VDD = 2.4 V, VIL= VSS VDD = 5.0 V VDD = 2.4 V, VIH = VDD VDD = 5.0 V VDD = 2.4 V VOL = 0.2*VDD VDD = 5.0 V VDD = 2.4 V VOL = 0.2*VDD VDD = 5.0 V VDD = 2.4 V VOL = 0.2*VDD VDD = 5.0 V VDD = 2.4 V VOH = 0.8*VDD VDD = 5.0 V VDD = 2.4 V VOH = 0.8*VDD VDD = 5.0 V VDD = 2.4 V VOH = 0.8*VDD VDD = 5.0 V Symbol VIL VIH IIL IOH IOH IOH IOL IOL IOL IIH IIH 0.8* VDD AAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAA AAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A Input Pins: NRST and TE Parameters Test Conditions / Pins Input voltage LOW VDD = 2.4 to 6.2 V Input voltage HIGH VDD = 2.4 to 6.2 V Input NRST with pull-up resistor Input LOW current VDD = 2.4 V, VIL = VSS VDD = 5.0 V Input TE with pull-down resistor Input HIGH current VDD = 2.4 V, VIH = VDD VDD = 5.0 V Symbol VIL VIH IIL 0.8* VDD TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 Preliminary Information -100 -250 Min. VSS Min. VSS -6.1 -4.4 -1.8 -1.7 28 -0.5 -1.0 -6.0 1.0 4.0 0.7 15 200 2.8 2.8 10.5 6.8 -125 -320 Typ. Typ. -7.6 -5.5 -2.2 -2.1 -1.5 -8.5 1.3 30 260 3.5 3.5 0.9 34.4 -0.6 13.1 8.5 M44C510 Max. 0.2*VDD VDD -2.5 -12.0 3.0 10.0 1.1 Max. 0.2*VDD VDD -150 -400 -9.1 -6.6 -2.6 -2.5 40.8 -0.7 50 300 4.2 4.2 15.7 10.2 Unit V V A A A A mA Unit V V mA mA mA mA mA mA mA mA mA mA A A A A AAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 66 Parameters 32-kHz crystal Crystal frequency Series resistance Static capacitance Dynamic capacitance Load capacitance 4 MHz crystal Crystal frequency Series resistance Static capacitance Dynamic capacitance OSCIN SCLIN AAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAA AAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAA A A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAA A A A A A A A AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAA A A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Supply voltage VDD = 2.4 to 6.2 V, VSS = 0 V, Tamb = 25C unless otherwise specified. Crystal Characteristics 3.3 M44C510 Parameters Test Conditions / Pins Timer input timing TIM1, BP40 and BP41 Timer input clock Timer input LOW time Rise / fall time < 10 ns Timer input HIGH time Rise / fall time < 10 ns Interrupt request input timing Int. request LOW time Rise / fall time < 10 ns Int. request HIGH time Rise / fall time < 10 ns System clock SCLIN input clock Rise / fall time < 10 ns Start-up time fx = 4 MHz, VDD = 3.0 V Reset timing Power-on reset time VDD VPOR NRST input LOW time RC oscillator - external resistor Frequency Note 1; Rext = 200 kW Stability Note 1; VDD = 3 to 5.5 V 32-kHz oscillator Start-up time AVDD = 3.0 V Stability Note 2; DAVDD = 100 mV Integrated input / output capacitances AC Characteristics Test Conditions / Pins u Preliminary Information OSCOUT SCLOUT Figure 43. Crystal equivalent circuit Symbol Symbol TPOR TNRST tSQ f/f CIN COUT fTIMx tTIL tTIH fRCe f/f tIRL tIRH f tSX Equivalent circuit fX RS C0 C1 fX RS C0 C1 CL 4*SYSCL Min. Min. 1.8 50 50 50 50 L C1 C0 TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 32.768 30 1.5 3 10 RS Typ. Typ. 200 0.5 0.1 20 20 2.0 4 30 2 3 4 10 4 4.192 50 4.5 15 Max. Max. 12.5 "5 500 2.2 50 10 20 10 1 96 11553 MHz MHz % MHz ms MHz ns ns Unit s ppm pF pF Unit kHz kW pF fF pF s s ns ns pF fF W M44C510 10000 VDD = 5 V M44C510 SCLIN Rext SYSCL ( kHz) VDD 1000 100 100 96 12372 96 12375 1000 Rext (kW) 10000 Figure 44. Clock generation with external resistor 3500 3000 SYSCL ( kHz ) SYSCL ( kHz) 2500 2000 1500 1000 500 0 2 96 12373 Figure 47. SYSCL = f (Rext) 2500 2250 2000 1750 1500 1250 1000 750 500 250 0 Rext = 2.2 M 2 96 12376 Rext = 220 k Rext = 470 k 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD ( V ) VDD ( V ) Figure 45. Internal RC-oscillator frequency = f (VDD) 6.0 5.5 5.0 SYSCL ( MHz ) 4.0 3.5 3.0 2.5 2.0 1.5 1 -40 96 12374 Figure 48. SYSCL = f (VDD, Rext) 2100 VDD = 5 V SYSCL ( kHz ) 4.5 VDD = 5 V 2050 VDD = 3 V 2000 VDD = 3 V 1950 -20 0 20 40 60 80 1900 -10 96 12477 10 30 50 70 90 110 Tamb ( _C ) Tamb ( _C ) Figure 46. Internal RC-oscillator frequency = f (Tamb) Figure 49. SYSCL = f (Tamb); Rext = 220k TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 67 Preliminary Information M44C510 30 VDD = 3 V 25 20 15 Dr = 4 10 5 5 0 0 96 12378 20 Dr = 12 15 I OH ( mA ) VDD = 3 V Dr = 12 IOL ( mA) 10 Dr = 4 Dr = 1 0 0.5 1.0 1.5 VOL ( V ) 2.0 2.5 3.0 96 12380 Dr = 1 0 0.5 1.0 1.5 2.0 2.5 3.0 VDD-VOH ( V ) Figure 50. Typical low output driver 70 60 50 I OH ( mA ) IOL ( mA) 40 30 Dr = 4 20 10 10 0 0 96 12379 Figure 52. Typical high output driver 50 VDD = 5 V Dr = 12 40 30 20 VDD = 5 V Dr = 12 Dr = 4 Dr = 1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 96 12381 Dr = 1 0 1 2 3 4 5 VOL ( V ) VDD-VOH ( V ) Figure 51. Typical low output driver Figure 53. Typical high output driver 68 Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 AAAAA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A Table 22. Pad coordinates TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 4 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Pad Layout SCLOUT SCLIN AVDD Name VSS SCLIN SCLOUT BP61 BP60 BPB3 BPB2 BPB1 BPB0 AVDD OSCIN OSCOUT NRST BPA0 BPA1 BPA2 BPA3 BP10 BP11 BP12 BP13 BP61 BP60 BPB0 BPB2 BPB3 BPB1 OSCIN VSS 10 11 1 2 3 4 5 6 7 8 9 OSCOUT BP73 12 43 X-Coord 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 9.8 263.0 513.1 663.1 813.1 963.1 1113.1 1263.1 1413.1 1563.1 1713.1 BP72 NRST 42 13 BP71 BPA0 41 14 Preliminary Information BP70 BPA1 40 15 BPA2 M44C510 Y-Coord Pad No. 0.0 22 202.6 23 352.6 24 502.6 25 652.6 26 802.6 27 952.6 28 1102.6 29 1252.6 30 1402.6 31 1931.6 32 1931.6 33 1931.6 34 1931.6 35 1931.6 36 1931.6 37 1931.6 38 1931.6 39 1931.6 40 1931.6 41 1931.6AA 42 43 16 VSS Figure 54. Pad assignments 39 BPA3 17 BP10 18 BP53 38 BP11 19 BP52 37 BP12 20 BP51 36 BP13 21 BP50 35 BPC0 22 Name BPC0 TE BPC1 TIM1 BP00 BP01 BP02 BP03 BP40 BP41 BP42 BP43 VDD BP50 BP51 BP52 BP53 VSS BP70 BP71 BP72 BP73 VDD 34 24 23 28 27 26 25 31 30 29 33 32 BP03 BP41 BP02 BP43 BP42 BP40 BP01 TIM1 BP00 BPC1 TE X-Coord 1863.1 2093.0 2103.2 2103.2 2103.2 2103.2 2103.2 2103.2 2103.2 2103.2 2103.2 2103.2 2103.2 1705.2 1555.2 1405.2 1255.2 923.5 755.5 605.5 455.5 305.5 M44C510 Die size: 2.44 x 2.32 mm Thickness: 480 ( 19 Pad size: 100 x 100 mm 96 11554 25 mm 1 mil) Y-Coord 1931.6 1931.6 1675.8 1525.8 1375.8 1225.8 1075.8 925.8 757.5 607.5 457.5 307.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 69 M44C510 5 Application Examples PC keyboard matrix 8 +5V 220 k SCLIN Lock Shift Num 3 * LED Shield 96 11555 16 Port B Port 1 Port 4 Port 5 Port 7 VDD BP60 +5V Data Clock GND PC connector Port A V DD BP02 BP01 BP00 M44C510 BP61 V SS Figure 55. M44C510 as keyboard controller VDD 470 k SCLIN BP73 (Power save) VDD 2.2 V ... 3.6 V 100 nF V SS GND 3x 470 k M44C510 BP72 BP71 BP70 Port A Port B Port 5 COM0 COM1 COM2 3x 470 k 96 12382 Figure 56. Driving a LCD panel with 1/3 duty 70 Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 M44C510 6 Ordering Information Please select the option setting from the list below and insert ROM CRC. DR means driver ratio (= mA @ 3 V) and can be choosen from 1 to 12, however, the hole port must have the same value. Port 0 BP00 DR =_____ BP01 BP02 BP03 J - CMOS Pull-up Pull-down Pull-up Pull-down Pull-up Pull-down Pull-up Pull-down Port 5 Port 1 BP11 BP12 BP13 BP10 DR =_____ CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] BP51 BP52 BP53 BP50 DR =_____ CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] - Pull-up Pull-down Pull-up Pull-down Pull-up Pull-down Pull-up Pull-down Pull-up Pull-down Port 6 Pull-up Pull-down Pull-up Pull-down Port 7 Pull-up Pull-down BP61 BP60 DR =_____ CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] Pull-up Pull-down Pull-up (2 k) Pull-up Pull-down Pull-up (2 k) Port 4 BP41 BP42 BP43 BP40 DR =_____ CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] Pull-up Pull-down Pull-up Pull-down BP71 BP72 BP73 BP70 DR =_____ CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] Pull-up Pull-down Pull-up Pull-down Pull-up Pull-down Pull-up Pull-down Pull-up Pull-down Port C Pull-up Pull-down BPC1 BPC0 DR =_____ CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] Pull-up Pull-down Pull-up Pull-down TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 71 Preliminary Information M44C510 Port A BPA1 BPA2 BPA3 BPA0 DR =_____ CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] - BPA-Reset Pull-up Pull-down Pull-up (30 k) Pull-up Pull-down Pull-up (30 k) Pull-up Pull-down Pull-up (30 k) Pull-up Pull-down Pull-up (30 k) Watchdog SYSCL Type SLEEP CLK Port B BPB1 BPB2 BPB3 BPB0 DR =_____ CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] Pull-up Pull-down Pull-up (30 k) Pull-up Pull-down Pull-up (30 k) Pull-up Pull-down Pull-up (30 k) Pull-up Pull-down Pull-up (30 k) SUBCLK OSCIN OSCOUT SCLIN SCLOUT TIM1 - DR =_____ CMOS Open drain [N] Open drain [P] Package -Pull-up -Pull-down - No BPA0 & BPA1 BPA0 & BPA1 & BPA2 BPA0 & BPA1 & BPA2 & BPA3 Hz 1 Hz 2 Hz 1/ 2 - Disabled R extern RC intern 4 MHz crystal oscillator 4 MHz ceramic resonator SYSCL running SYSCL stopped SYSCL / 64 32 kHz crystal No integrated capacitance Internal CAP ( _ pF) No intergrated capacitance Internal CAP ( _ pF) No integrated capacitance Internal CAP ( _ pF) No integrated capacitance Internal CAP ( _ pF) DIT PDIL40 SSO44 SO28 SO20 File:____________. HEX CRC: _____________ HEX Approval Date: ____-____-____ Signature: _______________ 72 Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 M44C510 We reserve the right to make changes to improve technical design without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2831, Fax Number: 49 ( 0 ) 7131 67 2423 TELEFUNKEN Semiconductors Rev. A2, 24-Jun-96 73 Preliminary Information |
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