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9-BIT LATCH WITH PARITY
SY10E175 SY100E175
FEATURES
s s s s s s s s 9-bit latch Extended 100E VEE range of -4.2V to -5.5V Parity detection/generation 800ps max. D to Output Reset Internal 75K input pull-down resistors Fully compatible with Motorola MC10E/100E175 Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E175 are 9-bit latches. They also feature a tenth latched output (ODDPAR) which is formed as the odd parity of the nine data inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH). The E175 can also be used to generate byte parity by using D8 as the parity-type select (L = even parity, H = odd parity) and using ODDPAR as the byte parity output. The LEN pin latches the data when asserted with a logical high and makes the latch transparent when placed at a logic low level.
BLOCK DIAGRAM
D0 D EN R Q Q0
PIN CONFIGURATION
D8 VCCO Q8 Q7 VCCO
D5
D6 D7
25 24 23 22 21 20 19 26 27 28 1 2 3 4 5 6 7 8 9 10 11 18 17
Q6 Q5 VCC Q4 Q3 VCCO Q2
bits 1-7
D4 D3 VEE
D8
D EN R
Q
Q8
LEN MR D2
TOP VIEW PLCC J28-1
16 15 14 13 12
D1
VCCO ODDPAR Q0
D EN R LEN MR
Q
ODDPAR
PIN NAMES
Pin D0 - D8 LEN MR Q0 - Q8 ODDPAR VCCO Data Inputs Latch Enable Master Reset Data Outputs Parity Output VCC to Output Function
VCCO Q1
Rev.: C
D0
Amendment: /1
1
Issue Date: February, 1998
Micrel
SY10E175 SY100E175
TRUTH TABLE
D H L X X LEN L L H X MR L L L H Q H L Q0 L ODDPAR H if odd no. of Dn HIGH H if odd no. of Dn HIGH Q0 L
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0C Symbol IIH IEE Parameter Input HIGH Current Power Supply Current 10E 100E -- -- 110 110 132 132 -- -- 110 110 132 132 -- -- 110 127 132 152 Min. -- Typ. -- Max. 150 Min. -- TA = +25C Typ. -- Max. 150 TA = +85C Min. -- Typ. -- Max. 150 Unit A mA Condition -- --
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0C Symbol tPLH tPHL Parameter Propagation Delay to Output D to Q D to ODDPAR LEN to Q LEN to ODDPAR MR to Q (tPHL) MR to ODDPAR (tPHL) Set-up Time D (Q) D (ODDPAR) Hold Time D (Q) D (ODDPAR) Reset Recovery Time Within-Device Skew LEN, MR D to Q D to ODDPAR Rise/Fall Times 20-80% Min. 450 850 525 525 525 525 275 900 175 -300 850 -- -- -- 300 Typ. 600 1150 700 700 700 700 100 700 -100 -700 600 75 75 200 500 Max. 800 1450 900 900 900 900 -- -- -- -- -- -- -- -- 800 TA = +25C Min. 450 850 525 525 525 525 275 900 175 -300 850 -- -- -- 300 Typ. 600 1150 700 700 700 700 -- -- -- -- 600 75 75 200 500 Max. 800 1450 900 900 900 900 -- -- -- -- -- -- -- -- 800 TA = +85C Min. 450 850 525 525 525 525 275 900 175 -300 850 -- -- -- 300 Typ. 600 1150 700 700 700 700 -- -- -- -- 600 75 75 200 500 Max. 800 1450 900 900 900 900 ps -- -- ps -- -- -- -- -- -- 800 ps -- ps ps -- 1 -- -- Unit ps Condition --
tS
tH
tRR tskew
tr tf
NOTE: 1. Within-device skew is defined as identical transitions on similar paths through a device.
PRODUCT ORDERING CODE
Ordering Code SY10E175JC SY10E175JCTR SY100E175JC SY100E175JCTR 2 Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial
Micrel
SY10E175 SY100E175
28 LEAD PLCC (J28-1)
Rev. 03
3
Micrel
SY10E175 SY100E175
MICREL-SYNERGY
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FAX
+ 1 (408) 980-9191
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated
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