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Differential Two-Wire Hall Effect Sensor IC
TLE4941 TLE4941C
Features
* * * * * * * * * Two-wire current interface Dynamic self-calibration principle Single chip solution No external components needed High sensitivity South and north pole pre-induction possible High resistance to piezo effects Large operating air-gaps Wide operating temperature range PSSO2-1
* TLE 4941C: 1.8nF overmolded capacitor
Type TLE 4941 TLE 4941C
Marking 4100E 41C0E
Ordering Code Q62705-K427 Q62705-K439
Package PSSO2-1 PSSO2-2
The Hall Effect sensor IC TLE4941 is designed to provide information about rotational speed to modern vehicle dynamics control systems and ABS. The output has been designed as a two wire current interface. The sensor operates without external components and combines a fast power-up time with a low cut-off frequency. Excellent accuracy and sensitivity is specified for harsh automotive requirements as a wide temperature range, high ESD and EMC robustness. State-ofthe art BiCMOS technology is used for monolithic integration of the active sensor areas and the signal conditioning circuitry. Finally, the optimised piezo compensation and the integrated dynamic offset compensation enable easy manufacturing and elimination of magnet offsets. The TLE4941C is additionally provided with an overmolded 1.8nF capacitor for improved EMI performance.
TLE4941, TLE4941C
Functional Description The differential hall sensor IC detects the motion of ferromagnetic and permanent magnet structures by measuring the differential flux density of the magnetic field. To detect the motion of ferromagnetic objects the magnetic field must be provided by a back biasing permanent magnet. Either south or north pole of the magnet can be attached to the rear unmarked side of the IC package. Magnetic offsets of up to +/- 20mT and device offsets are cancelled by a selfcalibration algorithm. Only a few transitions are necessary for self-calibration. After the initial calibration sequence switching occurs when the input signal is crossing the arithmetic mean of its max and min value. (E.g. zero-crossing for sinusoidal signals) The ON and OFF state of the IC are indicated by High and Low current consumption. Circuit Description The circuit is supplied internally by a 3V voltage regulator. An on-chip oscillator serves as clock generator for the digital part of the circuit. TLE4941 signal path is comprised of a pair of hall probes, spaced at 2.5mm, a differential amplifier including a noise-limiting low-pass filter and a comparator feeding a switched current output stage. In addition an offset cancellation feedback loop is provided by a signal-tracking A/D converter, a digital signal processor (DSP) and an offset cancellation D/A converter. During the startup phase (un-calibrated mode) the output is disabled (I=ILow). The differential input signal is digitized in the speed A/D converter and fed into the DSP. The minimum and maximum values of the input signal are extracted and their corresponding arithmetic mean value is calculated. The offset of this mean value is determined and fed into the offset cancellation DAC. After successful correction of the offset, the output switching is enabled. In running mode (calibrated mode) the offset correction algorithm of the DSP is switched into a low-jitter mode, avoiding oscillation of the offset DAC LSB. Switching occurs at zero-crossing. It is only affected by the (small) remaining offset of the comparator and by the remaining propagation delay time of the signal path, mainly determined by the noise-limiting filter. Signals below a defined threshold BLimit are not detected to avoid unwanted parasitic switching.
TLE4941 - TLE 4941C Data Sheet
2
Febrary 2002
TLE4941, TLE4941C
Pin Configuration (view on branded side of component)
2.67
S 0015 S 0015 4942 4100E
Date Code Marking
1.44 2.5
VCC
GND
VCC
GND
Figure 1
"Vcc"
power supply regulator
main comp oscillator
(syst clock)
"GND"
hall probes
-
-
PGA
speed ADC digital
offset DAC
gain range
circuit
Figure 2
Block diagram
TLE4941 - TLE 4941C Data Sheet
3
Febrary 2002
TLE4941, TLE4941C
Absolute Maximum Ratings Tj = -40 to 150C, 4.5V Vcc 16.5V Parameter Supply voltage Supply voltage Supply voltage Supply voltage Supply voltage Supply voltage Reverse polarity current Junction temperature Junction temperature Junction temperature Junction temperature Active lifetime Storage Temperature Thermal Resistance PSSO2-1 ESD Symbol Vcc Vcc Vcc Vcc Vcc Vcc Irev Tj Tj Tj Tj tB,active Ts RthJA UESD 10000 -40 Limit values Min Max -0.3 16.5 20 22 24 27 200 150 160 170 190 150 190 2 Unit Remarks Tj < 80C Tj = 170C Tj = 150C t = 10 * 5 min t = 10 * 5 min, RM 75 t = 400 ms, RM 75 External current limitation required, t < 4h 5000 h, Vcc < 16.5V 2500 h, Vcc < 16.5V 500 h, Vcc < 16.5V 4 h, Vcc < 16.5V
V V V V V mA C C C C h C K/W kV
1)
According to standard EIA/JESD22-A114-B HBM 2) R=1500 , C=100pF
1) can be improved significantly by further processing like overmolding 2) covers MIL STD 883D
Note: Stresses in excess of those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
TLE4941 - TLE 4941C Data Sheet
4
Febrary 2002
TLE4941, TLE4941C
Operating Range Parameter Supply voltage Supply voltage ripple Junction temperature Junction temperature Pre-induction Pre-induction offset between outer probes Differential Induction Symbol VCC VAC Tj Tj B0 Bstat., l/r B Limit values Min Max 4.5 20 6 -40 150 170 +500 +20 +120 Unit V Vpp C C mT mT mT Remarks
VCC=13V 0 < f < 50kHz VCC 16.5V, increased jitter permissible
-500 -20 -120
Note: Within the operating range the functions given in the circuit description are fulfilled.
TLE4941 - TLE 4941C Data Sheet
5
Febrary 2002
TLE4941, TLE4941C
AC/DC Characteristics All values specified at constant amplitude and offset of input signal Limit values Unit Parameter Symbol Min Typ Max Supply current ILow 5.9 7 8.4 mA Supply current IHigh 11.8 14 16.8 mA Supply current ratio IHigh/ILow 1.9 tr, tf 12 26 Output rise/fall mA/s slew rate 7.5 24 TLE 4941 Output rise/fall slew rate TLE4941C Current ripple dIX/dVCC Limit threshold Initial calibration delay time Magnetic edges required for initial calibration1) Frequency Frequency changes Duty cycle tr, tf 8 8 IX BLimit t d,input nstart 22 26 90 1.5 300 6* A/V mT s magn. edges Hz Hz/ms % mA/s Remarks
RM 150 RM 750 See Figure 4. RM = 75 T < 125C T < 170C See Figure 4.
0.35
0.8
Additional to nstart
3
f df/dt duty
1 40 50
2500 100 60
2)
Jitter, Tj < 150C Tj < 170C Jitter, Tj < 150C Tj < 170C Jitter at board net ripple
* See appendix B
SJit-close
2 3
% % % % %
SJit-far
4 6
SJit-AC
2
Measured @B = 2mT sine wave Def. Figure 4 1 s value VCC = 12 V ?B 2mT 1 s value VCC = 12 V (2mT ) B > BLimit VCC=13V6Vpp 0 < f < 50kHz B = 15 mT
The sensor requires up to nstart magnetic switching edges for valid speed information after power-up or after a stand still condition. During that phase the output is disabled.
2)
1)
During fast offset alterations, due to the calibration algorithm, exceeding the specified duty cycle is permitted for short time periods.
TLE4941 - TLE 4941C Data Sheet
6
Febrary 2002
TLE4941, TLE4941C
Output Description Under ideal conditions, the output shows a duty cycle of 50 %. Under real conditions, the duty cycle is determined by the mechanical dimensions of the target wheel and its tolerances. (40% to 60% might be exceeded for pitch >> 5mm due to the zerocrossing principle.)
Speed signal sensor internal
Transferred speed signal
Figure 3
Speed Signal (half a period = 0.5 * 1/fspeed)
I
tr tf 90% 50% 10%
IHigh
ILow
t1 T
t
Figure 4
Definition of rise and fall time, duty = t1/T * 100%
TLE4941 - TLE 4941C Data Sheet
7
Febrary 2002
TLE4941, TLE4941C
Electro Magnetic Compatibility - (values depend on RM!)
Ref. ISO 7637-1; test circuit 1; B = 2mT (amplitude of sinus signal); VCC=13.5 V, fB= 100 Hz; T= 25C; RM 75 No. 1.1.1 Parameter Testpulse 1 Testpulse 2 Testpulse 3a Testpulse 3b Testpulse 4 Testpulse 5
(1) (2)
Symbol
Level/typ. IV / -100 V IV / 100 V IV / -150 V IV / +100 V IV / -7 V IV / +86,5 V
(2)
Status C C
(1) (1)
VLD
A A B
(3)
C
According to 7637-1 the supply switched OFF" for t=200ms. For battery ON" is valid status A". Applying in the board net a suppressor diode with sufficient energy absorption capability. (3) According to 7637-1 for test pulse 4 the test voltage shall be 12V 0,2V
Values are valid for all TLE4941/42 types!
Ref. ISO 7637-3; test circuit 1; B = 2mT (amplitude of sinus signal); VCC=13.5 V, fB= 100 Hz; T= 25C; RM 75 No. 1.2.1 Parameter Testpulse 1 Testpulse 2 Testpulse 3a Testpulse 3b Values are valid for all TLE4941/42 types! Symbol VLD Level/typ. IV / -30 V IV / 30 V IV / -60 V IV / 40 V Status A A A A
Ref. ISO 11452-3; test circuit 1; measured in TEM-cell B = 2mT; VCC=13.5V, fB= 100 Hz; T= 25C No. 1.2.2 Parameter EMC field strength
Symbol
Level/Max. IV / 200 V/m
Remarks AM=80%, f=1kHz;
ETEM-Cell
Only valid for non C- types!
Ref. ISO 11452-3; test circuit 1; measured in TEM-cell B = 2mT; VCC=13.5V, fB= 100 Hz; T= 25C Symbol No. Parameter 1.2.2 EMC field strength ETEM-Cell
Level/Max. IV / 250 V/m
Remarks AM=80%, f=1kHz;
Only valid for C-types!
TLE4941 - TLE 4941C Data Sheet
8
Febrary 2002
TLE4941, TLE4941C
D1
VCC GND
Sensor
VEMC
D2
C1 RM C2
EMC- Generator
Mainframe
Components: D1: D2: C1: C2: RM:
1N4007 T 5Z27 1J 10F/35V 1nF/1000V 75/5W
Figure 5
Test Circuit 1
TLE4941 - TLE 4941C Data Sheet
9
Febrary 2002
TLE4941, TLE4941C
Package Outlines PSSO2-1 (Plastic Single Small Outline Package)
TLE4941 - TLE 4941C Data Sheet
10
Febrary 2002
TLE4941, TLE4941C
PSSO2-2 (Plastic Single Small Outline Package)
TLE4941 - TLE 4941C Data Sheet
11
Febrary 2002

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