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FEATURES 500 MHz Driver Operation (1 Gb/s) Driver Inhibit Function 100 ps Edge Matching Guaranteed Industry Specifications 20 Output Impedance 5 V/ns Slew Rate Variable Output Voltages for ECL, TTL, and CMOS High-Speed Differential Inputs for Maximum Flexibility Ultrasmall 100-Lead LQFP Package with Built-In Heat Sink APPLICATIONS Automatic Test Equipment Semiconductor Test Systems Board Test Systems Instrumentation and Characterization Equipment
Quad Ultrahigh-Speed Pin Driver with High-Z and VTERM Modes AD53513
FUNCTIONAL BLOCK DIAGRAM
VCC
VCC1 VCC2
VEE
VCC3 VCC4 VEE3 VEE1 VEE2 VEE4
RLD1 VBB VH1 DATA1 DATAB1 INH1 INHB1 VL1 VT1 VH2 DATA2 DATAB2 INH2 INHB2 VL2 VT2 VBB RLD2 RLD3 VBB VH3 DATA3 DATAB3 INH3 INHB3 VL3 VT3 VH4 DATA4 DATAB4 INH4 INHB4 VL4 VT4 VBB RLD4 GND
VHDCPL1 39nF 20 ROUT VOUT1 VLDCPL1 30 39nF 50
DRIVER 1
VHDCPL2 39nF 20 ROUT VOUT2 VLDCPL2 30 39nF 50
DRIVER 2
PRODUCT DESCRIPTION
AD53513
VHDCPL3 39nF 20 ROUT VOUT3 VLDCPL3 30 39nF 50
The AD53513 is a quad high-speed pin driver designed for use in digital or mixed-signal test systems. Combining a high-speed monolithic process with a convenient surface-mount package, this product attains superb electrical performance while preserving optimum packaging densities and long-term reliability in a 100-lead, LQFP package with built-in heat sink. Featuring unity gain programmable output levels of -2.5 V to +5.5 V, with output swing capability of less than 200 mV to 8 V, the AD53513 is designed to stimulate ECL, TTL, and CMOS logic families, as well as high-speed memory. The 1.0 Gb/s data rate capacity and matched output impedance allow for real-time stimulation of these digital logic families. To test I/O devices, the pin driver can be switched into a high impedance state (Inhibit Mode), electrically removing the driver from the path. The pin driver leakage current in inhibit is typically 100 nA and output charge transfer entering inhibit is typically less than 20 pC. The AD53513 transition from HI/LO or to inhibit is controlled through the data and inhibit inputs. The input circuitry uses high-speed differential inputs with a common-mode range of 2 V. This allows for direct interface to precision differential ECL timing. The analog logic HI/LO inputs are equally easy to interface. Typically requiring 10 A of bias current, the AD53513 can be directly coupled to the output of a digitalto-analog converter. Each channel of the AD53513 has a Mode Select Pin RLD, which is a single-sided logic input. The logic threshold is set by
DRIVER 3
VHDCPL4 39nF 20 ROUT VOUT4 VLDCPL4 30 39nF 50
DRIVER 4
TVCC GND GND GND GND 1.0 A/K THERM
the VBB input which is common to all four channels. The RLD Mode Select controls whether inhibit puts the driver in High-Z or VTERM mode. (Refer to Table I.) All of the digital logic inputs (DATA, DATAB, INH, INHB, RLD, VBB), must share a common set of logic levels. The VBB threshold should be set to the midrange of the logic levels. For example, if ECL levels of -0.8 V to -1.8 V are used, VBB should be set to -1.3 V. The AD53513 is available in a 100-lead, LQFP package with a built-in heat sink and is specified to operate over the ambient commercial temperature range of -25C to +85C.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
3% unless otherwise noted. All temperature coefficients are measured J S S at TJ = 75 C-95 C). (A 39 nF capacitor must be connected between VCC and VHDCPL and between VEE and VLDCPL.)
Parameter DIFFERENTIAL INPUT CHARACTERISTICS (Data to DATA, INH to INH), RLD, VBB Input Voltage Differential Input Range Bias Current VBB Threshold Input REFERENCE INPUTS (VL, VH, VT) Bias Currents OUTPUT CHARACTERISTICS Logic High Range Logic Low Range Amplitude (VH-VL) Absolute Accuracy VH Offset VH Gain and Linearity Error VL Offset VL Gain and Linearity Error VT Offset VT Gain and Linearity Error Offset TC, VH, or VL, or VTERM Output Resistance Output Leakage Dynamic Current Limit Static Current Limit Min Typ* Max Unit Test Conditions VBB = -1.3 V -2 ECL -1 Midrange -50 -2.3 -2.5 0.2 -100 0.3 5 -100 0.3 5 -100 0.3 5 0.5 20 -1.0 130 85 +1.0 +100 +100 +50 +5.5 +5.3 8.0 +100 +1 mA V A Volts Volts Volts mV % of VH + mV mV % of VL + mV mV % of VT + mV mV/C A mA mA VIN = -2 V, 0.0 V Set to Midrange of Logic Levels VL , VH = 2 V DATA = H DATA = L 0 Volts
AD53513-SPECIFICATIONS -V = -6 V (All specifications are at T = 85 C 5 C, +V = +9 V 3%,
PSRR, Drive Mode DYNAMIC PERFORMANCE, DRIVE (VH and VL ) Propagation Delay Time Propagation Delay TC Delay Matching, Edge to Edge Rise and Fall Time 1 V Swing 2 V Swing 3 V Swing Rise and Fall Time TC 1 V Swing 2 V Swing 3 V Swing Overshoot, Undershoot, and Preshoot
35
dB
DATA = H, VH = 0 V, VL = -2 V, VT = +3 V DATA = H, VH = -2 V to +5 V, VL = -2.5 V, VT = +3 V DATA = L, VL = 0 V, VH = +5 V, VT = +4.5 V DATA = L, VL = -2 V to +5 V, VH = +5.5 V, VT = +4.5 V Term Mode, VT = 0 V, VL = -1 V, VH = +3 V Term Mode, VT = -2.0 V to +5.0 V, VL = 0, VH = +3 V VL , VH = 0 V DATA = H, VH = 3 V, VL = 0 V, IOUT = 45 mA VOUT = -2 V to +5 V CBYP = 39 nF, VH = +5 V, VL = -2 V Output to -2.5 V, VH = +5.5 V, VL = -2.5 V, VT = 0; DATA = H and Output to 5.5 V, VH = +5.5 V, VL = -2.5 V, VT = 0 VL = -3 V, DATA = L VS = VS 3%
0.3 0.5 100
1.1
ns ps/C ps
Measured at 50%, VH = 800 mV, 50 Load, VL = -800 mV Measured at 50%, VH = 800 mV, 50 Load, VL = -800 mV Measured at 50%, VH = 800 mV, 50 Load, VL = -800 mV Measured 20%-80%, VL = 0 V, VH = 1 V, VT = -2 V Measured 10%-90%, VL = 0 V, VH = 2 V, VT = -2 V Measured 10%-90%, VL = 0 V, VH = 3 V, VT = -2 V Measured 20%-80%, VL = 0 V, VH = 1 V, VT = -2 V Measured 10%-90%, VL = 0 V, VH = 2 V, VT = -2 V Measured 10%-90%, VL = 0 V, VH = 3 V, VT = -2 V a. VL , VH = 0 V, +1 V, VT = -2 V, 50 b. VL, VH = 0 V, +3 V, VT = -2 V, 50 c. VL, VH = 0 V, +5 V, VT = -2 V, 50 VL = 0 V, VH = +0.5 V, VT = -2 V VL = 0 V, VH = +0.5 V, VT = -2 V VL = 0 V, VH = +2 V, VT = -2 V, Pulsewidth/Period = 1.0 ns/4.0 ns, 30 ns/120 ns 700 ps Input, 10%/90% Output, VT = -2 V, VL = 0 V, VH = +2 V, 50 Terminated VL = -1.8 V, VH = -0.8 V, VT = -2 V, VOUT > 300 mV p-p at 50 Terminated
300 450 650 1 1 1 (6% +50 mV)
ps ps ps ps/C ps/C ps/C % of Step + mV
Settling Time to 15 mV to 4 mV Delay Change vs. Pulsewidth Minimum Pulsewidth 2 V Swing Toggle Rate
50 10 10
ns s ps
700 3.2
ps GHz
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AD53513
Parameter DYNAMIC PERFORMANCE, INHIBIT Delay Time, Active to Inhibit Delay Time, Inhibit to Active I/O Spike Output Capacitance DYNAMIC PERFORMANCE, VTERM Delay Time, Active to VTERM Delay Time, VTERM to Active Overshoot, Undershoot, and Preshoot VTERM to VL or VH POWER SUPPLIES Total Supply Range Positive Supply Negative Supply Positive Supply Current Negative Supply Current Total Power Dissipation Temperature Sensor Gain Factor Min 1.5 0.7 <200 6 0.50 0.45 6%/ 75 1.30 1.25 Typ* Max 2.5 1.7 Unit ns ns mV p-p pF ns ns mV Test Conditions Measured at 50%, VH = +2 V, VL = -2 V, VT = -2 V Measured at 50%, VH = +2 V, VL = -2 V, VT = -2 V VH = 0 V, VL = 0 V, VT = -2 V Driver Inhibited Measured at 50%, VH = +0.8 V, VL = -0.8 V, VT = 0 V 50 Terminated VL = -2 V, VH = +2 V, VT = 0 V VL = -0.8 V, VH = +0.8 V, VT = 0 V Output Terminated 50
15 9 -6 570 570 8.6 1.0
V V V mA mA W A/K
RLOAD = 4.2 k, VSOURCE = 9 V
NOTES Connecting or shorting the decoupling capacitors to ground will result in the destruction of the device. *Typical parameters are not production tested but guaranteed through characterization. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
Power Supply Voltage +VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 V -VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7 V +VS to -VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Inputs DATA, DATA, INH, INH, RLD, VBB . . . . . . . +5 V, -3 V DATA to DATA, INH to INH, RLD, VBB . . . . . . . . . 3 V VH, VL, VT to GND . . . . . . . . . . . . . . . . . . . . . . +7 V, -2 V VH to VL (VH - VT) and (VT - VL) . . . . . . . . . . . . . . . . 9 V Outputs VOUT Short Circuit Duration . . . . . . . . . . . . . . . Indefinite2 VOUT Range in Inhibit Mode VHDCPL . . . . . Do Not Connect Except for Capacitor to VCC VLDCPL . . . . . Do Not Connect Except for Capacitor to VEE THERM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 V, 0 V
Environmental Operating Temperature (Junction) . . . . . . . . . . . . . . . 175C Storage Temperature . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec)3 . . . . . . . . . . . 260C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Absolute maximum limits apply individually, not in combination. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Output short circuit protection is guaranteed as long as proper heat sinking is employed to ensure compliance with the operating temperature limits. 3 To ensure lead coplanarity ( 0.002 inches) and solderability, handling with bare hands should be avoided and the device should be stored in environments at 24 C 5C (75F 10F) with relative humidity not to exceed 65%.
ORDERING GUIDE Package Description 100-Lead LQFP-CDQUAD Shipment Method, Quantity Per Shipping Container Tray, 90 Pieces Package Option SQ-100
Model AD53513JSQ
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD53513 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD53513
PIN CONFIGURATION
98 VHDCPL1 97 VCC 93 PWRGND 91 PWRGND 90 PWRGND 88 PWRGND 85 PWRGND 83 PWRGND 82 PWRGND 80 PWRGND
s
94 THERM
95 TVCC
77 RLD1
100 VT1 99 VT2
76 RLD2
96 VCC
87 VCC
86 VCC
79 VEE
78 VEE
92 VH1
84 VH2
89 VL1
81 VL2
HQGND1 HQGND1 OUT1 HQGND1 VLDCPL1 PWRGND VHDCPL2 HQGND2 OUT2 HQGND2 HQGND2 VLDCPL2 PWRGND VLDCPL3 HQGND3 HQGND3 OUT3 HQGND3 VHDCPL3 PWRGND VLDCPL4 HQGND4 OUT4 HQGND4 HQGND4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
40 42 47 41 30 34 35 43 46 27 32 44 28 29 33 37 38 45 48 49 31 36 39 50 26
PIN 1 IDENTIFIER
73 DATAB1 72 INH1 71 INB1
HEAT SLUG
70 PWRGND 69 INHB2 68 INH2 67 VEE 66 VEE 65 DATAB2
AD53513
TOP VIEW (Not to Scale)
64 DATA2 63 PWRGND 62 DATA3 61 DATAB3 60 VEE 59 VEE 58 INH3 57 INHB3 56 PWRGND 55 INHB4 54 INH4 53 DATAB4 52 DATA4 51 GND
NC = NO CONNECT
NOTE THAT THE DIE IS MOUNTED TO THE BACK OF THE HEAT SLUG. THE PACKAGE IS MOUNTED TO THE BOARD HEAT SLUG UP.
DATA 0 1 X X
NC VBB VT4 VT3 VHDCPL4 VCC VCC PWRGND VH4 PWRGND PWRGND VL4 PWRGND VCC VCC PWRGND VH3 PWRGND PWRGND VL3 PWRGND VEE VEE RLD4 RLD3
Table I. Driver Truth Table
DATA 1 0 X X
INH 0 0 1 1
INH 1 1 0 0
RLD X X 0 1
VBB VBB VBB VBB VBB
Output State VL VH INH VTERM
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
100-Lead LQFP_ED Package (SQ-100)
0.063 (1.60) MAX 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) SEATING PLANE 0.630 (16.00) BSC 0.551 (14.00) BSC 0.472 (12.00) BSC
100 1 76 75
0.551 (14.00) BSC TOP VIEW
(PINS DOWN)
0.057 (1.45) 0.055 (1.40) 0.053 (1.35)
0.008 (0.20) 0.004 (0.09) 7 3.5 0
0.472 (12.00) BSC 0.630 (16.00) BSC
50
0.006 (0.15) 0.002 (0.05)
VIEW A
0.003 (0.08) MAX
ROTATED 90 CCW
VIEW A
25 26 49
0.020 (0.50) BSC LEAD PITCH
0.011 (0.27) 0.009 (0.22) 0.007 (0.17)
-4-
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PRINTED IN U.S.A.
C01540-0-1/02(0)
75 GND 74 DATA1

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