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MultiG E NTM GF9102A G
Decimating/Interpolating Digital Filter
DATA SHEET
FEATURES * improved performance over TMC2242 in applications not requiring 1:1 low pass filtering * low power (60mA typical at = 20MHz) * 40 MHz maximum clock rate * single device exceeds CCIR 601 lowpass filter requirements * true unity gain (0.0 dB) at DC * reduced output ringing with constant input in interpolation mode * built-in TRS code protection * 12 bit inputs and 16 bit outputs in 2's complement signed or unsigned formats * user-selectable 8 to 16 bit output rounding * can also be operated as a 9 or 21 tap chroma bandpass filter under user control * single +5 V power supply * three state outputs APPLICATIONS * CCIR 601-compliant oversampling video A/D and D/A conversion * 2:1 interpolation and decimation * 4:2:2 to 4:4:4 format conversion * Chroma bandpass filtering ORDERING INFORMATION
Part Number GF9102ACPM GF9102ACTM Package Type 44 Pin PLCC 44 Pin PLCC Tape
CLK DEC
DEVICE DESCRIPTION The GF9102A is a linear phase FIR digital filter that is usable in a variety of video signal processing applications. The device contains three separate fixed coefficient filters and can be operated in three basic modes: 53 tap low pass filter, 9 tap chroma bandpass filter or 21 tap chroma bandpass filter. In the 53 tap low pass filter mode, the GF9102A can replace the TMC2242 in all applications, except those requiring 1:1 low pass filtering, for improved performance and full CCIR 601 compatibility. Specific improvements include true unity gain at DC, 12.4 dB attenuation at s/4 with a single device, reduced output ringing with constant input in interpolate mode, support for signed and unsigned data formats, rounding to 10 and 8 bit CCIR 601 data formats, masking of serial digital TRS codes in the data stream, and elimination of the non-saturated-type overflow condition. The device can be operated in both TMC2242 compatible modes and in GF9102A enhanced modes. When used as a decimating post-filter with a double speed oversampling analog-digital converter, the device greatly reduces the cost and complexity of the associated analog anti-aliasing pre-filter. In a similar fashion, when used as an interpolating pre-filter with a double speed oversampling digitalanalog converter, the GF9102A simplifies the analog reconstruction post-filter. The GF9102A also exceeds the requirements for conversion between 4:2:2 and 4:4:4 signal formats. For chroma filtering applications, the GF9102A can be operated as a 9 or 21 tap bandpass filter by selecting the appropriate operating mode. The GF9102A is packaged in a 44 pin PLCC and is pin compatible with the TMC2242. The device operates with a single +5 V supply.
Temperature Range 0 to 70 C 0 to 70 C
INT SYNC
RND2..0
TCO
TIMING CONTROLS
OUTPUT FORMAT
SO3..0
DATA IN SI11..0
INPUT PROCESSING UNIT
BPF1 BPF2 53 TAP LPF
M U X
OUTPUT PROCESSING UNIT
DATA OUT SO15..0
Revision Date: February 1996
FUNCTIONAL BLOCK DIAGRAM
OE
Document No. 521 - 26 - 02
GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-5946
Gennum Japan Corporation: A-302 Miyamae Village, 2-10-42 Miyamae, Suginami-ku, Tokyo 168, Japan tel. (03) 3334-7700 fax (03) 3247-8839
PIN DESCRIPTION
SYMBOL CLK SYNC
PIN NO. 42 43
TYPE I I
DESCRIPTION System Clock. TTL input. All timing specifications are referenced to the rising edge of clock. Data Synchronization. TTL input with internal pull-up. This input is used to synchronize the incoming data with the GF9102A by holding SYNC high on clock N and low on clock N+1 when the first data word is presented to the input SI11..0 . SYNC may be held low until resynchronization is desired, or it may be clocked at half the clock rate.
SI11..0
40, 37, 36, 35, 34, 33, 32, 31, 30, 27, 26, 25
I
Input Data Port. TTL inputs with internal pull-downs. Data is presented to this registered 12-bit data input port. This port can be programmed as two's complement signed or unsigned binary format. See the following section on input data format. Data is latched internally on every clock in decimate mode, and on every other clock in interpolate mode. SI11 is the MSB.
TCO
2
I
Two's Complement Output Format Control. TTL input with internal pull-down. When TCO is high, output data is presented in two's complement format. When TCO is low, the output is inverted offset binary, obtained by inverting bits SO14 through SO0, leaving SO15 unchanged.
INT
44
I
Interpolate. Active low TTL input with internal pull-up. When the interpolate control is low, data is input at full clock speed and the chip inserts zeros between samples, padding the input to match the output rate. The GF9102A then interpolates between these alternate input data points to achieve full output data rate.
DEC
1
I
Decimate. Active low TTL input with internal pull-down. When the decimate control is low, the output register is driven at half system clock speed, decimating the output data stream. When DEC and INT are low, the GF9102A will be programmed as a 21 tap or 9 tap bandpass filter depending on the state of the SYNC input. See Operation Mode Control below for more detail.
RND2..0
22, 23, 24
I
Output Rounding Control. TTL inputs with internal pull-down. These pins set the position of the effective least significant bit of the output port by adding a rounding bit to the next lower internal bit and zeroing all outputs below the rounding bit. Additional rounding functions are added with the SO 1 control input. See Table 6.
SO15..0
4, 5, 6, 7, 8, 9, 10, 11, 14, 15, 16, 17, 18, 19, 20, 21
O
Output Data Port. TTL outputs (SO3..0 are bi-directional pins with an internal pull-down). The filtered result is available at this registered 16-bit output port, half LSB rounded as determined by the rounding control word RND 2..0. SO15 is the MSB. The SO3..0 control inputs enable additional formatting and rounding features as described below.
SO3..0
18, 19, 20, 21
I/O
Output Data Port. TTL bi-directional pins with internal pull-down. The SO0 control input enables the unsigned input and output format. The SO1 control input enables 8-bit rounding or CCIR 601 8-bit and 10-bit modes of operation. SO3..2 are reserved for future functions.
OE
3
I
Output Enable. Active low TTL input with internal pull-up. When this asynchronous input is high, the output data port is in the high impedance state.
VDD GND
13, 29, 38 12, 28, 39, 41
+5 V 5% power supply. Ground
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2
SO13 SO14
SO15
OE
TCO
DEC
INT
SYNC
CLK
GND
SI11
6 SO12 SO11 SO10 SO9 SO8 GND VDD 7
5
4
3
2
1
44
43
42
41
40 39 GND
8
38
VDD SI10 SI9 SI8 SI7 SI6 SI5 SI4 SI3 VDD
9
37
10
36
11
35
12
GF9102A TOP VIEW
34
13
33
SO7 SO6
14
32
15
31
SO5 SO4
16
30
17 18 19 20 21 22 23 24 25 26 27 28
29
SO3
SO2
SO1
SO0
RND2
RND1 RND0
SI0
SI1
SI2
GND
Fig. 1 GF9102A Pin Connections
LOWPASS FILTER CHARACTERISTICS at SAMPLING FREQUENCY OF 27MHz
PARAMETER Filter Order Pass Band Ripple Pass Band Edge DC Gain 6.75 MHz (s/4) Attenuation Minimum Stop Band Attenuation Stop Band Edge
VALUE 53 < 0.02 dB 5.75 MHz 0.00 dB 12.4 dB >58 dB 7.4 MHz
3
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0
2
4
6
8
10
12
14
0
1
2
3
4
5
6
0 -10 -20
-20 -10 CCIR601 CCIR601 GF9102 GF9102A
0
0.05 0.0375 0.025
MAGNITUDE (dB)
-30
dB
-30
MAGNITUDE (dB)
0.0125 0 -0.0125 -0.025 -0.0375 -0.05
CCIR601 CCIR601 GF9102 0
-40
-50 -50
-40
-60 -60
-70 -70
CCIR601 GF9102A 2 3 4 5 6
-80 -80
0
2
4
6
8
10
12
14
0
1
FREQUENCY (MHz)
FREQUENCY (MHz)
Fig. 2 Frequency Response of the Decimation/Interpolation Filter (Sampling at 27 MHz)
Fig. 3 Frequency Response of the Decimation/Interpolation Filter Passband (Sampling at 27 MHz)
0
110 100
0
6
MAGNITUDE (dB) 21 TAP BPF
-20
-15
80
% FULL SCALE
70 60 50 40 30 20 10 0 -10 0 10 20 30 40 50 60 70 80
-40
-36
-60
-58
-80
-79
21 TAP BPF 21 TAP BPF 9 TAP BPF 9 TAP BPF
-100 0 1 2
freq enc
-100 3
(MH )
4
5
6
7
SAMPLE NUMBER
FREQUENCY (MHz)
Fig. 4 Step Response of Decimation Filter
Fig. 5 Frequency Response of the Bandpass Filter (Sampling at 14.31818 MHz)
0 -1
6 5
0
0
6.02
MAGNITUDE (dB) 21 TAP BPF
MAGNITUDE (dB) 9 TAP BPF
MAGNITUDE (dB) 21 TAP BPF
-2 -3 -4 -5 -6 -7 -8 -9 -10 1.5 21 21 TAP BPF TAP BPF 9 TAP BPF 9 TAP BPF 2 2.5 3 3.5 4 4.5 5 5.5
4 3 2 1 0 -1 -2 -3 -4
-0.005
6.015
-0.01
6.01
-0.015 2121 TAP BPF TAP BPF 9 TAP BPF 9 TAP BPF -0.02 2.579545 3.079545
frequency (MHz)
6.005
3.579545
4.079545
4.579545
6.00
FREQUENCY (MHz)
FREQUENCY (MHz)
Fig. 6 Frequency Response of the Bandpass Filter Transition Band (Sampling at 14.31818 MHz)
Fig. 7 Frequency Response of the Bandpass Filter Passband (Sampling at 14.31818 MHz)
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4
MAGNITUDE (dB) 9 TAP BPF
MAGNITUDE (dB) 9 TAP BPF
90
Table 1: Input Data Format and Bit Weighting
Two's complement signed binary, data range: -1 SI < 1 SI 11 -20 SI 10 2-1 SI9 2-2 SI8 2-3 SI7 2-4 SI6 2-5 SI5 2-6 SI4 2-7 SI3 2-8 SI2 2-9 SI1 2-10 SI0 2-11
Unsigned binary, data range: 0 SI < 256 SI 11 27 SI 10 26 SI9 25 SI8 24 SI7 23 SI6 22 SI5 21 SI4 20 SI3 2-1 SI2 2-2 SI1 2-3 SI0 2-4
Table 2: Output Data Format and Bit Weighting
Two's complement signed binary, data range: -1 SO < 1 SO15 -20 SO 14 SO 13 2-1 2-2 SO12 SO11 2-3 2-4 SO 10 2-5 SO9 2-6 SO8 2-7 SO7 2-8 SO6 2-9 SO5 2 -10 SO4 2 -11 SO 3 2-12 SO2 2-13 SO1 2-14 SO0 2-15
Unsigned binary, data range: 0 SO < 256 SO 15 27 SO 14 26 SO13 25 SO12 SO11 24 23 SO 10 22 SO9 21 SO8 20 SO7 2-1 SO6 2-2 SO5 2-3 SO4 2-4 SO3 2-5 SO2 2-6 SO1 2-7 SO0 2-8
Table 3: Operation Mode Control
DEC 0 0 0 1 1 1 Notes: INT 0 0 1 0 0 1 Sync 0 1 Sync Sync Sync Sync Mode Bandpass1 Bandpass2 Decimating Interpolating Interpolating Pass through Description 21 Tap Bandpass 9 Tap Bandpass Gain=2 Gain=1 Gain=0.5 Gain=1 for unsigned input3 Top 12 bit pass through Device Latency 18 Clock Cycles 18 Clock Cycles 33 Clock Cycles 33 Clock Cycles 33 Clock Cycles 33 Clock Cycles Notes 2 2 1 1 2 2
1. This operating mode is compatible with TMC2242. 2. This is an enhanced operating mode of the GF9102A. 3. This mode is invoked using the SO0 pin. See I/O Format control below.
Table 4: I/O Format Control
RND2..0 RND = 000 RND 000 RND 000 SO03 Output TCO 0 1 0 0 1 1 0 1 Notes: 1. 2. 3. 4. Input5 Signed Signed Signed Signed Unsigned4 Unsigned Output5 I_Unsigned Signed I_Unsigned Signed Unsigned Signed 2 Limit output up to 15 bits 1 Notes 1
This operating mode is compatible with TMC2242. This is an enhanced operating mode of the GF9102A. SO 0, the LSB of the output is a bi-directional pad with a large pull-down resistor. This pin does not have to be connected. When this pin is not connected the GF9102A defaults to a mode compatible with the TMC2242. Application notes for the TMC2242 suggest grounding the MSB of the input if the input data is unsigned as in most A/D converters. This method limits the input to 11 bits and leads to potential output non-saturated type overflow since the MSB of the output is ignored.
5.
Signed: two's complement binary data. I_unsigned: invert all bits in signed data except for the MSB; also called inverted offset binary. Unsigned: invert MSB of signed data; also called offset binary.
5
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Table 5: Output Rounding Control
RND2..0 000 001 010 011 100 101 110 111 100 110 101
SO13 Output Output 0 0 0 0 0 0 1 1 1
No. of Output Bits 16 15 14 13 12 11 10 9 8 10 8
Description Rounding to 16 bit Rounding to 15 bit Rounding to 14 bit Rounding to 13 bit Rounding to 12 bit Rounding to 11 bit Rounding to 10 bit Rounding to 9 bit Rounding to 8 bit CCIR 601 10 bit data format4 CCIR 601 8 bit data format5
Notes 1 1 1 1 1 1 1 1 2 2 2
Notes:
1. 2. 3.
This operating mode is compatible with TMC2242. This is an enhanced operating mode of the GF9102A. SO1, the second LSB of the output is a bi-directional pad with a large pull-down resistor. This pin does not have to be connected. When this pin is not connected the GF9102A defaults to a mode compatible with the TMC2242.
4. . 5.
CCIR 601 10 bit data format range from Hex 004 to 3FB. CCIR 601 8 bit data format range from Hex 01 to FE.
Table 6: Extra Control Input Pins using the Four Least Significant Bi-directional Output Pads SO3..0
Conditions to allow Control Inputs RND 000 RND = 100 RND = 110 RND = 101 RND = 1XX RND = 1XX SO0 = 1 SO1 = 1 SO1 = 1 SO1 = 1 SO2 SO3 Unsigned input 8 bit output rounding CCIR 601 10 bit data format CCIR 601 8 bit data format Reserved Reserved 2 2 2 2 Output Pad1 Function Notes
Notes:
1. SO3..0 pins are bi-directional with a large pull-down resistor. These pins do not have to be connected. When these pins are not connected the GF9102A defaults to a mode compatible with the TMC2242. 2. This is an enhanced operating mode of the GF9102A.
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6
Table 7: Input Step Response
INPUT DECIMATION INT = 1, DEC = 0 XXX 400 400 * 55 cycles * * 400 400 000 * * * 000 000 000 000 000 000 * * * 000 NOTE: TCO = 1 XXX XX XX * * * 4000 4000 4000 * * * 44E2 44E2 2F6A 2F6A FC4C FC4C * * * 0000 SYNC 1 0 0 * * * 0 0 0 * * * 0 0 0 0 0 0 * * * 0 OUTPUT INTERPOLATION INT = 0, DEC = 1 XXX XX XX * * * 2000 2000 2000 * * * 244A 1F6A 1000 0096 FBB6 FF68 * * * 0000 SYNC 1 0 0 * * * 0 0 0 * * * 0 0 0 0 0 0 * * * 0 Steady State Minimum Ringing Maximum Ringing
7
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ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Range Operating Temperature Range Storage Temperature Range Lead Temperature (soldering, 10 sec) VALUE -0.3 to +7.0V 0.5 to (VDD + 0.5)V 0C TA 70C -65C TS 150C 260C CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
ELECTRICAL CHARACTERISTICS
Conditions: V DD = 5 V, T A = 0 to 70C, RL = 150 to GND and 144 AC coupled unless otherwise shown.
PARAMETER
Supply Voltage Supply Current Quiescent Supply Current Unloaded Input Voltage, Logic Low Input Voltage, Logic High Switching Threshold Input Current: (TTL Inputs) Inputs with Pulldown Resistors Inputs with Pullup Resistors Ouput Voltage, Logic Low Ouput Voltage, Logic High Hi-Z Output Leakage Current Short Circuit Output Current
SYMBOL
VDD IDDQ I DDU V IL V IH VT IIN TTL
CONDITIONS
MIN
4.75
TYP
5 5 60 1 1.5 1 115 -115 0.2 4.5 1 -
MAX
5.25 10 95 0.8 10 222 -214 0.4 10 210
UNITS
volts mA mA volts volts volts A A A volts volts A mA
VDD = Max, VIN = 0V VDD = Max, OE = VDD , = 20 MHz
-
2.0 -10 35 -35 2.4 -10 -
VIN = VDD OR VSS VIN = VDD VIN = VSS
VOL VOH I OZ I OS
VDD = Min, I OL = 6mA VDD = Min, I OH = -6mA VDD = Max, OE = 1 VDD = Max, output high one pin to ground, one second duration max
Input Capacitance Output Capacitance Ambient Temperature, Still Air
CIN COUT TA
TA = 25C, = 1MHz TA = 25C, = 1MHz
0
-
10 10 70
pF pF C
NOTE 1: Supply current may fluctuate with changes in data pattern.
VDD VDD
n SUBSTRATE n SUBSTRATE D1 p+ CONTROL INPUT n+ D2 n n p p D1 p+
n+ D2 p WELL GND GND
p WELL
Fig. 8a Equivalent Input Circuit
Fig. 8b Equivalent Output Circuit
521 - 26 - 02
8
SWITCHING CHARACTERISTICS, TA from 0C NAME
tD tOH tEN tDIS tCY tPWL tPWH tS tH
to 70C unless otherwise specified.
PARAMETER
Output delay Output hold Output enable Output disable Cycle time Clock pulse width low Clock pulse width high Input setup time Input hold time
TEST CONDITIONS
VDD=Min, CL=25 pF VDD=Max, CL=25 pF VDD=Min, CL=25 pF VDD=Min, CL=25 pF
MIN
3 25 10 10 6 0
TYP
-
MAX
15 15 15 -
UNITS
ns ns ns ns ns ns ns ns ns
0
1
2
3
4
5
6
CLK tPWH tPWL tCY
SI11..0 tS
1 tH
2
3
4
5
6
SYNC 34 35 36 37 38 39 40
CLK tD 1 3 tOH
SO15..0
5
7
7
tDIS
tEN
OE
Fig. 9 Timing Diagram - Decimation INT = 1, DEC = 0, SYNC = SYNC
9
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0
1
2
3
4
5
6
CLK tPWH tPWL
1 SI11..0 tS tH
3
5
SYNC 34 35 36 37 38 39
CLK tD 1 2 tOH 3 4 5 tDIS 6
SO15..0
tEN
OE
Fig. 10 Timing Diagram - Interpolation INT = 0, DEC = 1, SYNC = SYNC
0
1
2
3
4
5
6
CLK tS tH tPWH tPWL tCY
SI11..0
1
2
3
4
5
6
19
20
21
22
23
24
25
CLK tD 1 2 3 4 tOH
SO15..0
5
6
7
7
tDIS
tEN
OE
Fig. 11 Timing Diagram - Decimation INT = 0, DEC = 0, SYNC = 0 or SYNC = 1
521 - 26 - 02
10
0
1
2
3
4
5
6
CLK tPWH tPWL tCY
SI11..0 tS
1 tH
2
3
4
5
6
SYNC 34 35 36 37 38 39 40
CLK tD 1 2 3 4 tOH
SO15..0
5
6
7
7
tDIS
tEN
OE
Fig. 12 Timing Diagram - Decimation INT = 1, DEC = 1, SYNC = SYNC
tEN OE tDIS 0.5V
THREE STATE OUTPUTS 0.5V
HIGH IMPEDANCE
2.0V 0.8V
Fig. 13 Threshold Levels for Three State Measurement
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. (c) Copyright January 1995 Gennum Corporation. All rights reserved. Printed in Canada.
11
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