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| ICS2059-02 Clock Multiplier and Jitter Attenuator Description The ICS2059-02 is a VCXO (Voltage Controlled Crystal Oscillator) based clock multiplier and jitter attenuator designed for system clock distribution applications. This monolithic IC, combined with an external inexpensive quartz crystal, can be used to replace a more costly hybrid VCXO retiming module. A dual input mux is also provided. By controlling the VCXO frequency within a phase-locked loop (PLL), the output clock is phase and frequency locked to the input clock. Through selection of external loop filter components, the PLL loop bandwidth and damping factor can be tailored to meet system clock requirements. A loop bandwidth down to the Hz range is possible. Features * Excellent jitter attenuation for telecom and video clocks * 2:1 Input MUX for input reference clocks * No switching glitches on output * VCXO-based clock generation offers very low jitter and phase noise generation * Output clock is phase and frequency locked to the selected input reference clock * Fixed input to output phase relationship * +115 ppm minimum crystal frequency pullability range, using recommended crystal * * * * Industrial temperature range Low power CMOS technology 16-pin TSSOP package Single 3.3 V power supply Block Diagram Pullable Crystal VDD VDD 3 ISET Input Clock ICLK2 Input Clock ICLK1 ISEL X1 X2 1 0 Phase Detector Charge Pump VCXO Selectable Divider CLK SEL1:0 2 CHGP VIN GND 2 MDS 2059-02 C 1 Revision 031605 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com ICS2059-02 Clock Multiplier and Jitter Attenuator Pin Assignment X1 VDD VDD VDD VIN GND GND CHGP 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X2 ISEL ICLK1 ICLK2 SEL0 CLK SEL1 ISET Output Frequency Select Table Input 8 kHz 8 kHz 15.625 kHz 15.734265 kHz 151.875 kHz 27 MHz SEL1 SEL0 0 0 1 1 M M 0 1 0 1 0 1 N 1296 2430 1728 1716 128 1 Output Clock Crystal Used (MHz) (MHz) 10.368 20.736 19.44 19.44 27 27 27 27 19.44 19.44 27 27 16- pin ( 173 mil) TSSOP Note: For SEL input pin programming: 0 = GND, 1 = VDD, M = Floating Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin Name X1 VDD VDD VDD VIN GND GND CHGP ISET SEL1 CLK SEL0 ICLK2 ICLK1 ISEL Pin Type -- Power Power Power Input Power Power Output -- Input Output Input Input Input Input Pin Description Crystal Input. Connect this pin to the specified crystal. Power Supply. Connect to +3.3 V. Power Supply. Connect to +3.3 V. Power Supply. Connect to +3.3 V. VCXO Control Voltage Input. Connect this pin to CHGP pin and the external loop filter as shown in this data sheet. Connect to ground. Connect to ground. Charge Pump Output. Connect this pin to the external loop filter and to pin VIN. Charge pump current setting node, connection for setting resistor. Output Frequency Selection Pin 1. Determines output frequency as per table above. Includes mid-level input. Clock Output. Output Frequency Selection Pin 0. Determines output frequency as per table above. Internal pull-up resistor. Input Clock Connection 2. Connect an input reference clock to this pin. If unused, connect to ground. Input Clock Connection 1. Connect an input reference clock to this pin. If unused, connect to ground. Input Selection. Used to select which reference input clock is active. Low input level selects ICLK1, high input level selects ICLK2. Internal pull-up resistor. Crystal Output. Connect this pin to the specified crystal. 16 X2 -- MDS 2059-02 C 2 Revision 031605 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com ICS2059-02 Clock Multiplier and Jitter Attenuator Functional Description The ICS2059-02 is a clock generator IC that generates an output clock directly from an internal VCXO circuit which works in conjunction with an external quartz crystal. The VCXO is controlled by an internal PLL (Phase-Locked Loop) circuit, enabling the device to perform clock regeneration from an input reference clock. The ICS2059-02 is configured to provide an output clock that is the same frequency as the input clock. There are 12 selectable input / output frequency ranges, each of which is a submultiple of the supported quartz crystal frequency range. Please refer to the Output Clock Selection Table on Page 2. Most typical PLL clock devices use an internal VCO (Voltage Controlled Oscillator) for output clock generation. By using a VCXO with an external crystal, the ICS2059-02 is able to generate a low jitter, low phase-noise output clock within a low bandwidth PLL. This serves to provide input clock jitter attenuation and enables stable operation with a low-frequency reference clock. The VCXO circuit requires an external pullable crystal for operation. External loop filter components enable a PLL configuration with low loop bandwidth. output clock will change to reflect the phase of the newly selected input at a controlled phase slope (rate of phase change) as influenced by the PLL loop characteristics. Quartz Crystal It is important that the correct type of quartz crystal is used with the ICS2059-02. Failure to do so may result in reduced frequency pullability range, inability of the loop to lock, or excessive output phase jitter. The ICS2059-02 operates by phase-locking the VCXO circuit to the input signal of the selected ICLK input. The VCXO consists of the external crystal and the integrated VCXO oscillator circuit. To achieve the best performance and reliability, a crystal device with the recommended parameters (shown below) must be used, and the layout guidelines discussed in the PCB Layout Recommendations section must be followed. The frequency of oscillation of a quartz crystal is determined by its cut and by the external load capacitance. The ICS2059-02 incorporates variable load capacitors on-chip which "pull", or change, the frequency of the crystal. The crystals specified for use with the ICS2059-02 are designed to have zero frequency error when the total of on-chip + stray capacitance is 14 pF. To achieve this, the layout should use short traces between the ICS2059-02 and the crystal. A complete description of the recommended crystal parameters is in application note MAN05. A list of approved crystals is located on the ICST web site (www.icst.com). Application Information Input / Output Frequency Configuration The ICS2059-02 is configured to generate an output frequency that is equal to the input reference frequency. Clock frequencies that are supported are those which fall into the ranges listed in the Output Clock Selection Table on Page 2. Input bits SEL2:0 are set according to this table, as is the external crystal frequency. Other input/output frequency combinations can be used if the necessary integer multiplication factor "N" appears in the Output Frequency Select table. fro example, 20 MHz can be generated from 156.25 kHz by using select M0, as N=128. PLL Loop Filter Components All analog PLL circuits use a loop filter to establish operating stability. The ICS2059-02 uses external loop filter components for the following reasons: 1) Larger loop filter capacitor values can be used, allowing a lower loop bandwidth. This enables the use of lower input clock reference frequencies and also input clock jitter attenuation capabilities. Larger loop filter capacitors also allow higher loop damping factors when less passband peaking is desired. 2) The loop filter values can be user selected to optimize loop response characteristics for a given application. Input Mux The Input Mux serves to select between two alternate input reference clocks. Upon reselection of the input clock, clock glitches on the output clock will not be generated due to the "fly-wheel" effect of the VCXO (the quartz crystal is a high-Q tuned circuit). When the input clocks are not phase aligned, the phase of the MDS 2059-02 C 3 Revision 031605 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com ICS2059-02 Clock Multiplier and Jitter Attenuator Referencing the External Component Schematic on this page, the external loop filter is made up of the components RZ, C1 and C2. RSET establishes PLL charge pump current and therefore influences loop filter characteristics. Design aid tools for configuring the loop filter can be found at www.icst.com, including on-line and PC-based calculators. External Component Schematic CL (Refer to Crystal Tuning section) CL Crystal X1 VDD VDD VDD VIN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X2 ISEL ICLK1 ICLK2 SEL0 CLK SEL1 ISET P RS CS GND GND CHGP 16-pin (173 mil) TSSOP R SET Recommended Loop Filter Values Vs. Output Frequency Range Selection Crystal SEL1 SEL0 Multiplier RSET RS CS 0.47 F 0.68 F 0.68 F 0.68 F 1 F 1 F CP Loop Bandwidth (-3dB point) Damping Factor 3.00 2.97 3.17 3.18 3.16 3.08 0 0 1 1 M M 0 1 0 1 0 1 (N) 2592 2430 1728 1716 128 1 180 k 120 k 330 k 330 k 120 k 1 M 820 k 560 k 680 k 680 k 330 k 22 k 1.8 nF 3.3 nF 3.9 nF 3.9 nF 3.3 nF 3.3 nF 11.2 Hz 11.8 Hz 11.5 Hz 11.5 Hz 14.5 Hz 204.2 Hz Note: For SEL input pin programming: 0 = GND, 1 = VDD, M = Floating MDS 2059-02 C 4 Revision 031605 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com ICS2059-02 Clock Multiplier and Jitter Attenuator A "normalized" PLL loop bandwidth may be calculated as follows: 575 R S x I CP x345 NBW = --------------------------------------N The "normalized" bandwidth equation above does not take into account the effects of damping factor or the second pole. However, it does provide a useful approximation of filter performance. The loop damping factor is calculated as follows: 375 x I CP x C S 625 Damping Factor = R S x ---------------------------------------N Where: RS = Value of resistor in loop filter (Ohms) ICP = Charge pump current (amps) (refer to Charge Pump Current Table, below) N = Crystal multiplier shown in the above table CS = Value of capacitor C1 in loop filter (Farads) As a general rule, the following relationship should be maintained between components C1 and C2 in the loop filter: CP Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20. (The optional series termination resistor is not shown in the External Component Schematic.) Decoupling Capacitors As with any high-performance mixed-signal IC, the ICS2059-02 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01F must be connected between each VDD and the PCB ground plane. To further guard against interfering system supply noise, the ICS2059-02 should use one common connection to the PCB power plane as shown in the diagram on the next page. The ferrite bead and bulk capacitor help reduce lower frequency noise in the supply that can lead to output clock phase modulation. Recommended Power Supply Connection for Optimal Device Performance V D D P in C onnection to 3.3V P ow er P lane Ferrite Bead V D D P in = ----20 CS B ulk D ecoupling C apacitor (such as 1 F Tantalum ) V D D P in Charge Pump Current Table 0.01 F D ecoupling C apacitors RSET 1.4 M 680 k 540 k 120 k Charge Pump Current (ICP) 10 A 20 A 25 A 100 A Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground, shown as CL in the External Component Schematic. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. Special considerations must be made in choosing loop components CS and CP. These recommendations can be found in the design aid tools section of www.icst.com. MDS 2059-02 C 5 Revision 031605 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com ICS2059-02 Clock Multiplier and Jitter Attenuator In most cases the load capacitors will not be required. They should not be stuffed on the prototype evaluation board as the indiscriminate use of these trim capacitors will typically cause more crystal centering error than their absence. If the need for the load capacitors is later determined, the values will fall within the 1-4 pf range. The need for, and value of, these trim capacitors can only be determined at prototype evaluation. Please refer to MAN05 for the procedure to determine the component values. The ICS Applications Note MAN05 may also be referenced for additional suggestions on layout of the crystal section. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Please also refer to the Recommended PCB Layout drawing on page 7. 1) Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) The loop filter components must also be placed close to the CHGP and VIN pins. CP should be closest to the device. Coupling of noise from other system signal traces should be minimized by keeping traces short and away from active signal traces. Use of vias should be avoided. 3) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 4) To minimize EMI, the 33 series termination resistor (if needed) should be placed close to the clock output. 5) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the ICS2059-02. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. MDS 2059-02 C 6 Revision 031605 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com ICS2059-02 Clock Multiplier and Jitter Attenuator Recommended PCB Layout For minimum output clock jitter, device VDD connections should be made to common bulk decoupling device (see text). G For minimum output clock jitter, remove ground and power plane within this entire area. Also route all other traces away from this area. G G G 1 2 3 4 5 6 7 8 G G G 16 15 14 13 12 11 10 9 G Legend: G = Ground Connection Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS2059-02. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 7V Rating -0.5 V to VDD+0.5 V -40 to +85C -65 to +150C 125C 260C MDS 2059-02 C 7 Revision 031605 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com ICS2059-02 Clock Multiplier and Jitter Attenuator Recommended Operation Conditions Parameter Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Min. -40 +3.15 Typ. +3.3 Max. +85 +3.45 Units C V DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85C Parameter Operating Voltage Supply Current Input High Voltage, SEL1 Input Low Voltage, SEL1 Input High Voltage, ISEL, SEL0 Input Low Voltage, ISEL, SEL0 Input High Voltage, ICLK1, 2 Input Low Voltage, ICLK1, 2 Input High Current Input Low Current Input Capacitance, except X1 Output High Voltage (CMOS Level) Output High Voltage Output Low Voltage Short Circuit Current VIN, VCXO Control Voltage Nominal Output Impedance Symbol VDD IDD VIH VIL VIH VIL VIH VIL IIH IIL CIN VOH VOH VOL IOS VXC ZOUT Conditions Clock outputs unloaded, VDD = 3.3 V Min. 3.15 Typ. 3.3 10 Max. 3.45 15 Units V mA V VDD-0.5 0.5 2 0.8 VDD/2+1 VDD/2-1 V V V V V A A pF V V VIH = VDD VIL = 0 IOH = -4 mA IOH = -8 mA IOL = 8 mA -10 -10 7 VDD-0.4 2.4 +10 +10 0.4 50 0 20 VDD V mA V MDS 2059-02 C 8 Revision 031605 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com ICS2059-02 Clock Multiplier and Jitter Attenuator AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85 C Parameter VCXO Crystal Pull Range VCXO Crystal Nominal Frequency Input Jitter Tolerance Input pulse width (1) Output Frequency Error Output Duty Cycle (% high time) Output Rise Time Output Fall Time Skew, Input to Output Clock Cycle Jitter (short term jitter) Timing Jitter, Filtered 500 Hz-1.3 MHz (OC-3) Timing Jitter, Filtered 65 kHz-1.3 MHz (OC-3) Symbol fXP fX tji tpi FOUT tOD tOR tOF tIO tja tjf tjf Conditions Using recommended crystal Min. -115 8.5 Typ. Max. Units +115 27 0.4 ppm MHz UI ns 0 0 60 1.5 1.5 ppm % ns ns ns ps p-p ps p-p ps p-p 10 ICLK = 0 ppm error Measured at VDD/2, CL=15 pF 0.8 to 2.0V , CL=15 pF 2.0 to 0.8 V, CL=15 pF 27 MHz output, rising edges, CL=15 pF -5 150 210 150 0 40 +5 Note 1: Minimum high or low time of input clock. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Symbol JA JA JA JC Conditions Still air 1 m/s air flow 3 m/s air flow Min. Typ. 78 70 68 37 Max. Units C/W C/W C/W C/W Thermal Resistance Junction to Case MDS 2059-02 C 9 Revision 031605 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com ICS2059-02 Clock Multiplier and Jitter Attenuator Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 16 Millimeters Symbol Min Max Inches Min Max E1 IN D EX AR EA E 1 2 D A A1 A2 b C D E E1 e L aaa -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10 -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004 A 2 A 1 A c -Ce b S E A TIN G P LA N E L aaa C Ordering Information Part / Order Number ICS2059GI-02 ICS2059GI-02T Marking 2059GI02 2059GI02 Shipping Packaging Tubes Tape and Reel Package 16-pin TSSOP 16-pin TSSOP Temperature -40 to +85 C -40 to +85 C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. MDS 2059-02 C 10 Revision 031605 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com ICS2059-02 Clock Multiplier and Jitter Attenuator Revision History Rev. A B C Originator P.Griffith P.Griffith P.Griffith Date 11/19/04 11/29/04 03/16/05 Description of Change New device/datasheet. Change proposal number from 4MPG019 to ICS2059-02. Move from Advance to Preliminary. Updated values for "Loop Bandwidth" and" Damping Factor" in "Recommended Loop Filter Values vs Output Frequency Range Selection" table; Released to Final and standard, general purpose device. MDS 2059-02 C 11 Revision 031605 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com |
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