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LH5332600
FEATURES * 4,194,304 x 8 bit organization (Byte mode: BYTE = VIL) 2,097,152 x 16 bit organization (Word mode: BYTE = VIH) * Access time: 100 ns (MAX.) * Supply current: - Operating: 100 mA (MAX.) - Standby: 100 A (MAX.) * TTL compatible I/O * Three-state output * Single +5 V power supply * Static operation * Packages: 44-pin, 600-mil SOP 48-pin, 12 mm x 18 mm2 TSOP (Type I) * Others: - Non programmable - Not designed or rated as radiation hardened - CMOS process (P type silicon substrate) DESCRIPTION
The LH5332600 is a 32M-bit mask-programmable ROM organized as 4,194,304 x 8 bits (Byte mode) or 2,097,152 x 16 bits (Word mode) that can be selected by a BYTE input pin. It is fabricated using silicon-gate CMOS process technology.
CMOS 32M (4M x 8/2M x 16) MROM
PIN CONNECTIONS
44-PIN SOP TOP VIEW
NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE D0 D8 D1 D9 D2 D10 D3 D11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A20 A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE GND D15/A-1 (NOTE) D7 D14 D6 D13 D5 D12 D4 VCC
NOTE: The D15/A-1 pin becomes LSB address input (A-1) when the BYTE pin is set to be LOW in byte mode and data output (D15) when set to be HIGH in word mode.
5332600N-1
Figure 1. SOP Pin Connections
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LH5332600
CMOS 32M (4M x 8/2M x 16) MROM
48-PIN TSOP (Type I)
TOP VIEW
BYTE A16 A15 A14 A13 A12 A11 A10 A9 A8 A19 GND A20 A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
GND GND D15/A-1 (NOTE) D7 D14 D6 D13 D5 D12 D4 VCC VCC GND D11 D3 D10 D2 D9 D1 D8 D0 OE GND GND
NOTE: The D15/A-1 pin becomes LSB address input (A-1) when the BYTE pin is set to be LOW in byte mode and data output (D15) when set to be HIGH in word mode.
5332600T-1
Figure 2. TSOP Pin Connections
2
CMOS 32M (4M x 8/2M x 16) MROM
LH5332600
A20 44 A19 43 A18 2 A17 3 A16 34 A15 35
ADDRESS DECODER
ADDRESS BUFFER
DATA SELECTOR/OUTPUT BUFFER
A14 36 A13 37 A12 38 A11 39 A10 40 A9 41 A8 42 A7 4 A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11
MEMORY MATRIX (4,194,304 x 8) (2,097,152 x 16)
31 D15 29 D14 27 D13 25 D12 22 D11 20 D10 18 D9 16 D8 30 D7 28 D6 26 D5 24 D4 21 D3 19 D2 17 D1 15 D0
COLUMN SELECTOR
CE 12
CE BUFFER
TIMING GENERATOR
SENSE AMPLIFIER
OE 14
OE BUFFER
BYTE 33
BYTE/WORD SWITCHOVER CIRCUIT
ADDRESS BUFFER
31 A-1
23 VCC
13 32 GND
5332600N-2
Figure 3. LH5332600 Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME SIGNAL PIN NAME
A-1 - A20 D0 - D15 BYTE CE
Address input Data output x8bit / x16 bit (byte/word) mode select input Chip enable input
OE VCC GND NC
Output enable input Power supply Ground No connection (Non wire bonding)
3
LH5332600
CMOS 32M (4M x 8/2M x 16) MROM
TRUTH TABLE
CE OE BYTE A-1 (D15) DATA OUTPUT D0 - D7 D8 - D15 ADDRESS INPUT LSB MSB SUPPLY CURRENT
H L L L L
X H L L L
X X H L L
X X L H
High-Z High-Z D 0 - D7 D0 - D7 D8 - D15
High-Z High-Z D8 - D15 High-Z High-Z
A0 A-1 A-1
A20 A20 A20
Standby (ISB) Operating Operating Operating Operating
NOTES: X = Don't care; High-Z = High-impedance
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Supply voltage Input voltage Output voltage Operating temperature Storage temperature
VCC VIN VOUT TOPR TSTG
-0.3 to +7.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 0 to +70 -65 to +150
V V V C C
RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply voltage
VCC
4.5
5.0
5.5
V
DC ELECTRICAL CHARACTERISTICS (VCC = 5 V 10%, TA = 0 to +70C)
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
Input `High' voltage Input `Low' voltage Output `High' voltage Output `Low' voltage Input leakage current Output leakage current Operating current
V IH VIL VOH VOL | ILI | | ILO | ICC1 ICC2
I OH = -400 A I OL = 2.0 mA V IN = 0 V to VCC V OUT = 0 V to VCC t RC = 100 ns t RC = 1 s CE = VIH CE = VCC - 0.2 V f = 1 MHz, t A = 25C
2.2 -0.3 2.4
VCC + 0.3 0.8 0.4 10 10 100 90 2 100 10 10
V V V V A A mA mA A pF pF
1 2
Standby current Input capacitance Output capacitance
ISB1 ISB2 CIN COUT
NOTES: 1. CE = VIH, OE = VIH 2. VIN = VIH or VIL, CE = VIL, output is open
4
CMOS 32M (4M x 8/2M x 16) MROM
LH5332600
AC ELECTICAL CHARACTERISTICS (VCC = 5 V 10%, TA = 0 to +70C)
PARAMETER SYMBOL MIN. MAX. UNIT NOTE
Read cycle time Address access time Chip enable access time Output enable delay time Output hold time
tRC tAA tACE tOE tOH tCHZ tOHZ
100 5
100 100 50 40 40
ns ns ns ns ns ns
1
Output floating time
ns
NOTE: 1. Determined by the time for the output to be opened. (Irrespective of output voltage)
AC TEST CONDITIONS
PARAMETER RATING
Input voltage amplitude Input rise/fall time Input signal fall time Input reference level Output reference level Output load condition
0.4 V to 2.6 V 10 ns 10 ns 1.5 V 1.5 V 1TTL + 100 pF
CAUTION
It is recommended that a decoupling capacitor be connected between VCC and GND-Pin.
5
LH5332600
CMOS 32M (4M x 8/2M x 16) MROM
tRC
A-1 - A20 tAA (NOTE) CE tACE (NOTE) OE tOE (NOTE) tOLZ tOHZ tOH tCHZ
D0 - D7 NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded.
DATA VALID
5332600N-3
Figure 4. Byte Mode (BYTE = VIL)
tRC
A-1 - A20 tAA (NOTE) CE tACE (NOTE) OE tOE (NOTE) tOHZ tOH tCHZ
(D0 - D15) NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded.
DATA VALID
5332600N-4
Figure 5. Word Mode (BYTE = VIH)
6
CMOS 32M (4M x 8/2M x 16) MROM
LH5332600
PACKAGE DIAGRAM
44SOP (SOP044-P-0600)
1.27 [0.050] TYP.
0.50 [0.020] 0.30 [0.012]
44
23
13.40 [0.528] 13.00 [0.512]
16.40 [0.646] 15.60 [0.614]
14.40 [0.567]
1 28.40 [1.118] 28.00 [1.102]
22
SEE DETAIL 0.20 [0.008] 0.10 [0.004] 2.9 [0.114] 2.5 [0.098]
DETAIL
0.15 [0.006] 1.275 [0.050] 2.9 [0.114] 2.5 [0.098] 0.25 [0.010] 0.05 [0.002] 1.275 [0.050] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 3.25 [0.128] 2.45 [0.096] 0.25 [0.010] 0.05 [0.002]
1.275 [0.050]
0 - 10 0.80 [0.031]
44SOP
48TSOP (TSOP048-P-1218)
0.50 [0.020] TYP. 48 0.30 [0.012] 0.10 [0.004] 25
16.60 [0.654] 16.20 [0.638]
18.40 [0.724] 17.60 [0.693]
17.00 [0.669]
1 12.20 [0.480] 11.80 [0.465]
24 0.20 [0.008] 0.10 [0.004] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] 0.20 [0.008] 0.00 [0.000]
0.15 [0.006] 0.425 [0.017]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT MINIMUM LIMIT
48TSOP
7
LH5332600
CMOS 32M (4M x 8/2M x 16) MROM
ORDERING INFORMATION
LH5332600 Device Type X Package
N 44-pin, 600-mil SOP (SOP044-P-0600) T 48-pin, 12 mm x 18 mm2 TSOP (Type I) (TSOP048-P-1218) CMOS 32M (4M x 8 or 2M x 16) Mask-Programmable ROM
Example: LH5332600N (CMOS 32M (4M x 8 or 2M x 16) Mask-Programmable ROM, 44-pin, 600-mil SOP)
5332600N-5
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