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INDEX PRELIMINARY
MX8350
2 in 1 RAMBUS CLOCK GENERATOR
FEATURES
* Clock generator for RambusTM Channel * Provide output frequency select pin * Provide a RambusTM interface level output frequency which is 17 times of input frequency * Provide a TTL interface level output frequency which is one fourth of input frequency * Provide a TTL interface level output frequency which is 14/5 or 17/5 times of input frequency * Provide a chip reset pin (RESET) for external control * 3.3 V power supply * Package 14-pin SOP
GENERAL DESCRIPTION
The product is a clock synthesizer chip for RambusTM channel. It uses advanced phase lock loop technology to generate three desired clock. The reference clocks are supplied by two external crystals. (X'tal1 and X'tal2) The X'tal1 frequency is 14.31818MHz in NTSC case, 17.734475MHz in PAL case and 14.302446MHz in MPAL case. With X'tal1 input frequency, the TTL-interface-level output clock set (VCLK and FSC) is (48.681812MHz, 3.579545MHz), (49.65653MHz, 4.433619MHz) and (48.628318MHz, 3.5756115MHz) in the three cases respectively. The RambusTM-interface-level clock (RCLK) is 250MHz which is 17 times of the X'tal2 frequency. i.e.14.705882MHz. The product is 3.3 V operation, and the package type is 14-pin SOP.
PIN CONFIGURATIONS
14-PIN SOP
FSC GND VCLK VDD OSC2 IN OSC2 OUT NTSC/PAL 1 2 14 13 RESET OSC1 IN OSC1 OUT GND TEST VDD RCLK
3 4 5 6 7
MX8350
12 11 10 9 8
Rambus and
are trademarks of Rambus Inc.
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MX8350
PIN DESCRIPTION
SYMBOL FSC GND VCLK VDD OSC2 IN OSC2 OUT NTSC/PAL PIN TYPE O O I O I PIN NUMBER 1 2 3 4 5 6 7 DESCRIPTION Clock output. 1/4 of OSC1 frequency. Circuit ground Video data transfer clock output. +3.3V power supply. OSC2 (14.705882MHz) crystal pin. OSC2 (14.705882MHz) crystal pin. OSC1 frequency select pin. High; VCLK=17/5 times of input frequency. Low; VCLK=14/5 times of input frequency. Rambus clock output. +3.3V power supply. OSC2 test pin. 1/4 of OSC2 frequency. Circuit ground. OSC1 crystal pin. OSC1 (NTSC; 14.31818MHz, PAL; 17.734475MHz, MPAL; 14.302446MHz) crystal pin. System reset input. Reset the chip when any transition edge is tetected.
RCLK VDD TEST GND OSC1 OUT OSC1 IN RESET
O O O I I
8 9 10 11 12 13 14
BLOCK DIAGRAM
NTSC/PAL
Feedback Divider
OSC1 IN X'tal1 OSC1 OUT
OSC
PFC
Charge Pump
VCO
O5
VCLK
Loop Filter POR RESET
Delay
O4 RESET
FSC
Feedback Divider
OSC2 IN X'tal2 OSC2 OUT
OSC
PFC
Charge Pump
VCO
RCLK
Loop Filter
O4
TEST
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MX8350
FUNCTIONAL DESCRIPTION
The Rambus clock generator is an integrated circuit of phase locked loop frequency synthesizer. It provides three clock output frequencies. The first clock output (FSC) is the crystal 1 frequency divided by 4 clock. The second clock output frequency (VCLK) is 14/5 or 17/5 times of crystal1 frequency. It can be selected by NTSC/ PAL pin. When NTSC/PAL pin is high, VCLK is 17/5 times of crystal 1 frequency. When NTSC/PAL pin is low, VCLK is 14/5 times of crystal 1 frequency. FSC and VCLK are TTL-interface-level outputs. The third clock output (RCLK) which is 17 times of crystal2 frequency is Rambus-interface-level signal. As shown in the block diagram, two phase locked loops which consist of feedback divider, phase frequency comparator (PFC), charge pump, voltage controlled oscillator (VCO) and loop filter are used. All components for PLL are integrated inside the chip.
FREQUENCY TABLE( in MHz)
NTSC PAL MPAL CRYSTAL 1 14.31818 17.734475 14.302446 NTSC/PAL H L H VCLK 48.681812 49.65653 48.628318 FSC 3.579545 4.433619 3.575612
CRYSTAL2 14.705882
RCLK 250
ABSOLUTE MAXIMUM RATINGS
RATING Storage Temperature Applied Input Voltage Applied Output Voltage Supply Voltage Operating Temperature Power Dissipation VALUE -55oC to 150oC -0.5V to VDD + 0.5V -0.5V to VDD + 0.5V -0.5V to 5V 0 to 70oC 0.5Watts
NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. NOTICE: Specifications contained within the following tables are subject to change.
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MX8350
DC CHARACTERISTICS TA = 0oC to 70oC, VDD = 3.15V to 3.6V
SYMBOL VIL VIH IIL IIH IVDD VOL VOH CI RL VLT IOH IOL Ro Ro (PMOS) Ro (NMOS) PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current VDD Current Output Low Voltage Output High Voltage Input Capacitance Line Impedence Line Termination Voltage Output High Current Output Low Current Output Resistance Output Resistance Output Resistance MIN. 2.4 -5 5 TBD 0.4 2.4 20 2.2 -10 40 5.3 50 10 75 2.7 10 75 10 TYP. MAX. 0.8 UNIT V V uA uA mA V V pF Ohm V uA mA Ohm Ohm Ohm CONDITIONS
IOL=8mA, VCLK output IOH=-4mA, VCLK output Rambus Level Rambus Level RCLK output VOL=0.4V, RCLK output RCLK output IOH=-600uA, FSC output IOL=600uA, FSC output
50 8 TBD TBD
AC CHARACTERISTICS TA = 0oC to 80oC, VDD = 3.15V to 3.6V
SYMBOL Dt1 Dt2 J Tr/Tf Tr/Tf Tup PARAMETER Duty Cycle Duty Cycle Jitter,short term Rise/Fall Time Rise/Fall Time Power up Time MIN. 45 55 TYP. MAX. 55 65 150 0.7 3.5 1 5 5 UNIT % % ps ns ns ms CONDITIONS RCLK, FSC *Note 1 VCLK *Note 2 *Note 1 Rambus level, RCLK output *Note 1 VCLK output, 30pF load *Note 2 1. After power is stable 2.Frequency from 0 to 250MHz *Note3
60
0.3 2
*Note 1: We measured FSC output with 20pF load to GND. Considering with probe loading, the total loading on FSC is 28pF. The test fixture to measure RCLK output is shown as Fig. 1. The measured duty cycle, jitter and Rise/Fall time are based on the test fixture. The reference voltage as measureing duty cycle is 50%. Short tern jitter means jitter measured at 11th rising edge after trigger point. Rise/Fall time is measured from 20% to 80%. *Note 2: VCLK output is measured with 22pF external capacitance loading. Considering with probe loading, the total loading on VCLK is 30pF. The reference voltage to measure duty cycle of VCLK is VDD/2. Rise/Fall time is measured from 20% to 80%. *Note 3: It's guaranteed by design.
P/N:PM0519
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MX8350
APPENDIX
VDD (3.3V)
VEE (5.0V) Instrument
RX=100 ohm RS=56 ohm FSO out
RT=51 ohm 50 Ohm Cable SMA jack Rscope (50 Ohm) *Note 4 GND
Measure point
*Note 4: Rscope is the internal equivalent resistance of instrument.
Fig. 1
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MX8350
ORDERING INFORMATION
PART NO. MX8350 PACKAGE 14-PIN SOP
PACKAGE INFORMATION
14-PIN PLASTIC SOP (150 mil)
ITEM A B C D E F G H I J K L
MILLIMETER 8.66 MAX. .53 [REF] 1.27 [TP] .41 [TYP.] .10 MIN. 1.73 MAX. 1.45 .13 5.99 .25 3.91 .13 1.04 .20 [TYP.] .67
INCHES .341 MAX. .021 [REF] .050 [TP] .016 [TYP.] .004 MIN. .068 MAX. .057 .005 .236 .010 .154 .005 .041 .008 [TYP.] .026
14
8
1 A
7
H I J
G
F K E
NOTE:Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition.
D
C
B
L
REVISION HISTORY
Revision 1.1 Description P 4: Add Note 1-3 P 5: Add Apendix Date JUL. 23, 1998
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MX8350
MACRONIX INTERNATIONAL CO., LTD.
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TEL:+886-3-578-8888 FAX:+886-3-578-8887
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http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
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