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ANALOG DEVICES Preliminary Technical Data
March 19, 2004
JPEG2000 VIDEO CODEC ADV202*
*Previously referred to as ADV-JP2001
1. FEATURES
* * Complete single-chip JPEG2000 compression/ decompression solution for video and still images. Patented SURFTM (Spatial Ultra-efficient Recursive Filtering) technology enables low power and low cost wavelet based compression. Supports both 9/7 and 5/3 wavelet transforms with up to 6 levels of transform. Programmable tile/image size with widths up to 2048 pixels in three-component 4:2:2 interleaved mode, and up to 4096 pixels in single-component mode. Maximum tile/image height is 4096 pixels. Video interface directly supporting ITU.R-BT656, SMPTE125M PAL/ NTSC, SMPTE274M, SMPTE293M [525p], ITU.R-BT1358[625p] or any video format with a max. input rate of 65 Msamples/ sec for irreversible mode or 40Msamples/sec for reversible mode. Two or more ADV202s can be combined to support full frame SMPTE274M HDTV [1080i] or SMPTE296M [720p]. Interlace temporally coherent frame based SD video sources for improved performance. Flexible asynchronous SRAM style host interface allows glue-less connection to most 16/32-bit microcontrollers and ASICs. 2.5-3.3v I/O and 1.5v core supply. 12mm x 12mm 121-ball fpBGA, speed grade 115MHZ or 13mmx13mm 144 fpBGA, speed grade 150MHz.
2. APPLICATIONS
* * * * * * * * Networked video and image distribution systems Wireless video and image distribution Image archival/retrieval Digital CCTV and surveillance systems Digital Cinema Systems Professional Video editing and recording Digital Still Cameras Digital Camcorders
* *
3. GENERAL DESCRIPTION
The ADV202 is a single-chip JPEG2000 CODEC targeted at video and high bandwidth image compression applications that will benefit by the enhanced quality and feature set provided by the JPEG2000 (J2K) ISO/IEC15444-1 image compression standard. It implements the computationally intensive operations of the JPEG2000 image compression standard as well as providing fully compliant code stream generation for most applications. The ADV202's dedicated video port provides glueless connection to common digital video standards such as ITU.R-BT656, SMPTE125M, SMPTE293M [525p], ITU.R-BT1358 [625p], SMPTE274M[1080i] or SMPTE296M [720p]. A variety of other high speed synchronous pixel and video formats can also be supported using the programmable framing and validation signals. The ADV202 can process images at a rate of 40M samples/sec in reversible mode, and at higher rates when used in irreversible mode. The ADV202
*
* *
* *
Pixel I/F
Pixel I/F External DMA Ctrl
ADV202
Wavelet Engine EC1 EC2 EC3
Host I/F
Pixel FIFO Code FIFO Attr FIFO Ancl FIFO Embedded RISC Processor System Memory System Internal bus and DMA engine
Rev. PrT SURF is a trademark of Analog Devices, Inc.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that my result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
ADV202
PRELIMINARY TECHNICAL DATA
4. FUNCTIONAL DESCRIPTION
The input video or pixel data is passed on to the ADV202's pixel interface where samples are de-interleaved and passed on to the Wavelet Engine where each tile or frame is decomposed into subbands using the 5/3 or 9/7 filters. The resultant wavelet coefficients are then written to internal memory. The entropy codecs then code the image data so that it conforms to the JPEG2000 standard. An internal DMA provides high bandwidth memory to memory transfers as well as high performance transfers between functional blocks and memory. 4.1 Wavelet Engine The ADV202 provides a dedicated wavelet transform processor based on Analog Devices' proven and patented SURFR technology. This processor can perform up to 6 wavelet decomposition-levels on a tile. In Encode mode, the wavelet transform processor will take in uncompressed samples, perform the wavelet transform and write the wavelet coefficients in all frequency subbands to internal memory. Each of these subbands is then further broken down into code-blocks. The code-block dimensions can be user-defined, and are used by the wavelet transform processor to organize the wavelet coefficients into code-blocks when writing to internal memory. Each completed code-block is then entropy coded by one of the Entropy Codecs. In Decode mode, wavelet coefficients are read from internal memory and are recomposed into uncompressed samples. 4.2 Entropy Codecs The entropy codec block performs context modeling and arithmetic coding on a codeblock of the wavelet coefficients. Additionally, this block also performs the distortion metric calculations during compression that are required for optimal rate/distortion performance. Since the entropy coding process is the most computationally intensive operation in the JPEG2000 compression process, three dedicated hardware entropy codecs are provided on the ADV202. 4.3 Embedded Processor System The ADV202 incorporates an embedded 32-bit RISC processor. This processor is used for configuration, control and management of the dedicated hardware functions as well for parsing/generation
contains a dedicated wavelet transform engine, three entropy codecs, on board memory system and an embedded RISC processor which can provide a complete JPEG2000 compression/decompression solution. The wavelet processor supports the 9/7 irreversible wavelet transform and the 5/3 wavelet transform in reversible and irreversible modes. The entropy codecs support all features in the JPEG2000 Part 1 specification, except Maxshift ROI. The ADV202 operates on a rectangular array of pixel samples called a tile. A tile may contain a complete image, up to the maximum supported size, or some portion of an image. The maximum horizontal tile size supported depends on the wavelet transform selected and the number of samples in the tile. Images larger than the ADV202's maximum tile size may be broken into individual tiles and then sent sequentially to the chip while still maintaining a single, fully compliant, JPEG2000 code stream for the entire image. 3.1 JPEG2000 Feature Support The ADV202 supports a broad set of features that are included in Part 1 of the JPEG2000 standard (ISO/IEC 15444). Refer to the "Getting Started with the ADV202" for information as to what JPEG2000 features are presently supported by the ADV202. Depending on the particular application requirements, the ADV202 can provide varying levels of JPEG2000 compression support. It can provide raw code-block and attribute data output which allows the host software to have complete control over the generation of the JPEG2000 code stream and other aspects of the compression process such as bit-rate control. Otherwise the ADV202 can create a complete, fully compliant, JPEG2000 code stream (.j2c) and enhanced file formats such as.jp2,.jpx and.mj2 (Motion JPEG2000). Refer to the "Getting Started with the ADV202" for information what formats are presently supported by the ADV202.
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of the JPEG2000 code stream. The processor system includes ROM and RAM for both program and data memory, an interrupt controller, standard bus interfaces and other hardware functions, such as timers, counters, etc. 4.4 Memory System The memory system's main function is to manage wavelet coefficient data, interim code-block/ attribute data and temporary work space for creation/parsing/storage of JPEG2000 codestream. The memory system can also be used for program and data memory for the embedded processor. 4.5 Internal DMA engine The internal DMA engine provides high bandwidth memory to memory transfers as well as high performance transfers between memory and functional blocks. This function is critical for high speed code stream generation and parsing. 4.6 Configurable FIFO block FIFOs are provided for pixel data, code-stream data, attribute data or ancillary data. The FIFOs can be accessed directly from the host interface using normal addressed read/write cycles or by external host DMA accesses using a DREQ/DACK protocol or by one of the dedicated hardware handshake protocols. Each FIFO also has a programmable threshold that can be used to generate an interrupt. Refer to Appendix for more detail on the dataflow and functional description.
ADV202
cessing, which yields significantly better compression performance for temporally coherent frame based video sources. Additionally, high definition digital video, such as SMPTE-274M (1080i) are supported using two or more ADV202 devices. The video interface can support video data or still image data input/output. 8, 10, 12-bit single or multiplexed components, dual-lane 8, 10, or 12-bit components as explained on the following pages. The VDATA interface supports digital video in YCbCr format in single input mode or Y and CbCr in dual lane input mode. YCbCr data must be in 4:2:2 format. Video data can be input/output in several different modes on the VDATA bus. In all of these modes the pixel clock must be input on the VCLK pin. 5.1.1 EAV/SAV mode: Accepts video with embedded EAV/SAV codes where the YCbCr data is interleaved onto a single bus. 5.1.2 HVF mode: Accepts video data accompanied with separate H, V, F signals where YCbCr data is interleaved onto a single bus. 5.1.3 Extended mode: Y and CrCb are on separate buses accompanied by EAV/SAV codes. 5.1.4 Raw Video mode: This mode is used for still picture data and non-standard video. VFRM, VSTRB, VRDY are used to program the dimension of the image. 5.1.5 High Speed Video mode: This mode is used for applications were video data is clocked into the part at higher rates than 27MHz. 5.2 Host Interface [HDATA bus] The ADV202 can connect directly to a wide variety of host processors and ASICs using an asynchronous SRAM-style interface, DMA accesses or JDATA mode interface. The ADV202 supports 16 and 32-bit buses for control and 8/16/ 32-bit buses for data transfers. The control and data channel bus widths can be specified independently which allows the ADV202 to support applications that require control and data buses of different width. The host interface is used for configuration, control and status functions as well as for transferring compressed data streams. It can be used for
5. ADV202 INTERFACE
There are several possible modes to interface to the ADV202 using the VDATA bus and the HDATA bus or the HDATA bus alone.
5.1 Video Interface [VDATA bus] The video interface can be used in applications where uncompressed pixel data is on a separate bus from compressed data. For example, it is possible to use the VDATA bus to input uncompressed video while using the HDATA bus to output the compressed data. This interface is ideal for applications requiring very high throughput such as live video capture. Optionally the ADV202 interlaces ITU.R-BT656 resolution video, on the fly prior to wavelet pro-
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uncompressed data transfers in certain modes. The host interface may be shared by as many as four concurrent data streams in addition to control and status communications. The data streams are: 1) uncompressed tile data [for example: still image data]. 2) fully encoded JPEG2000 code stream (or unpackaged code blocks), 3) code-block attributes, and 4) ancillary data. The ADV202 uses big endian byte alignment for 16 and 32-bit transfers. All data is left justified [most significant bit].
5.2.4 Control register access With the exception of the indirect address and data registers (IADDR and IDATA) all control/status registers in the ADV202 are 16 bits wide and are half-word (16-bit) addressable only. When 32-bit host mode is enabled, the upper 16 bits of the HDATA bus are ignored on writes and will return all zeros on reads of 16-bit registers. 5.2.5 Pin Configuration and Bus Modes The ADV202 provides a wide variety of control and data configurations which allows it to be used in many applications with little or no glue logic. The modes described below are configured using the BUSMODE register. In the following descriptions `host' is used to refer to normal addressed accesses (i.e., CS/RD/WR/ADDR) and `data' refers to external DMA accesses (i.e., DREQ/DACK). 32-Bit host/32-Bit data In this mode the HDATA<31:0> pins are used to provide full 32-bit wide data access to Pixel, Code, Attr and Ancl FIFOs. The expanded video interface [VDATA] is not available in this mode. 16-Bit host/32-bit data This mode allows a 16-bit host to configure and communicate with the ADV202 while still allowing 32-bit accesses to the Pixel, Code, Attr and Ancl FIFOs using the external DMA capability. All addressed host accesses are 16-bits and therefore only use the HDATA<15:0> pins. The HDATA<31:16> pins are used to provide the additional 16-bits necessary to support the 32-bit external DMA transfers to/from the FIFOs only. The expanded video interface [VDATA] is not available in this mode. 16-Bit host/16-bit data This mode uses 16-bit transfers for if used for host or external DMA data transfers. This mode allows for use of the extended pixel interface modes. 16-Bit host/8-bit data JDATA bus mode This mode provides separate data input/output and host control interface pins. Host control accesses are 16 bits and use HDATA<15:0> while the dedicated data bus uses
5.2.1 Pixel input on Host interface Pixel input on the host interface supports 8/10/12/ 14 or 16-bit raw pixel data formats. It can be used for pixel [still image] input/output or compressed video output. Since there are no timing codes or sync signals associated with the input data on the host interface, dimension registers and internal counters are used and must be programmed to indicate start and end of frame. Refer to the TechNote "ADV202 in HIPI mode" for detail on how to use the ADV202 in this mode. 5.2.2 Host Bus Configuration To provide maximum flexibility, the Host interface provides several configurations to meet particular system requirements. The default bus mode uses the same pins to transfer both control/status and data to/from the ADV202. In this mode, the ADV202 can support 16 or 32-bit control transfers and 8/16/32-bit data transfers. The size of the control/status and data busses can be selected independently. This allows for example a 16-bit micro controller to configure and control the ADV202 while still providing 32-bit data transfers to an ASIC or external memory system. 5.2.3 Direct and Indirect registers In order to minimize pin count and cost, the number of address pins has been limited to four, which yields a total direct address space of 16 locations. These 16 locations are the ones most commonly used by the external controller and are therefore accessible directly. All other registers in the ADV202 can be accessed indirectly through the use of the IADDR and IDATA register.
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JDATA<7:0>. JDATA uses a valid/hold synchronous transfer protocol. The direction of the JDATA bus is determined by the mode of the ADV202. If the ADV202 is encoding (compression) then JDATA<7:0> is an output. If the ADV202 is decoding (de-compressing) then JDATA<7:0> is an input. Host control accesses remain asynchronous. See also 5.4 JDATA mode. 5.3 Stage register Since the ADV202 contains both 16 and 32-bit registers and its internal memory is mapped as 32-bit data, a mechanism has been provided to allow 16-bit hosts to access these registers and memory locations. This is accomplished with the staging register (STAGE). STAGE is accessed as a 16-bit register using HDATA[15:0]. Prior to writing to the desired register, the STAGE register must be written with the upper [most significant] half-word. When the host subsequently writes the lower half-word to the desired control register, HDATA is combined with the previously staged value to create the required 32-bit value that will be written. When a register is read, the upper [most significant] half-word is returned immediately on HDATA and the lower half-word can be retrieved by reading the STAGE register on a subsequent access. Additional information for using the STAGE register can be found in the register section. NOTE: this does not apply to the four data channels (PIXEL, CODE, ATTR or ANCL). These channels are always accessed at the specified data width and do not require the use of the STAGE register. 5.4 JDATA mode The JDATA mode is typically only used when the dedicated video interface [VDATA] is also enabled. This mode allows code stream data [compressed data compliant to JPEG 2000] to be input or output on a single dedicated 8-bit bus (JDATA<7:0>). The bus will always be an output during compression operation, and will be an input during decompression. A two pin handshake is used to transfer data over this synchronous interface. VALID is used to indicate that the ADV202 is ready to provide/accept data and is always an output. HOLD is always an input and is asserted by the host if it can not accept/provide data. For example, JDATA mode allows real time applications, where pixel data is input over the VDATA
ADV202
bus while the compressed data steam is output over the JDATA bus.
5.5 External DMA Interface The External DMA Interface is provided to enable high-bandwidth data I/O between an external DMA controller and the ADV202 data FIFOs. There are two independent DMA channels which can each be assigned to any one of the four data stream FIFOs [Pixel/Code/Attribute/Ancillary]. The controller supports asynchronous DMA using a Data-Request/Data-Acknowledge (DREQ/DACK) protocol in either single or burst access modes. Additional functionality is provided for single address compatibility (Fly-By mode) and Dedicated Chip Select (DCS) modes. 5.6 Serial Communication Ports This port is used to provide serial communication to/from the ADV202 where the ADV202 always is the SPI master. 6. INPUT FORMATS The ADV202 supports a wide variety of formats for uncompressed video and still image data [refer to 8.4 Input formats]. The actual interface and bus modes selected for transferring uncompressed data dictates the allowed size of the input data and the number of samples transferred with each access. The host interface can support 8, 10, 12, 14, 16-bit data formats. The video interface can support video data or still image data input/output. Supported formats are 8, 10, 12 or 16-bit single or 2x8-bit, 2x10-bit, 2x12 bit multiplexed formats [refer to 8.4 Input formats]. All possible formats are listed in section 8 of this datasheet. All formats can support less precision than provided by specifying the actual data width/precision in the PMODE register The maximum allowable data input rate is limited by using irreversible or reversible compression modes and the data width (or precision) of the input samples. Table 1, 2, 3 should be used for determining maximum data input rate.
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Table 1: Maximum pixel data input rates for 144-pin package
APPROX. MIN. PEAK OUTPUT RATE [COMPRESSED DATA]* APPROX. MAX. OUTPUT RATE [COMPRESSED DATA]*
INTER FACE
COMPRESSION MODES
INPUT FORMAT
INPUT RATE LIMIT [ACTIVE RESOLUTION]
HDATA
irreversible irreversible irreversible irreversible reversible reversible reversible reversible
8-bit data 10-bit data 12-bit data 16-bit data 8-bit data 10-bit data 12-bit data 14-bit data 8-bit data 10-bit data 12-bit data 8-bit data 10-bit data 12-bit data
45 Msamples/sec 45 Msamples/sec 45 Msamples/sec 45 Msamples/sec 40 Msamples/sec 32 Msamples/sec 27 Msamples/sec 23 Msamples/sec 65 Msamples/sec 65 Msamples/sec 65 Msamples/sec 40 Msamples/sec 32 Msamples/sec 27 Msamples/sec
130 Mbits/sec 130 Mbits/sec 130 Mbits/sec 130 Mbits/sec 130 Mbits/sec 130 Mbits/sec 130 Mbits/sec 130 Mbits/sec 130 Mbits/sec 130 Mbits/sec 130 Mbits/sec 130 Mbits/sec 130 Mbits/sec 130 Mbits/sec
200 Mbits/sec 200 Mbits/sec 200 Mbits/sec 200 Mbits/sec 200 Mbits/sec 200 Mbits/sec 200 Mbits/sec 200 Mbits/sec 200 Mbits/sec 200 Mbits/sec 200 Mbits/sec 200 Mbits/sec 200 Mbits/sec 200 Mbits/sec
VDATA
irreversible irreversible irreversible reversible reversible reversible
Table 2: Maximum pixel data input rates for 121-pin package
APPROX. MIN PEAK OUTPUT RATE [COMPRESSED DATA]* APPROX. MAX. OUTPUT [COMPRESSED DATA]*
INTER FACE
COMPRESSION MODES
INPUT FORMAT
INPUT RATE LIMIT [ACTIVE RESOLUTI ON]
HDATA
irreversible irreversible irreversible irreversible reversible reversible reversible reversible
8-bit data 10-bit data 12-bit data 16-bit data 8-bit data 10-bit data 12-bit data 14-bit data 8-bit data 10-bit data 12-bit data 8-bit data 10-bit data 12-bit data
34 Msamples/sec 34 Msamples/sec 34 Msamples/sec 34 Msamples/sec 30 Msamples/sec 24 Msamples/sec 20 Msamples/sec 17 Msamples/sec 48 Msamples/sec 48 Msamples/sec 48 Msamples/sec 30 Msamples/sec 24 Msamples/sec] 20 Msamples/sec]
98 Mbits/sec 98 Mbits/sec 98 Mbits/sec 98 Mbits/sec 98 Mbits/sec 98 Mbits/sec 98 Mbits/sec 98 Mbits/sec 98 Mbits/sec 98 Mbits/sec 98 Mbits/sec 98 Mbits/sec 98 Mbits/sec 98 Mbits/sec
150 Mbits/sec 150 Mbits/sec 150 Mbits/sec 150 Mbits/sec 150 Mbits/sec 150 Mbits/sec 150 Mbits/sec 150 Mbits/sec 150 Mbits/sec 150 Mbits/sec 150 Mbits/sec 150 Mbits/sec 150 Mbits/sec 150 Mbits/sec
VDATA
irreversible irreversible irreversible reversible reversible reversible
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Table 3: Maximum supported tile width for data input on HDATA and VDATA bus Compression Mode 9/7i 9/7i 9/7i 5/3i 5/3i 5/3i 5/3r 5/3r 5/3r Input format Single component Two component Three component Single component Two component Three component Single component Two component Three component Tile/Precinct max. width 2048 1024 each 1024 [Y] 4096 2048 [each] 2048 [Y] 4096 2048 1024
* Min. peak output rate or guaranteed sustained output rate. Max. output rate or a output rate above this value is not possible.
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7. PIN CONFIGURATIONS
ADV202
Table 4: Pin configurations NAME MCLK PINS 1 121-PIN PACKAGE L9 144-PIN PACKAGE L12 I/O I DESCRIPTION System input clock. For more detail refer to PLL register section. Maximum input frequency on MCLK is 74.25MHz. Reset. Causes the ADV202 to immediately reset. For more detail refer to Boot mode register section. CS/, RD/, WE/, DACK0/, DACK1/, DREQ0, DREQ1 must be held high when a RESET/ is applied. Host data bus. With HDATA<23:16>, <27:24>, <31:28> these pins make up the 32-bit wide host data bus. The async host interface is interfaced together with ADDR<3:0>,CS, WE, RD, ACK. Unused HDATA pins should be pulled-down via a 10K resistor. Address bus for the host interface. Chip select.This signal is used to qualify addressed read and write access to the ADV202 using the host interface. Write Enable used with the host interface. Read Enable when "Fly-by" DMA is enabled. Note: simultaneous assertion of WE/ and DACK/ low will activate the HDATA bus, even if the DMA channels are disabled. RD 1 H9 G12 I Read Enable used with the host interface. Write Enable when "Fly-by" DMA is enabled. Note: simultaneous assertion of RD/ and DACK/ low will activate the HDATA bus, even if the DMA channels are disabled.
RESET
1
L7
L11
I
HDATA<15:0>
16
D4-D1 C5-C3 B5, B4, C2 B3-B1 A2, A6-A5
F4, E1-E3, D1-D3, C1-C3, B1-B3, A2, A3, A4
I/O
ADDR<3:0> CS
4 1
H11, K8, H10, J9 J8
J12, J11, J10, H12 H11
I I
WE
1
J7
H10
I
RDFB
WEFB
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Table 4: Pin configurations NAME ACK PINS 1 121-PIN PACKAGE H8 144-PIN PACKAGE G11 I/O O
ADV202
DESCRIPTION Acknowledge. Used with the host interface. This signal indicates that the last register access was successful. Note: due to synchronization issues, control and status register accesses may incur an additional delay, so the host software should wait for acknowledgement from the ADV202. Accesses to the FIFOs [External DMA modes], on the other hand, are guaranteed to occur immediately and should not wait for ACK provided that the timing constraints are observed. If ACK/ is shared with more than one device, ACK/ should be connected to a pull-up resistor [10K] and the PLL_HI register, bit 4 must be set to `1'.
IRQ
1
G10
G10
O
Interrupt. This pin indicates that the ADV202 requires the attention of the host processor. This pin can be programmed to indicate the status of the internal interrupt conditions within the ADV202. The interrupt sources are enabled via bits in register EIRQIE.
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Table 4: Pin configurations NAME DREQ0 PINS 1 121-PIN PACKAGE F8 144-PIN PACKAGE F12 I/O O DESCRIPTION Data Request for External DMA interface. Indicates that the ADV202 is ready to send/receive data from/to the FIFO assigned to DMA channel 0. Must be held high at all times if the DMA interface is not used, even if the DMA channels are disabled. Used in DCS-DMA mode. Service request from the FIFO assigned to channel 0 (asynchronous mode). Valid indication for JDATA input/output stream. Polarity of this pin is programmable in the EDMOD0 register. VALID is always an output.
O FSRQ0
O VALID
I CFG<1>
Boot mode configuration. This pin is read on reset to determine the boot configuration of the on-board processor. The pin should be tied to IOVDD or IOGND through a 10 Kohm resistor. Details of boot modes can be found in the BOOT register description below. Data Acknowledge for External DMA interface. Signal from the host CPU that indicates that the data transfer request (DREQ0) has been acknowledged and data transfer can proceed. Must be held high at all times if the DMA interface is not used, even if the DMA channels are disabled.
DACK0
1
F9
F11
I
HOLD
I
External hold indication for JDATA input/ output stream. Polarity is programmable in the EDMOD0 register. This pin is always and input. Used in DCS-DMA mode. Chip select for the FIFO assigned to channel 0 (asynchronous mode).
FCS0
I
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Table 4: Pin configurations NAME DREQ1 PINS 1 121-PIN PACKAGE F10 144-PIN PACKAGE F10 I/O O
ADV202
DESCRIPTION Data Request for External DMA interface. Indicates that the ADV202 is ready to send/receive data from/to the FIFO assigned to DMA channel 1. Must be held high at all times if the DMA interface is not used, even if the DMA channels are disabled.
FSRQ1
O
Used in DCS-DMA mode. Service request from the FIFO assigned to channel 1 (asynchronous mode).
CFG<2>
I
Boot mode configuration. This pin is read on reset to determine the boot configuration of the on-board processor. The pin should be tied to IOVDD or IOGND through a 10 Kohm resistor. Details of boot modes can be found in the BOOT register description below. Data Acknowledge for External DMA interface. Signal from the host CPU that indicates that the data transfer request (DREQ1) has been acknowledged and data transfer can proceed. Must be held high at all times if the DMA interface is not used, even if the DMA channels are disabled.
DACK1
1
G9
F9
I
FCS1
I
Used in DCS-DMA mode. Chip select for the FIFO assigned to channel 1 (asynchronous mode).
HDATA<31:28> JDATA<7:4> HDATA<27:24> JDATA<3:0> VDATA<23:20>
4
J2-J4,H1
K3, J1-J3
I/O I/O
Host expansion bus. JData bus (JDATA mode) Host expansion bus. JData bus (JDATA mode) Video Data expansion bus
4
H2-H4, G4
J4, H1-H3
I/O I/O I/O
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Table 4: Pin configurations NAME HDATA<23:16> PINS 8 121-PIN PACKAGE G3, G2, F4, F3, F2 E2, E3, E4 144-PIN PACKAGE H4, G1-G4, F1-F3 I/O I/O DESCRIPTION Host expansion bus.
VDATA<19:12>
I/O
Video Data expansion bus. Extended Pixel Interface mode. Used for video formats which use Y and CrCb on separate buses.
SCOMM<7> SCOMM<6>
8
L2 L3
M2 M3
I/O I/O
When not used should be tied low. When not used should be tied low.
SCOMM<5>
L4
M4
I/O
This pin must be used in multiple chip mode to align the outputs of two or more ADV202s. For more detail refer to Applications section and the `ADV202 multi-chip application' Appnote. When not used should be tied low. LCODE output in encode mode. When LCODE is enabled, the output on this pin indicates on a high transition that the last data word for a field has been read from the FIFO. For an 8-bit interface, i.e JDATA, LCODE will be asserted for 4 consecutive bytes and is enabled by default.
SCOMM<4>
K1
L1
O
SCOMM<3>
K2
L2
O
SPI interface: S_CSEL. Should be tied low when not used. Only used with boot mode 6. SPI interface: S_MO. Should be tied low when not used. Only used with boot mode 6. SPI interface: S_MI. Should be tied low when not used. Only used with boot mode 6. SPI interface: S_CLK. Should be tied low when not used. Only used with boot mode 6.
SCOMM<2>
L5
L3
O
SCOMM<1>
K4
K1
I
SCOMM<0>
K3
K2
O
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Table 4: Pin configurations NAME VCLK PINS 1 121-PIN PACKAGE E9 144-PIN PACKAGE E12 I/O I
ADV202
DESCRIPTION Video Data clock. Must be supplied if video data is input/output on the VDATA bus. Video Data. Unused pins should be pulled down via a 10K resistor.
VDATA<11:0>
12
D11, D10, C7, C9, C10, B7, B8, B9, B11, B10, A7, A10 D8
I/O D10-D12, C10-C12, B10-B12, A9-A11 E10 I/O
VSYNC VFRM HSYNC VRDY FIELD VSTRB TEST1
1
Vertical sync for video mode. Raw pixel mode framing signal. Indicates first sample of a tile when asserted high.
1
D9
E11
I/O O
Horizontal sync for video mode Raw pixel mode ready signal Field sync for video mode Raw pixel mode transfer strobe. Should be connected to ground via a pull-down resistor. Should be connected to ground via a pull-down resistor. Should be connected to ground via a pull-down resistor. Should be connected to ground via a pull-down resistor. No connect. Positive supply for core
1
E10
E9
I/O I
1
J6
K12
I
TEST2 TEST3 TEST4 TEST5 VDD
1 1 1 1
K9 J10 L6 K10 A3, A8, D7,H7
K11 K10 M9 L10 B6, B7, C6, C7, D6, D7, J6, J7, K6, K7, L6, L7
I I I O P
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Table 4: Pin configurations NAME DGND PINS 121-PIN PACKAGE A1, A11,A4, A9, C1, C11, D6, E1, E5-E7, E11, F1, F5-F7, F11, G1, G5-G7, G11,H6, J1, J11, K11, L1, L8, L11 144-PIN PACKAGE A1, A5-A8, A12, B5, B8, C5, C8,D5, D8, E4-E8, F5-F8, G5-G9, H5-H9, J5, J8-J9, K5,K8,L5, L8,M1, M5-M8, M12, M11 PLLVDD IOVDD 1 L10 B6, C6, C8 D5,E8, G8, H5, J5, K5, K6, K7, M10 B4, B9, C4,C9, D4,D9, K4,K9, L4,L9, P P Positive supply for PLL Positive supply for I/O. I/O G DESCRIPTION Ground for core
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8. DIRECT AND INDIRECT REGISTERS
ADV202
The following section describes the direct and indirect registers of the ADV202. The "Getting Started..." application note describes how and which registers to access to operate the ADV202. This section contains a functional description of the registers only.
8.1 Direct Register Definition
Direct register access is required regardless of what interface is used [SPI, JDATA mode, Normal Host mode, all DMA modes etc.]. The direct registers are accessed over the ADDR [3-0], CS/, RD/, WR/, ACK/ pins. The host has to initialize these registers before any application specific operation can take place.
Table 5: Direct Registers
DIRECT REGISTER ADDRESS NAME DESCRIPTION
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0X0F
PIXEL CODE ATTR ANCL CMDSTA EIRQIE EIRQFLG SWFLAG BUSMODE MMODE STAGE IADDR IDATA BOOT PLL_HI PLL_LO
Pixel FIFO Access Register Compressed Code Stream Access Register Attribute FIFO Access Register Ancillary FIFO Access Register Command Stream FIFO External Interrupt Enabled External interrupt Flags Software Flag Register Bus Mode Configuration Register Miscellaneous Mode Register Staging Register Indirect Address Register Indirect Data Register Boot Mode Register PLL Control Register - High Byte PLL Control Register - Low Byte
0x0
PIXEL
Pixel FIFO access register
R/W
This register is used to access the Pixel data FIFO via normal addressed accesses and generally is used for pixel data input on the host interface [HIPI mode - Host Interface Pixel Interface mode]. The actual number of bits accepted or returned on this register depends on the host data mode selected [BUSMODE]. 8-bit data mode will accept/return data on bits <7:0>, 16-bit mode will accept/return data on bits <15:0> and 32-bit mode will use all bits. Unused bits will be ignored on writes and return zeros on reads. The size of the PIXEL FIFO register is limited to 256x32-bits and can not be changed as for the other FIFOs with the settings in the FFMODE register. A read operation when the PIXEL FIFO is empty or a write when it is full,
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will cause the PFERR bit in the EIRQFLG to be asserted.
Bits 31:0
Name PDATA
Description Pixel data
Reset Value undef
0x1
CODE
Compressed code stream access register
R/W
This register is used to access the JPEG2000 compressed code stream FIFO via normal addressed accesses. It is also used for accessing raw code blocks when the ADV202 is in HIPI mode [Host Interface Pixel Interface mode]. The actual number of bits accepted or returned on this register depends on the host data mode selected [BUSMODE]. 8-bit data mode will accept/return data on bits <7:0>, 16-bit mode will accept/return data on bits <15:0> and 32-bit mode will use all bits. Unused bits will be ignored on writes and return zeros on reads. A read operation when the CODE FIFO is empty or a write when it is full, will cause the DFERR bit in the EIRQFLG to be asserted.
Bits 31:0
Name CDATA
Description Compressed data
Reset Value undef
0x2
ATTR
Attribute FIFO access register
R/W
This register is used to access the attribute FIFO via normal addressed accesses. The actual number of bits accepted or returned on this register depends on the host data mode selected [BUSMODE]. 8-bit data mode will accept/return data on bits <7:0>, 16-bit mode will accept/return data on bits <15:0> and 32-bit mode will use all bits. Unused bits will be ignored on writes and return zeros on reads. A read operation when the ATTR FIFO is empty or a write when it is full, will cause the AFERR bit in the EIRQFLG to be asserted.
Bits 31:0
Name ADATA
Description Code-block attribute data
Reset Value undef
0x3
ANCL
Ancillary FIFO access register
R/W
This register is used to access the Ancillary data FIFO via normal addressed accesses. The actual number of bits accepted or returned on this register depends on the host data mode selected [BUSMODE]. 8-bit data mode will accept/return data on bits <7:0>, 16-bit mode will accept/return data on bits <15:0> and 32-bit mode will use all bits. Unused bits will be ignored on writes and return zeros on reads. A read operation when the ANCL FIFO is empty or a write when it is full, will cause the NFERR bit in the EIRQFLG to be asserted.
Bits 31:0
Name NDATA
Description Ancillary data
Reset Value undef
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ADV202
WO
0x4
CMDSTA
Command stream port
Bits 31:0
Name CMDSTA
Description Reserved. For internal use only.
Reset Value undef
0x5
EIRQIE
External interrupt enables
R/W
This register is used to enable conditions that will cause an external interrupt to occur on the IRQ/ pin. Refer to the "Getting Started with the ADV202" for details on how to use this register.
Bits 0 1 2 3 4 5 6 7 8 9 10
Name PFTH DFTH AFTH NFTH PFERR DFERR AFERR NFERR Reserved Reserved SWIRQ0
Description Pixel FIFO threshold condition exists (Level sensitive) Data FIFO threshold condition exists (Level sensitive) Attribute FIFO threshold condition exists (Level sensitive) Ancillary FIFO threshold condition exists (Level sensitive) Pixel FIFO has overflowed or underflowed Data FIFO has overflowed or underflowed. Attribute FIFO has overflowed or underflowed. Ancillary FIFO has overflowed or underflowed. Always write 0 Always write 0 Software interrupt 0. Refer to "Getting Started with the ADV202" application note for more detail. Software interrupt 1. Refer to "ADV202 multi-chip application" application note for more detail. Software interrupt 2. Reserved for future use. Error occurred on indirect register access Internal hardware interrupt The ADV202 has encountered an unexpected fatal error
Reset Value 0 0 0 0 0 0 0 0 0 0 0
11 12 13 14 15
SWIRQ1 SWIRQ2 INDERR IHWDIRQ FERR
0 0 0 0 0
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0x6 EIRQFLG
PRELIMINARY TECHNICAL DATA
External interrupt flags
R/W
This register indicates which external interrupt conditions are currently active. The bits in this register correspond directly to the bits in the external interrupt enable register (EIRQIE). Individual interrupts are cleared by writing a `1' in the proper bit position of this register (i.e., "Write 1 to clear".) Reset Value 1 1 1 1 0 0 0 0 0 0 Software interrupt 0 Software interrupt 1 Software interrupt 2 Error occurred on indirect register access Internal hardware interrupt The ADV202 has encountered an unexpected fatal error 0 0 0 0 0 0
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Name PFTH DFTH AFTH NFTH PFERR DFERR AFERR NFERR Reserved Reserved SWIRQ0 SWIRQ1 SWIRQ2 INDERR IHWDIRQ FERR
Description Pixel FIFO threshold condition exists (Level sensitive) Data FIFO threshold condition exists (Level sensitive) Attribute FIFO threshold condition exists (Level sensitive) Ancillary FIFO threshold condition exists (Level sensitive) Pixel FIFO has overflowed or underflowed Data FIFO has overflowed or underflowed. Attribute FIFO has overflowed or underflowed. Ancillary FIFO has overflowed or underflowed.
0x7
SWFLAG
Software flag register
RO
Bits 15:0
Name SWFLAGS
Description Reserved. For internal use only
Reset Value undef
0x8
BUSMODE
Bus mode configuration register
R/W
Configures host control and data busses. Reset Value 1 1
Bit(s) 1:0 3:2
Name HWIDTH DWIDTH
Description Host control data width, 1=half-word [16-bits], 2=word[32-bits] DMA data width, 0=byte [8-bits], 1=half-word [16-bits], 2=word [32-bits]
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ADV202
Reset Value 0
Bit(s) 6:4
Name BCFG
Description Bus configuration 0 Normal. HDATA [31:16] are available for host or data transfers according to the settings of HWIDTH and DWIDTH. For normal read/write access HWIDTH and DWIDTH are set to 1 or 2. For DMA mode HDWIDTH and DWIDTH can take any settings. 1 JDATA Mode (JDATA). Enables JDATA[7:0]. HWIDTH/DWIDTH can not be set to 2. 2 Extended Video Interface. Enables HDATA [27:16] to be used as a video extension bus where Y and CbCr data is used on separate buses. HWIDTH/DWIDTH can not be set to 2. 3-7 Reserved Reserved for future use; always write 0. Reserved for future use; always write 0.
7 15:8
Reserved N/A
0 undef
0x9
MMODE
Misc mode configuration register
R/W
Configures miscellaneous functions for Indirect Access. Reset Value 1
Bit(s) 1:0
Name IWIDTH
Description Indirect access width 0 Byte [8-bits] 1 Half-word [16-bits] 2 Word [32-bits] 3 Invalid IADDR step size. IADDR can automatically increment/decrement after each internal access based on the value of IAUTOINC. Increment/decrement is selected using bit 4 in this register. 0 Byte addressing 1 Half-word addressing 2 Word addressing. Note: all internal/indirect registers are on word boundaries. 3 Disable auto increment/decrement Indirect address modify mode 1 0=increment, 1=decrement Control register address mode. Enable full indirect address map Control register mode. The upper 16-bits of the internal address are forced to the beginning of the control register address map. This eliminates the need to set the upper 16-bits of the indirect address register prior to each access. Full address mode. Provides full access to the ADV202's internal address space.
3:2
IAUTOSTP
2
4 5
IAUTOMOD CTLREGAM
0 0
0 15:6 Reserved
Reserved for future use; always write 0.
0
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0xA STAGE
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Staging register R/W
This register is used to access Words (32-bit) when using a 16-bit host control bus. The STAGE register acts as a holding register. When writing to a 32-bit register with a 16-bit host, the host first writes the upper (most significant) half-word to the STAGE register prior to writing the lower half-word to the desired register address. When reading a 32-bit register with a 16-bit host, the host first reads the desired register to acquire the upper half-word, and then reads the STAGE register to acquire the lower half-word. Reset Value undef
Bits 15:0
Name STG
Description Staged value for a write access, or from a read access.
In the following examples, bit <31> is denoted as the most significant bit and bit <0> is the least significant. Ex 1. Writing to the 32-bit IDATA register with a 16-bit host. The 16-bit host provides the data on the HDATA<15:0> pins. First write: Second write: IDATA<31:16> IDATA<15:0> is written to the STAGE register (address 0xA) is written to the IDATA register (address 0xC)
Ex 2. Reading the 32-bit IDATA register with a 16-bit host. In this mode, half-word(16-bit) data will be returned on the HDATA<15:0> pins. First read: Second read: IDATA<31:16> IDATA<15:0> is read from IDATA register (address 0xC) is read from STAGE register (address 0xA)
0xB
IADDR
Indirect address register
R/W
This register is used to set the address for indirect register accesses. The indirect address may optionally be auto-incremented by setting the IAUTOMOD and IAUTOSTP fields in the MMODE register. Reset Value undef
Bits 31:0
Name ADDR
Description Indirect address register
0xC
IDATA
Indirect data register
R/W
This register is used to access indirect registers. Reset Value undef
Bits 31:0
Name DATA
Description Indirect data register
0xD
BOOT
BOOT mode register
R/W
This register is used to read/set the boot mode and initiate a soft or hard reset of the ADV202. Note: A hard reset, via the reset pin or setting the HARDRST bit causes bits 2:0 to be loaded from the configuration pins as specified below, all other bits in this register will be set as specified in the table. A soft reset, via setting the SOFTRST bit will ONLY clear the SOFTRST bit, all other bits will remain unchanged.
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Bits 2:0
Name BOOTMODE
Description Boot mode. These bits are used to select various boot modes of the ADV202 after reset to load specific instruction sets into memory. The boot mode can be configured via hardware [over the CFG pins] or via software [via firmware]. In a hardware configuration, after a hard reset the boot mode will be set to the values on the configuration pins CFG<2-1>. These bits do not get reset on a soft reset, see HARDRST and SOFTRST bit definitions below. The first boot mode after power-up is set by the CFG pins. Only boot modes 2, 4 and 6 are available in hardware bootmode. SOFTWARE BOOTMODE 0 1 2 Reserved. For internal use only. Do not use. Reserved. For internal use only. Do not use. No-Boot Host mode, ADV202 does not boot but all internal registers and memory are accessible through normal host I/O operations. Refer to the "Getting started with the ADV202" application note. Reserved. SoC boot mode. The Embedded Software Framework [ESF] gets control and establishes communications with the host. This mode will be available on the released version of the ADV202. Co-Processor Boot. Is used in conjunction with No-Boot Host mode and starts loaded firmware. Refer to the "Getting started with the ADV202" application note. Boot firmware over SPI from external flash memory. This mode will be available on the released version of the ADV202. Reserved.
Reset Value See Text
3 4
5
6 7
HARDWARE BOOTMODE 0 1 2 Reserved. For internal use only. Do not use. Not available. No-Boot host mode, ADV202 does not boot but all internal registers and memory are accessible through normal host I/O operations. Refer to the "Getting started with the ADV202" application note. Not available. SoC boot mode. The Embedded Software Framework [ESF] gets control and establishes communications with the host. This mode will be available on the released version of the ADV202. Not available. Boot firmware over SPI from external flash memory. Not available.
3 4
5 6 7
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0xE PLL_HI
PRELIMINARY TECHNICAL DATA
PLL control register (high byte)
R/W
This register is used to configure the on chip PLL. HDATA<7:0> are used to set this register regardless of host mode. Internally, the ADV202 uses two clock domains which are generated by an on chip Phase Locked Loop from the input clock MCLK. JCLK is used to clock all of the JPEG2000 specific hardware blocks and HCLK is used to clock the embedded processor system. A block diagram of the PLL and its control parameters are shown in the figure below. Reset Value 0 0 0 1
Bits 0 1 2 3 4 6:4 7 15:8
Name PLLPDN BYPASS reserved HCLKD ACK_FN reserved SM N/A
Description Power down enable = 1 Bypass enabled = 1 always write 0 HCLK divider enabled = 1 ACK/ is in high-impedance mode = 0 ACK/ is configured as open drain output = 1 ADI use only; always write 0 ADI use only; always write 0 Not applicable
undef 0 undef
0xF
PLL_LO
PLL control register (low byte)
R/W
This register is used to configure the on chip PLL. HDATA<7:0> are used to set this register regardless of host mode. Reset Value 6 0 0 0 undef
Bits 4:0 5 6 7 15:8
Name PLLMULT LFB reserved IPD N/A
Description Multiplier [values from 0 to 31] Loop feedback divider enable = 1 Always write 0 Input clock divider enable = 1 Not applicable
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ADV202
BYPASS IPD
MCLK
2
PHASE DETECT
JCLK LPF VCO
HCLK
2 2
PLLMULT HCLKD LFB
Equivalent transfer function:
JCLK _________ = MCLK
PLLMULT * LFB IPD
Figure 9. PLL architecture and control functions
Table 1: Recommended Register Settings for PLL registers1 IPD 0 0 0 0 1 1 1 1 LFB 0 0 1 1 0 0 1 1 PLLMULT N N N N N N N N HCLKD 0 1 0 1 0 1 0 1 HCLK N * MCLK N * MCLK / 2 2 * N * MCLK N * MCLK [N * MCLK] / 2 [N * MCLK] / 4 N * MCLK N * MCLK / 2 JCLK N * MCLK N * MCLK 2 * N * MCLK 2 * N * MCLK [N * MCLK] / 2 N * MCLK / 2 N * MCLK N * MCLK
Note 1: The PLL can be programmed to have any possible final multiplier value as long as: 1. JCLK >50MHz and <150MHz. 2. HCLK <115 MHz. 3. JCLK >= 2x VCLK for single component input. 4. JCLK >= 2x VLCK for YCrCb [4:2:2] input for silicon rev 0.0. 5. In JDATA Mode [JDATA] JCLK must be 4x MCLK or higher. 6. The max. burst frequency for external DMA modes is <= 0.44 JCLK 7. If MCLK is larger than 50 MHz, the input clock divider must be enabled, i.e. IPD set to `1'.
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If any settings in the PLL registers are changed, a period of 20us should be allowed for the part to re-lock after changing these settings. Example: For lowest power consumption an MCLK=27MHz is recommended for a standard definition CCIR656 input. The PLL circuit is recommended to be set to a total multiplier of 3. This will set JCLK and HCLK to 81MHz.
Table 2: Recommended register values for PLL registers VIDEO STANDARD SMPTE125M or ITU-R.BT656 [NTSC or PAL] SMPTE293M [525p] ITU-R.BT1358 [625p] SMPTE274M [1080i] 27MHz 27MHz 74.25MHz 0x0008 0x0008 0x0008 0x0004 0x0004 0x0084 CLKIN FREQUENCY ON MCLK 27MHz PLL_HI 0x0008 PLL_LOW 0x0004
8.2 Indirect Register Definition
These registers are generally accessed by the ESF [Embedded Software Framework] or downloadable firmware only. In this case indirect registers are configured automatically depending on which functions are selected with the ESF or firmware. In certain modes, for instance custom specific input format or HIPI mode, indirect registers have to be accessed by the user through the use of the IADDR and IDATA registers. The indirect register address space starts at internal address 0xFFFF0000. If the CTRLREGAM bit in the direct register MMODE is set to FULL ADDRESS MODE, then the complete 32-bit address must be loaded into IADDR before accessing the desired indirect register. Otherwise, the user only needs to load the 16 least significant bits of the desired register address.
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ADV202
Table 3: Indirect Registers
INDIRECT REGISTER ADDRESS
NAME PMODE1 COMP_CNT_STATUS LINE_CNT_STATUS XTOT YTOT F0_START F1_START V0_START V1_START V0_END V1_END PIXEL_START PIXEL_END PI_STATUS MS_CNT_DEL LINE_CNT_INTERRUPT PMODE2 VMODE EDMOD0 EDMOD1 FFMODE FFTHRP FFTHRC FFTHRA FFTHRN FFCNTP FFCNTC FFCNTA FFCNTN Reserved
DESCRIPTION Pixel/Video Format Horizontal count Vertical count Total Samples per line Total Lines per frame Start Line of Field 0 [F0] Start Line of Field 1 [F1] Start of active video Field 0 [F0] Start of active video Field 1 [F1] End of active video Field 0 [F0] End of active video Field 1 [F1] Horizontal start of active video Horizontal end of active video Pixel/Video Status Register Master/Slave Delay Line count interrupt Pixel Mode 2 Video Mode External DMA mode register 0 External DMA mode register 1 FIFO mode register FIFO Threshold for Pixel FIFO FIFO Threshold for Code FIFO FIFO Threshold for ATTR FIFO FIFO Threshold for ANCL FIFO FIFO Full/Empty count for PIXEL FIFO FIFO Full/ Empty count for CODE FIFO FIFO Full/Empty count for ATTR FIFO FIFO Full/Empty count for ANCL FIFO Reserved
0xFFFF0400 0xFFFF0404 0xFFFF0408 0xFFFF040C 0xFFFF0410 0xFFFF0414 0xFFFF0418 0xFFFF041C 0xFFFF0420 0xFFFF0424 0xFFFF0428 0xFFFF042C 0xFFFF0430 0xFFFF0434 0xFFFF0440 0xFFFF0444 0xFFFF0448 0xFFFF044C 0xFFFF1408 0xFFFF140C 0xFFFF1418 0xFFFF1410 0xFFFF141C 0xFFFF1420 0xFFFF1424 0xFFFF1414 0xFFFF1428 0xFFFF142C 0xFFFF1430 0xFFFF1434 0xFFFF14FC
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0xFFFF0400
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PMODE1
R/W
PFMT and PREC are used to configure the VDATA or HDATA bus for a specific pixel format.
Bits 4:0
Name PFMT
Forma t 4 5 6 7 8-15 16 17 18 19 20 21 22 23 24 25 26 27 28-31
Description 12-bit Single Component 12-bit Cb/Y/Cr/Y interleaved Reserved 12-bit Cb/Cr interleaved Reserved 24-bit 2x12-bit Packed Single Component 24-bit 2x12-bit Packed CbY/CrY interleaved Reserved 24-bit 2x12-bit Packed CbCr 32-bit 4x8-bit Single Component 32-bit 4x8-bit Packed YCbYCr 32-bit 4x8-bit Packed YYCbCr 32-bit 4x8-bit Packed CbCrCbCr 32-bit 2x16-bit Packed Single Component 32-bit 2x16-bit Packed YCb/YCr 32-bit 2x16-bit Packed YY/CbCr 32-bit 2x16-bit Packed CbCr Reserved Always write 0
Interface VDATA VDATA VDATA
Reset Value 0x5
VDATA VDATA
VDATA HDATA HDATA HDATA HDATA HDATA HDATA HDATA HDATA
7:5 10:8
Reserved PREC 0 1 2 3 4 5-7
0 1
8-bit precision 10-bit precision 12-bit precision 14-bit precision 16-bit precision Reserved Always write 0
15:11
Reserved
0
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0xFFFF0404
COMP_CNT_STATUS
RO
The value in this register indicates the number of columns [samples] presently read into the Pixel interface. It is a horizontal counter.
Bits 15:0
Name COMP_CNT_STAT
Description Sample count.
Reset Value 0x0
0xFFFF0408
LINE_CNT_STATUS
RO
The value in this register indicates the number of lines presently read into the Pixel interface. It is a vertical counter.
Bits 15:0
Name LINE_CNT_STAT
Description Line Count.
Reset Value 0x0
0xFFFF040C
XTOT
R/W
Reset Value 0x64b
This register is used to set total number of samples per line.
Bits 15:0
Name XTOT
Description Total samples per line
0xFFFF0410
YTOT
R/W
This register is used to set the total lines per frame for progressive standards or per field for interlaced standard.
Bits 15:0
Name YTOT
Description Total lines per frame
Reset Value 0x20d
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ADV202
R/W
0xFFFF0414
F0_START
This register is used to indicate the start of Field 0 in units of number of lines. Line count starts with line 1.
Bits 15:0
Name F0_START
Description Start of Field 0. Only used in Decode mode to identify at which line number the Field bit will transition from Field 1 to Field 0.
Reset Value 0x20d
0xFFFF0418
F1_START
R/W
This register is used to indicate the start of Field 1 in units of number of lines. Line count starts with line 1. Reset Value 0x10a
Bits 15:0
Name F1_START
Description Start of field 1. Only used in Decode mode to identify at which line number the Field bit will transition from Field 0 to Field 1.
0xFFFF041C
V0_START
R/W
This register is used to set the first active video line in Field 0 that will be captured by the ADV202. Line count starts with line 1.
Bits 15:0
Name V0_START
Description Start of active video in field 0
Reset Value 0x14
0xFFFF0420
V1_START
R/W
This register is used to set the first active video line in Field 1 that will be captured by the ADV202. Line count starts with line 1.
Bits 15:0
Name V1_START
Description Start of active video in field 1
Reset Value 0x11b
0xFFFF0424
V0_END
R/W
This register is used to set the vertical end of the active video in Field 0. This register should hold the value of the last active line number. Line count starts with line 1.
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Bits 15:0
Name V0_END
Description End of active video in field 0
Reset Value 0x107
0xFFFF0428
V1_END
R/W
This register is used to set the vertical end of the active video in Field 1. This register should hold the value of the last active line number. Line count starts with line1.
Bits 15:0
Name V1_END
Description End of active video in field 1
Reset Value 0x20d
0xFFFF042C
PIXEL_START
R/W
Reset Value 0x1
This register is used to set the horizontal start of the active video in units of samples.
Bits 15:0
Name PIXEL_START
Description Start of horizontal active video
0xFFFF0430
PIXEL_END
R/W
Reset Value 0x5A0
This register is used to set the horizontal end of the active video in units of samples.
Bits 15:0
Name PIXEL_END
Description End of horizontal active video
8.3 Video timing and dimension registers
8.3.1 Encode mode In encode mode the part is always in slave configuration. Input data can be accompanied by separate H,V,F signals or embedded timing codes. In both cases, XTOT, YTOT, V0_START, V1_START, V0_END, V1_END, PIXEL_START, PIXEL_END must reflect the video standard of the input. The part synchronizes itself to the incoming sync signals. Fields are identified by the incoming FIELD signal or the Field bit in the EAV/SAV codes. Using the value of registers Vx_START, Vx_END, PIXEL_START, PIXEL_END the active video region to be processed is calculated. This does apply to all input modes using the VDATA bus, in HIPI mode only values for XTOT and YTOT need to be programmed, all other dimension register values are ignored in HI PI mode [refer to "ADV202_HIPI_mode" application note]. 8.3.2 Decode slave In decode slave mode input data can be accompanied by separate H,V,F signals or embedded timing codes. In both cases, XTOT, YTOT, V0_START, V1_START, V0_END, V1_END, PIXEL_START, PIXEL_END must reflect the video standard of the input. The part synchronizes itself to the incoming sync signals. Fields are identified by the incoming FIELD signal or the Field bit in the EAV/SAV codes.
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8.3.3 Decode master
ADV202
VSYNC/VFRM, HSYNC/VRDY, FIELD/VSTRB are generated according to the register settings of: XTOT, YTOT, F0_START, F1_START, F0_END, F1_END, V0_START, V1_START, V0_END, V1_END, PIXEL_START, PIXEL_END. To enable the generation of these timing signals in decode mode, VMODE register must be programmed to decode master mode. VFRM, VRDY, VSTRB are generated when VMODE is set to RAW_MODE. The polarity of VSYNC/VFRM, HSYNC/VRDY, FIELD/VSTRB is programmed in PMODE2 with VSYNC_POL, HSYNC_POL, FIELD_POL.
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PRELIMINARY TECHNICAL DATA
HSYNC/VRDY
[HSYNC_POL = 0]
FIELD/VSTRB
V0_VID START
Captured Tile Field 0
Active edge
[VSYNC_POL = 0]
V0_VID END V1_VID START VSYNC/VFRM
Active edge
[VSYNC_POL = 0]
Captured Tile Field 1
Active edge
[FIELD_POL = 1]
V1_VID END
PX_START
PX_END
YTOT
XTOT
FIGURE 10. Pixel dimension registers [FFFF040C-FFFF0430]
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0xFFFF0434
Bits 0 Name ACTIVE_VIDEO
ADV202
R
Reset Value 0x0
PI_STATUS
Description Active Video Region status. This status bit is activated whenever active video is being processed. Pixel Interface to Wavelet Transform Strobe status. This status bit is activated when valid data is send from the PI to the WT. Wavelet Transform to Pixel Interface Ready status. This status bit is activated when valid data is send from the WT to the PI. Pixel Interface to Host Interface Ready status. This status bit is asserted to signal a valid data transfer between PI and Host interface. Input Field status. This status bit is the FSYNC routed from the PI input. It allows the Risc processor visibility to the input field sync signal. If this bit does not match what the Risc processor field status is, then the PI is not synced properly. Field Hold status. If the PI is not synced properly (mismatch between the input FSYNC and the Risc processors' field status bit), field data will be held off and this status bit asserted. The PI will output a black field instead of the data. Once syncing occurs, the PI will allow data to be output and this bit will be turned off. Field Status. In encode mode, this status bit indicates the field status at the PI. In decode mode, this status bit indicates the field status at the Risc processor. Pixel Interface Field Interrupt. This interrupt bit is asserted when the PI sends a Field Interrupt to the Risc processor. Line count interrupt. This interrupt bit is activated when the line number programmed in the LINE_CNT_INTERRUPT register is reached. This interrupt has to be additionally enabled in the PMOD2 register. Field start reached and FIFO not full - Interrupt. This interrupt bit is set on a field rate basis in decode mode. It is asserted when the PI's internal counters have reached start of active video at the beginning of decoding a field and the PI FIFO is not full. Pixel FIFO full interrupt. This interrupt bit is asserted when the Pixel FIFO has reached full capacity.
1
PI_VSTRB
0x0
2
WT_VRDY
0x0
3
PI_RDY
0x0
4
FLD_SYNCED
0x0
5
FLD_HOLD
0x0
6
F_STATUS
0x0
7
F_IRQ
0x0
8
L_COUNT_IRQ
0x0
9
F_ST_FIFO_IRQ
0x0
10
FIFO_FULL_IRQ
0x0
Rev. PrT
32
19-Mar-2004
ADV202
Bits 11 Name
PRELIMINARY TECHNICAL DATA
Reset Value 0x0
Description Pixel Interface Video Field Error End - Interrupt. This interrupt bit is asserted if an erroneous field, for example an incomplete field, is passed from the WT to the Pixel Interface in decode mode. Pixel interface FIFO empty status. This status bit is asserted when the Pixel FIFO is empty. Pixel Interface Error Field Bit Interrupt. This interrupt bit is asserted when FLD_IRQ is not cleared by the Risc processor. Pixel Interface Time Code Interrupt. This interrupt bit is asserted when an erroneous EAV/SAV sequence is being received. Pixel FIFO full status. This status bit is asserted when the Pixel FIFO has reached its full capacity.
ERR_FLD_END_IRQ
12 13
FIFO_EMPTY ERR_FLD_BIT_IRQ
0x0 0x0
14
ERR_TC_IRQ
0x0
15
FIFO_FULL
0x0
0xFFFF0440
MS_CNT_DEL
RO
Reset Value 0x0
Bits 15:0
Name MS_CNT_DEL
Description This register is controlled by the ESF or firmware only. Used only in multi-chip sync mode. Refer to AppNote "ADV202 multi-chip application".
0xFFFF0444
LINE_CNT_INTERRUPT
R/W
Reset Value 0x0
Bits 15:0
Name LINE_CNT_IRQ
Description Line count interrupt. This register holds the line number value at which a line interrupt will be asserted. L_COUNT_INT_EN must be enabled.
0xFFFF0448
PMODE2
R/W
Bits 0 1
Name VCLK_POL VSYNC_POL
Description VCLK active edge VSYNC active edge 1=pos 0=neg 1=pos 0=neg
Reset Value 1 0
19-Mar-2004
33
Rev. PrT
PRELIMINARY TECHNICAL DATA
ADV202
Reset Value 1=pos 0=neg 1=pos 0=neg 1=on 0=off 0 0 0
Bits 2 3 4
Name HSYNC_POL FIELD_POL YUNI
Description HSYNC active edge FIELD active edge Y unipolar Unipolar defines a range from 0 to 255. When this bit is disabled the range is defined to be -127 to +127. C unipolar Unipolar defines a range from 0 to 255. When this bit is disabled the range is defined to be -127 to +127. Always write 0 Field interrupt enable Refer to F_INT in the PI_STATUS register for explanation. 1=on 0=off
5
CUNI
1=on 0=off
0
6 7
reserved F_IRQ_EN
0 0
8
L_COUNT_IRQ_EN
Line count interrupt enable 1=on 0=off This bit enables the line count interrupt according to the setting in the LINE_CNT_INTERRUPT register. Start of field reached and FIFO not full interrupt enable. Refer to F_ST_FIFO_IRQ in the PI_STATUS register for explanation. Enables the FIFO_FULL_IRQ interrupt bit in the PI_STATUS register. 1=on 0=off
0
9
F_ST_FIFO_IRQ_EN
0
10 11 12 13 14 15
FIFO_FULL_IRQ_EN ERR_FLD_END_IRQ _EN Reserved ERR_FLD_BIT_IRQ _EN ERR_TC_IRQ_EN Reserved
0 1=on 0=off 0 0 0 0 1=on 0=off 1=on 0=off 0
Enables the ERR_FLD_BIT_IRQ in the PI_STATUS register. Always write 0. Enables the ERR_FLD_BIT_IRQ in the PI_STATUS register. Enables the ERR_TC_IRQ in the PI_STATUS register. Always write 0
Rev. PrT
34
19-Mar-2004
PRELIMINARY TECHNICAL DATA
ADV202
0xFFFF044C
VMODE
Video mode
R/W
This register sets the video interface basic operating mode. Reset Value 0
Bits 0
Name MAS_SLV
Description MASTER=1; SLAVE=0 Master or Slave operation is only selectable in Decode mode. ENCODE=1; DECODE=0 Video input timing control. EAV/SAV mode = 0; for video input with embedded timing codes. HVF mode = 1; for video input with separate H,V,F sync signals.
1 2
ENC_DEC MP_656
0 0
3
DUAL_MODE
Extended mode. Used for any video input data that is more than 12-bit wide on the VDATA bus Video input over HDATA bus Raw video input on the VDATA bus HVF mode is not required to be set in this mode.
0 1=on 0=off 1=on 0=off 0 0 1=on 0=off
4 5
HOST_MODE RAW_MODE
6 7
Reserved PRGRSV_SCN
This register should not be written to. Progressive scan mode; Must be set if video input on the VDATA bus is non-interlaced, i.e 1field/frame. Always write 0. Always write 0. Always write 0.
0 0 1=on 0=off 0 0
8 9 10
Reserved Reserved Reserved
0 11 12:14 15 CNT_RD_EN Reserved PI_EN Read PI control counters [CO_CNT_STATUS and LINE_CNT_STATUS] Always write 0 Pixel interface enable Enables video input over the VDATA bus 1=on 0=off 0 1=on 0=off 0 0
Rev. PrT
35
19-Mar-2004
PRELIMINARY TECHNICAL DATA
8.4 Input formats programmable in PMODE1 register
ADV202
8.4.1 Input formats on HDATA bus [8/10 bit data] controlled by PFMT and PREC register settings
8-bit three component YCbYCr 4:2:2
msb(7) msb(7) msb(7) msb(7)
8-bit three component YYCbCr 4:2:2
msb(7) msb(7) msb(7) msb(7)
Yn Cbn Yn+1 Crn
repeat
lsb(0) lsb(0) lsb(0) lsb(0)
Yn Yn+1 Cbn Crn
repeat
lsb(0) lsb(0) lsb(0) lsb(0)
8-bit single component
msb(7)
8- bit two component CbCr
lsb(0) msb(7) msb(7)
Sn
repeat
Cbn Crn
repeat
lsb(0) lsb(0)
FIGURE 11. 8-bit input formats on HDATA bus
10-bit three component YCbYCr 4:2:2
msb(9) msb(9) msb(9) msb(9)
10-bit three component YYCbCr 4:2:2
msb(9) msb(9) msb(9) msb(9)
Yn Cbn Yn+1 Crn
repeat
lsb(0) lsb(0) lsb(0) lsb(0)
Yn Yn+1 Cbn Crn
repeat
lsb(0) lsb(0) lsb(0) lsb(0)
10-bit two component CbCr
msb(9) msb(9)
10-bit single component
lsb(0) lsb(0) msb(9)
Cbn Crn
repeat
Sn
repeat
lsb(0)
FIGURE 12. 10-bit input formats on HDATA bus
Rev. PrT
36
19-Mar-2004
PRELIMINARY TECHNICAL DATA
ADV202
8.4.2 Input formats on HDATA bus [12-/14-bit data] controlled by PFMT and PREC register settings
12-bit three component YCbYCr 4:2:2
msb(11) msb(11) msb(11) msb(11)
12-bit three component YYCbCr 4:2:2
msb(11) msb(11) msb(11) msb(11)
Yn Cbn Yn+1 Crn
repeat
lsb(0) lsb(0) lsb(0) lsb(0)
Yn Yn+1 Cbn Crn
repeat
lsb(0) lsb(0) lsb(0) lsb(0)
12-bit single component
msb(11)
12-bit two component CbCr 4:2:2
lsb(0) msb(11) msb(11)
Sn
repeat
Cbn Crn
repeat
lsb(0) lsb(0)
FIGURE 13. 12-bit input formats on HDATA bus
14-bit three component YCbYCr 4:2:2 Yn Cbn Yn+1 Crn
repeat
14-bit two component CbCr
msb(13) msb(13) msb(13) msb(13)
lsb(0) lsb(0) lsb(0) lsb(0)
msb(13) msb(13)
Cbn Crn
repeat
lsb(0) lsb(0)
14-bit three component YYCbCr 4:2:2
14-bit single component
msb(13) msb(13) msb(13) msb(13)
Yn Yn+1 Cbn Crn
repeat
lsb(0) lsb(0) lsb(0) lsb(0)
msb(13)
Sn
repeat
lsb(0)
FIGURE 14. 14-bit input formats on HDATA bus
Rev. PrT
37
19-Mar-2004
ADV202
PRELIMINARY TECHNICAL DATA
8.4.3 Input formats on HDATA bus [16-bit packed] controlled by PFMT and PREC register settings 2x8bit three component YCbYCr 4:2:2
msb(7) msb(7)
2x8bit two component CbCr
lsb(0) lsb(0) msb(7)
Yn Yn+1
lsb(0) msb(7) lsb(0) msb(7) repeat
Cbn Crn
Cbn
lsb(0) msb(7) repeat
Crn
lsb(0)
2x8bit three component YYCbCr 4:2:2
msb(7) msb(7)
16-bit two component CbCr
lsb(0) lsb(0) msb(15) msb(15)
Yn Cbn
lsb(0) msb(6) lsb(0) msb(6) repeat
Yn+1 Crn
Cbn Crn
repeat
lsb(0) lsb(0)
16-bit three component YCbYCr 4:2:2
msb(15) msb(15) msb(15) msb(15)
2x8bit single component
lsb(0) lsb(0) lsb(0) lsb(0) msb(7)
Yn Cbn Yn+1 Crn
repeat
Sn
lsb(0) msb(7) repeat
S n+1 lsb(0)
16-bit single component 16-bit three component YYCbCr 4:2:2
msb(15) msb(15) msb(15) msb(15) msb(15) lsb(0) lsb(0) lsb(0) lsb(0)
Sn
repeat
lsb(0)
Yn Yn+1 Cbn Crn
repeat
FIGURE 15. 8-bit/16-bit input formats on HDATA bus
19-Mar-2004
38
Rev. PrT
PRELIMINARY TECHNICAL DATA
ADV202
8.4.4 Input formats on VDATA bus [8-bit data] controlled by PFMT and PREC register settings
8-bit three component - CbYCrY - EAV/SAV Mode
msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7)
8-bit single component - EAV/SAV Mode
msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7)
0xFF 0x00 0x00 SAV Cbn Yn Crn Yn+1
repeat
lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
0xFF 0x00 0x00 SAV Sn Sn+1 Sn+2 Sn+3
repeat
lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
0xFF 0x00 0x00 EAV
0xFF 0x00 0x00 EAV
8-bit two component CbCr - EAV/SAV Mode
msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7)
8-bit three component CbYCrY- HVF Mode
msb(7) msb(7) msb(7) msb(7)
0xFF 0x00 0x00 SAV Cbn Crn Cbn+1 Crn+1
repeat
lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 msb(7) msb(7) msb(7) msb(7)
Cbn Yn Crn Yn+1
repeat
lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
8-bit two component CbCr - HVF Mode Cbn Crn Cbn+1
Crn+1 repeat lsb(0) [3:0] 0x00 [3:0] 0x00 lsb(0) [3:0] 0x00
0xFF 0x00 0x00 EAV
lsb(0) [3:0] 0x00
lsb(0) [3:0] 0x00
8-bit single component - HVF Mode
msb(7)
8-bit single component - Raw Mode
[3:0] 0x00 msb(7)
Sn
repeat
lsb(0)
Sn
repeat
lsb(0)
[3:0] 0x00
FIGURE 16. 8-bit input formats on VDATA bus
Rev. PrT
39
19-Mar-2004
ADV202
PRELIMINARY TECHNICAL DATA
8.4.5 Input formats on VDATA bus [10-bit data] controlled by PFMT and PREC register settings 10-bit three component - CbYCrY - EAV/SAV Mode
msb(7) msb(7) msb(7) msb(7) msb(9) msb(9) msb(9) msb(9) msb(7) msb(7) msb(7) msb(7)
10-bit single component - EAV/SAV Mode
msb(7) msb(7) msb(7) msb(7) msb(9) msb(9) msb(9) msb(9) msb(7) msb(7) msb(7) msb(7)
0xFF 0x00 0x00 SAV Cbn Yn Crn Yn+1
repeat
lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [1:0] 0x00 [1:0] 0x00 [1:0] 0x00 [1:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
0xFF 0x00 0x00 SAV Sn Sn+1 Sn+2 Sn+3
repeat
lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [1:0] 0x00 [1:0] 0x00 [1:0] 0x00 [1:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
0xFF 0x00 0x00 EAV
0xFF 0x00 0x00 EAV
10-bit two component CbCr - EAV/SAV Mode
msb(7) msb(7) msb(7) msb(7) msb(9) msb(9) msb(9) msb(9) msb(7) msb(7) msb(7) msb(7)
10-bit three component CbYCrY- HVF Mode
msb(9) msb(9) msb(9) msb(9)
0xFF 0x00 0x00 SAV Cbn Crn Cbn+1 Crn+1
repeat
lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [1:0] 0x00 [1:0] 0x00 [1:0] 0x00 1:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
Cbn Yn Crn Yn+1
repeat
lsb(0) lsb(0) lsb(0) lsb(0)
[1:0] 0x00 [1:0] 0x00 [1:0] 0x00 [1:0] 0x00
10-bit two component CbCr - HVF Mode
msb(9) msb(9) msb(9) msb(9)
0xFF 0x00 0x00 EAV
Cbn Crn Cbn+1
Crn+1 repeat
lsb(0) lsb(0) lsb(0)
[1:0] 0x00 [1:0] 0x00 [1:0] 0x00 [1:0] 0x00
10-bit single component - HVF Mode
msb(9)
10-bit single component - Raw Mode
msb(9)
Sn
repeat
lsb(0)
[1:0] 0x00
Sn
repeat
lsb(0)
[1:0] 0x00
FIGURE 17. 10-bit input formats on VDATA bus
19-Mar-2004
40
Rev. PrT
PRELIMINARY TECHNICAL DATA
ADV202
8.4.6 Input formats on VDATA bus [12/16-bit data] controlled by PFMT and PREC register settings 12-bit three component - CbYCrY - EAV/SAV Mode
msb(7) msb(7) msb(7) msb(7) msb(11) msb(11) msb(11) msb(11) msb(7) msb(7) msb(7) msb(7)
12-bit single component - EAV/SAV Mode
msb(7) msb(7) msb(7) msb(7) msb(11) msb(11) msb(11) msb(11) msb(7) msb(7) msb(7) msb(7)
0xFF 0x00 0x00 SAV Cbn Yn Crn Yn+1
repeat
lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 lsb(0) lsb(0) lsb(0) lsb(0)
0xFF 0x00 0x00 SAV Sn
Sn+1
lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 lsb(0) lsb(0) lsb(0) lsb(0)
Sn+2 Sn+3
repeat
0xFF 0x00 0x00 EAV
lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
0xFF 0x00 0x00 EAV
lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
12-bit two component CbCr - EAV/SAV Mode
msb(7) msb(7) msb(7) msb(7) msb(11) msb(11) msb(11) msb(11) msb(7) msb(7) msb(7) msb(7)
12-bit three component CbYCrY- HVF Mode
msb(11) msb(11) msb(11) msb(11)
0xFF 0x00 0x00 SAV Cbn Crn Cbn+1 Crn+1
repeat
lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 lsb(0) lsb(0) lsb(0) lsb(0)
Cbn Yn Crn Yn+1
repeat
lsb(0) lsb(0) lsb(0) lsb(0)
12-bit two component CbCr - HVF Mode
msb(11)
0xFF 0x00 0x00 EAV
lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
msb(11) msb(11) msb(11)
Cbn Crn Cbn+1 Crn+1
repeat
lsb(0) lsb(0) lsb(0) lsb(0)
12-bit single component - HVF Mode
msb(11)
12-bit single component - Raw Mode
lsb(0) msb(11)
Sn
repeat
Sn
repeat
lsb(0)
16-bit single component - HVF Mode set PFMT to 0x4h, PREC to 0x04h
msb(15)
16-bit single component - Raw Mode set PFMT to 0x0Ch, PREC to 0x04h
lsb(0) msb(15)
Sn
repeat
Sn
repeat
lsb(0)
FIGURE 18. 12/16-bit input formats on VDATA bus
Rev. PrT
41
19-Mar-2004
ADV202
PRELIMINARY TECHNICAL DATA
8.4.7 Input formats on VDATA bus [extended mode] controlled by PFMT and PREC register settings 8-bit three component CbYCrY - Extended Mode
msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7)
0xFF 0x00 0x00 SAV Cbn Crn
repeat
lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00
msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7)
lsb(0) [3:0] 0x00 lsb(0) [3:0] 0x00 lsb(0) lsb(0) lsb(0) lsb(0) [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
0xFF 0x00 0x00 SAV Yn Yn+1
repeat
lsb(0) [3:0] 0x00 lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
0xFF 0x00 0x00 EAV
lsb(0) [3:0] 0x00
0xFF 0x00 0x00 EAV
lsb(0) [3:0] 0x00 lsb(0) lsb(0) lsb(0) [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
8-bit two component CbCr - Extended Mode
msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7)
0xFF 0x00 0x00 SAV Cbn Cbn+1
repeat
lsb(0) lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7)
0xFF 0x00 0x00 SAV Crn Crn+1
repeat
lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
0xFF 0x00 0x00 EAV
lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
0xFF 0x00 0x00 EAV
8-bit single component - Extended Mode
msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7)
0xFF 0x00 0x00 SAV Sn Sn+2
repeat
lsb(0)
[3:0] 0x00
msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7) msb(7)
lsb(0) [3:0] 0x00 lsb(0) [3:0] 0x00 lsb(0) lsb(0) lsb(0) lsb(0) [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
0xFF 0x00 0x00 SAV Sn+1 Sn+3
repeat
lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
0xFF 0x00 0x00 EAV
lsb(0) [3:0] 0x00 lsb(0) [3:0] 0x00 lsb(0) [3:0] 0x00
0xFF 0x00 0x00 EAV
FIGURE 19. 8-bit extended input formats on VDATA bus
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PRELIMINARY TECHNICAL DATA
ADV202
8.4.8 Input formats on VDATA bus [extended mode] controlled by PFMT and PREC register settings
10-bit three component CbYCrY- Extended Mode
msb(7) msb(7) msb(7) msb(7) msb(9) msb(9) msb(7) msb(7) msb(7) msb(7)
0xFF 0x00 0x00 SAV Cbn Crn
repeat
lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [1:0] 0x00 [1:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
msb(7) msb(7) msb(7) msb(7) msb(9) msb(9) msb(7) msb(7) msb(7) msb(7)
0xFF 0x00 0x00 SAV Yn Yn+1
repeat
lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [1:0] 0x00 [1:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
0xFF 0x00 0x00 EAV
0xFF 0x00 0x00 EAV
10-bit two component CbCr- Extended Mode
msb(7) msb(7) msb(7) msb(7) msb(9) msb(9) msb(7) msb(7) msb(7) msb(7)
0xFF 0x00 0x00 SAV Cbn Cbn+1
repeat
lsb(0) [3:0] 0x00 lsb(0) lsb(0) lsb(0) lsb(0) [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [1:0] 0x00 [1:0] 0x00 lsb(0) [3:0] 0x00 lsb(0) lsb(0) lsb(0) [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
msb(7) msb(7) msb(7) msb(7) msb(9) msb(9) msb(7) msb(7) msb(7) msb(7)
0xFF 0x00 0x00 SAV
Crn Crn+1 repeat
lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [1:0] 0x00 [1:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
0xFF 0x00 0x00 EAV
0xFF 0x00 0x00 EAV
10-bit single component - Extended Mode
msb(7) msb(7) msb(7) msb(7) msb(9) msb(9) msb(7) msb(7) msb(7) msb(7)
0xFF 0x00 0x00 SAV Sn Sn+2
repeat
lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [1:0] 0x00 [1:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
msb(7) msb(7) msb(7) msb(7) msb(9) msb(9) msb(7) msb(7) msb(7) msb(7)
0xFF 0x00 0x00 SAV Sn+1 Sn+3
repeat
lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [1:0] 0x00 [1:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
0xFF 0x00 0x00 EAV
0xFF 0x00 0x00 EAV
FIGURE 20. 10-bit extended input formats on VDATA bus
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ADV202
PRELIMINARY TECHNICAL DATA
8.4.9 Input formats on VDATA bus [extended mode] controlled by PFMT and PREC register settings 12-bit three component CbYCrY - Extended Mode
msb(7) msb(7) msb(7) msb(7) msb(11) msb(11) msb(7) msb(7) msb(7) msb(7)
0xFF 0x00 0x00 SAV Cbn Crn
repeat
lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 lsb(0) lsb(0)
msb(7) msb(7) msb(7) msb(11) msb(11) msb(7) msb(7) msb(7) msb(7)
0xFF 0x00 SAV Yn Yn+1
repeat
lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 lsb(0) lsb(0)
0xFF 0x00 0x00 EAV
lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
0xFF 0x00 0x00 EAV
lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
12-bit two component CbCr - Extended Mode
msb(7) msb(7) msb(7) msb(7) msb(11) msb(11) msb(7) msb(7) msb(7) msb(7)
0xFF 0x00 0x00 SAV Cbn Cbn+1
repeat
lsb(0) [3:0] 0x00 lsb(0) lsb(0) lsb(0) [3:0] 0x00 [3:0] 0x00 [3:0] 0x00 lsb(0) lsb(0) lsb(0) [3:0] 0x00 lsb(0) lsb(0) lsb(0) [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
msb(7) msb(7) msb(7) msb(11) msb(11) msb(7) msb(7) msb(7) msb(7)
0xFF 0x00 SAV Crn Crn+1
repeat
lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 lsb(0) lsb(0)
0xFF 0x00 0x00 EAV
0xFF 0x00 0x00 EAV
lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
12-bit one component- Extended Mode
msb(7) msb(7) msb(7) msb(7) msb(11) msb(11) msb(7) msb(7) msb(7) msb(7)
0xFF 0x00 0x00 SAV Sn Sn+2
repeat
lsb(0) [3:0] 0x00 lsb(0) [3:0] 0x00 lsb(0) [3:0] 0x00 lsb(0) [3:0] 0x00 lsb(0) lsb(0) lsb(0) [3:0] 0x00 lsb(0) [3:0] 0x00 lsb(0) [3:0] 0x00 lsb(0) [3:0] 0x00
msb(7) msb(7) msb(7) msb(11) msb(11) msb(7) msb(7) msb(7) msb(7)
0xFF 0x00 SAV Sn+1 Sn+3
repeat
lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 lsb(0) lsb(0)
0xFF 0x00 0x00 EAV
0xFF 0x00 0x00 EAV
lsb(0) lsb(0) lsb(0) lsb(0)
[3:0] 0x00 [3:0] 0x00 [3:0] 0x00 [3:0] 0x00
FIGURE 21. 12-bit extended input formats on VDATA bus
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PRELIMINARY TECHNICAL DATA
8.4.10 Input Pin Configurations for Pixel/Video input on HDATA or VDATA bus
ADV202
Table 4: Input pin configuration on VDATA bus DATA FORMAT Video PIN CONFIGURATION [MSB]...LSB] PIN CONFIGURATION [MSB]...[LSB] VDATA[11]...[4] VDATA[11]...[2] VDATA[11]...[0] VDATA[23]...[16] Sn, Cbn, Crn... Cbn, Cbn+1... 20-bit Extended VDATA[23]...[14] Sn Cbn, Crn... Cbn, Cbn+1... 24-bit Extended VDATA[23]...[12] Sn, Sn+2... Cbn, Crn... Cbn, Cbn+1... Pixel 8-bit 10-bit 12-bit 16-bit Raw Raw Raw Raw VDATA[11]...[4] Sn+1 Yn, Yn+1... Crn, Crn+1... VDATA[11]...[2] Sn+1 Yn, Yn+1... Crn, Crn+1... VDATA[11]...[0] Sn+1, Sn+3... Yn, Yn+1... Crn, Crn+1... VDATA[15]...[8] VDATA[15]...[6] VDATA[15]...[4] VDATA[15]...[0] 1 component 3 component 2 component 1 component 3 component 2 component 1 component 3 component 2 component I/P FORMAT
FORMAT 8-bit 10-bit 12-bit 16-bit
VMODE EAV/SAV EAV/SAV HVF Extended
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PRELIMINARY TECHNICAL DATA
Table 5: Input pin configuration on HDATA bus - 8-bit data DATA FOR -MAT Pixel PIN CONFIG. [MSB]...[LSB] HDATA [31]...[24] Sn Cbn Yn, Yn+2... Yn, Yn+2... PIN CONFIG. [MSB]...[LSB] HDATA [23]...[16] Sn+1. Crn Yn+1, Yn+3. Cbn, Cbn+1. PIN CONFIG. [MSB]...[LSB] HDATA [15]...[8] Sn+2 Cbn+1 Cbn, Cbn+1. Yn+1, Yn+3. PIN CONFIG. [MSB...[LSB] HDATA [7]...[0] Sn+3 Crn+1 Crn, Crn+1... Crn, Crn+1... 1 component 2 component 3 component 3 component
FORMAT 8-bit
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PRELIMINARY TECHNICAL DATA
ADV202
Table 6: Input pin configuration on HDATA bus - 10, 12, 14, 16-bit data DATA FOR -MAT Pixel PIN CONFIG. [MSB]...[LSB] HDATA [31]...[22] Sn Cbn, Cbn+1 Yn, Yn+1... Yn, Cbn Pixel 12-bit HDATA [31]...[20] Sn Cbn, Cbn+1 Yn, Yn+1... Yn, Cbn Pixel 14-bit HDATA [31]...[18] Sn Cbn, Cbn+1 Yn, Yn+1... Yn, Cbn Pixel 16-bit HDATA [31]...[16] Sn Cbn, Cbn+1 Yn, Yn+1... Yn, Cbn PIN CONFIG. [MSB]...[LSB] HDATA [15]...[6] Sn+1 Cr, Crn+1 Cbn, Crn Yn+1, Crn HDATA [15]...[4] Sn+1 Cr, Crn+1 Cbn, Crn Yn+1, Crn HDATA [15]...[2] Sn+1 Cr, Crn+1 Cbn, Crn Yn+1, Crn HDATA [15]...[0] Sn+1 Cr, Crn+1 Cbn, Crn Yn+1, Crn 1 component 2 component 3 component 3 component 1 component 2 component 3 component 3 component 1 component 2 component 3 component 3 component 1 component 2 component 3 component 3 component
FORMAT 10-bit
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ADV202
8.5.
PRELIMINARY TECHNICAL DATA
EXTERNAL DMA ACCESS
0xFFFF1408
EDMOD0
External DMA mode register 0
R/W
This register is used to configure external DMA channel 0 as to what data is assigned to channel 0 and which access pins are to be used. Reset Value 0
Bits 0
Name DMEN0
Description Enable external DMA channel 0 0 = disabled 1 = enabled DMA Channel 0 assignment 0 Pixel data 1 Compressed data/ Code-block data 2 Attribute data 3 Ancillary data. DMA Channel 0 mode 0 Dedicated Chip Select DMA mode 1 2 3 4 5 6 7 Single transfer DREQ/DACK DMA mode Burst transfer DREQ/DACK DMA mode JDATA mode reserved Single transfer Fly-by DMA mode Burst transfer Fly-by DMA mode reserved
2:1
DMSEL0
0
5:3
DMMOD0
0
8:6
DMBL0
DMA Channel 0 burst length [in number of accesses] 0 1 2 3 4 5 6 7 8 16 32 64 128 256 512 1024 not available for DWIDTH of 8-bit for DWIDTH of 8/16 or 32-bits for DWIDTH of 8/16 or 32-bits for DWIDTH of 8/16 or 32-bits for DWIDTH of 8/16 or 32-bits for DWIDTH of 8/16 or 32-bits for DWIDTH of 8/16-bit, for 32-bits not recommended for DWIDTH of 8-bit, for 16-bit not recommended, for 32-bits not available.
0
9 10 14:11
DR0POL DA0POL DR0PULS
DREQ0 / FSRQ0 / VALID polarity; 0=active low, 1=active high DACK0 / FCS0 / HOLD polarity; 0=active low, 1=active high DREQ0 pulse width [in Jclkcycles]. If DR0PULS==0, then DREQ0 will remain asserted until DACK0 and RD/ in read mode or WR/ in write mode are asserted. Reserved for future use. Always write 0.
0 0 1
15
Reserved
0
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0xFFFF140C EDMOD1
ADV202
R/W
External DMA mode register 1
This register is used to configure external DMA channel 1. Reset Value 0
Bits 0
Name DMEN1
Description Enable external DMA channel 1 0 = disabled 1 = enabled DMA Channel 1 assignment 0 Pixel data 1 Compressed data/ Code-block data 2 Attribute data 3 Ancillary data. DMA Channel 1 mode 0 Dedicated Chip Select DMA mode. 1 Single transfer DREQ/DACK DMA mode 2 Burst transfer DREQ/DACK DMA mode 3 reserved 4 reserved 5 Single transfer Fly-by DMA mode 6 Burst transfer Fly-by DMA mode 7 reserved DMA Channel 1 burst length [in number of accesses]: 0 1 2 3 4 5 6 7 8 16 32 64 128 256 512 1024 not available for DWIDTH of 8-bit for DWIDTH of 8/16 or 32-bits for DWIDTH of 8/16 or 32-bits for DWIDTH of 8/16 or 32-bits for DWIDTH of 8/16 or 32-bits for DWIDTH of 8/16 or 32-bits for DWIDTH of 8/16-bit, for 32-bits not recommended for DWIDTH of 8-bit, for 16-bit not recommended, for 32-bits not available. polarity; 0=active low, 1=active high polarity; 0=active low, 1=active high
2:1
DMSEL1
1
5:3
DMMOD1
0
7:6
DMBL1
0
9 10 14:11
DR1POL DA1POL DR1PULS
DREQ1 / FSRQ1 DACK1 / FCS1
0 0 1
DREQ1 pulse width [in Jclkcycles]. If DR1PULS==0, then DREQ1 will remain asserted until DACK1 and RD/ in read mode or WR/ in write mode are asserted. Reserved for future use. Always write 0.
15
Reserved
0
8.5.1 EDMOD REGISTERS EDMOD0 and EDMOD1 are used to configure the ADV202 for external DMA operation. DMA allows transfers from/to memory without the on-board processor being required to perform the transactions as it is the case in Normal Host mode. The external DMA registers include settings for Single/Burst DMA, Fly-By Mode DMA, and Dedicated Chip Select (DCS) DMA. These registers are used in conjunction with the Bus Mode (BUSMODE) and
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ADV202
PRELIMINARY TECHNICAL DATA
FIFO Mode (FFMODE) registers. 8.5.2 EXTERNAL DMA DATA WIDTH The desired data width when accessing data FIFOs is set in the BUSMODE register. The DWIDTH field in this register (direct address 0x8) can be programmed to byte, half-word (16-bit), or word (32-bit) data widths. The default data-width is half-word (16-bit). 8.5.3 FIFO MODE CONFIGURATION The FIFO mode configuration register (FFMODE) must be programmed before using External DMA. This register sets the FIFO depths and data direction for the Code, Attribute, and Ancillary FIFOs. The FFCFG field is used to configure the FIFO depths. The CINP/AINP/NINP bits are used to set the Code/Attribute/Ancillary FIFOs to data input. The register encodings are listed in the FFMODE description under the CONFIGURABLE FIFO BLOCK section. Writing to the FFMODE register automatically resets the CODE, ATTR, ANC FIFOs. For details on the Pixel FIFO refer to the CONFIGURABLE PARAMETERS FOR THE PIXEL INTERFACE section.The depth of the Pixel FIFO is fixed at 256 words. 8.5.4 DMA MODES 8.5.4.1 DREQ/DACK DMA Mode and FLY-BY DMA Mode These registers are used to enable the External DMA interface, assign the desired FIFO toeach channel, and select modes of operation. All EDMA modes make use of the Data Request (DREQ0/DREQ1) and Data Acknowledge (DACK0/DACK1) pins. DREQ/DACK DMA mode and Fly-By DMA mode can be used in single transfer or burst transfer modes. 8.5.4.2 Dedicated Chip Select DMA Mode This mode is available for devices which monitor the FSRQx (DREQx) pins statically (as opposed to pulse detection). The FSRQx (DREQx) pins will be asserted when data/space is available in the selected FIFO and will be de-asserted when the FIFO is empty/full. The FCSx (DACKx) pins are used as FIFO Chip Select signals and should be asserted in conjunction with the RD/WE pins. This mode is enabled via the EDMODE0/EDMOD1 registers. The FSRQx/ polarity can be programmed to be active low or active high in the EDMOD0 register.1 8.5.5 JDATA JDATA MODE This mode allows input/output of compressed data using the VALID/HOLD protocol and the JDATA[7:0] pins. Please note that 32-bit data/host modes and the Extended Pixel Interface are not available when JDATA mode is enabled. To assign HDATA [31:24] pins to JDATA[7:0], the BUSMODE register must first be programmed to JDATA. The polarity of the VALID (DREQ0 pin) and HOLD (DACK0 pin) is set in the EDMOD0 register through bits DR0POL/DA0POL. The DMSEL0 field in EDMOD0 must be set to "1" (Compressed Data). The DMMOD0 field must be set to "3" (JDATA Mode). It is recommended that the user set up all mode bits in EDMOD0 without enabling the interface (DMEN0). Then, the HOLD pin should be asserted (depending on the polarity selected), and then de asserted after the JDATA interface has been enabled by either the Host or the ADV202. Data transfers occur when the ADV202 asserts VALID and the external device de-asserts HOLD.
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PRELIMINARY TECHNICAL DATA
ADV202
The VALID signal will always function as an output from the ADV202 and the HOLD signal will always function as an input to the ADV202. Data transfers occur when VALID is asserted and HOLD is de-asserted at the rising edge of MCLK. JDATA is referenced with MCLK and requires a PLL_MULT setting of >= 4. 8.5.6. SINGLE TRANSFER/ BURST TRANSFER AND BURST LENGTH Single Transfer DREQ/DACK DMA In this mode, the ADV202 will assert DREQx when there is at least one data transfer available for the programmed FIFO. If the FIFO is set to output, the DREQx assertion indicates that output data is present in the FIFO. When set to input, this indicates that space is available in the FIFO for at least one data transfer. The external device must respond with DACKx, in conjunction with RD/WE/HDATA activity. In Single Transfer Fly-By Mode, the functionality of the RD and WE pins is reversed. Burst Transfer DREQ/DACK DMA This mode is similar to Single Transfer EDMA, but each DREQx assertion indicates that the programmed number of accesses of the width selected are available for transfer. The number of accesses per burst is set in the Burst Length (DMBL0/DMBL1) fields in the EDMOD0/EDMOD1 registers. The access data width is set by the BUSMODE/DWIDTH field, as previously described. In Burst Transfer Fly-By Mode, the functionality of the RD and WE pins is reversed. Burst Length The Burst Length settings must be programmed in conjunction with the FIFO depths setting in the FFMODE/FFCFG field. Note that the FIFO depths refer to 32-bit words, but the Burst Lengths correspond to the number of accesses (which may be 8/16/32 bits wide). A given FIFO depth can support the same number of word transfers, twice the number of half-word transfers, and four times the number of byte transfers. For example, if the Attribute FIFO is set to a depth of 64, Burst Length (EDMODx/DMBLx) can be programmed to up to 64 word transfers, 128 half-word transfers, or 256 byte transfers. For highest throughput, it is recommended that the Burst Length is set to a value which is less than the FIFO depth. This will allow the ADV202 to transfer data internally while the external device simultaneously accesses thesame FIFO through the EDMA interface. If the CODE FIFO does not contain the programmed number of accesses [i.e. words] for the last portion of the compressed field, the FIFO is packed with 0s to ensure that the field ends on a burst boundary.
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PRELIMINARY TECHNICAL DATA
8.6. CONFIGURABLE FIFO BLOCK
For details on how to use FIFO access refer to the External DMA section in this data sheet.
ADV202
0xFFFF1418
FFMODE
Configurable FIFO mode register
R/W
This register is used to configure the FIFO for the CODE, ATTR and ANCIL data channels. Writing to this register will reset all data FIFOs. The PIXEL FIFO has always a size of 256 words. Reset Value 4
Bits 3:0
Name FFCFG
Description Enables and sets the sizes of the FIFOs associated with the CODE, ATTR and ANCL data channels. The maximum data width of these FI FOs is 32-bits. FFCFG 0 1 2 3 4 15-5 CODE 256 256 384 384 512 Reserved ATTR 256 128 128 64 N/A ANCL N/A 128 N/A 64 N/A
4 5 6 15:7
CINP AINP NINP reserved
Sets the CODE data FIFO as an input channel. Sets the ATTR data FIFO as an input channel. Sets the ANCL data FIFO as an input channel. Reserved for future use, always write 0
0 0 0 undef
0xFFFF1410
FFTHRP
FIFO Threshold for PIXEL FIFO
R/W
Sets the threshold detect level for the PIXEL data channel. This value is compared with the empty/full count of the FIFO and is used to set interrupt conditions. If the ADV202 is used in Dedicated Chip Select mode the setting of this register will set the interrupt conditions and will drive the FSRQx/ signal.1 If the FIFO is in input mode then the threshold condition will be true whenever the empty count is greater than, or equal to, the threshold value. If the FIFO is in output mode then the threshold condition will be true whenever the full count is greater than, or equal to, the threshold value. The threshold count is in units of 32-bit words. Reset Value 0
Bits 15:0
Name THRP
Description Set the threshold level for PIXEL data FIFO.
0xFFFF141C
FFTHRC
FIFO Threshold for CODE FIFO
R/W
Sets the threshold detect level for the CODE data channel. This value is compared with the empty/full count of the FIFO and is used to set interrupt conditions. If the ADV202 is used in Dedicated Chip Select mode the setting of this register will set the interrupt conditions and will drive the FSRQx/ signal.1
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ADV202
PRELIMINARY TECHNICAL DATA
If the FIFO is in input mode then the threshold condition will be true whenever the empty count is greater than, or equal to, the threshold value. If the FIFO is in output mode then the threshold condition will be true whenever the full count is greater than, or equal to, the threshold value. The threshold count is in units of 32-bit words. Writing to this register will reset all data FIFOs.
Bits 15:0
Name THRC
Description Set the threshold level for CODE data FIFO.
Reset Value 0
0xFFFF1420
FFTHRA
FIFO Threshold for ATTR FIFO
R/W
Sets the threshold detect level for the ATTR data channel. This value is compared with the empty/full count of the FIFO and is used to set interrupt conditions. If the ADV202 is used in Dedicated Chip Select mode the setting of this register will set the interrupt conditions and will drive the FSRQx/ signal.1 If the FIFO is in input mode then the threshold condition will be true whenever the empty count is greater than, or equal to, the threshold value. If the FIFO is in output mode then the threshold condition will be true whenever the full count is greater than, or equal to, the threshold value.The threshold count is in units of 32-bit words. Writing to this register will reset all data FIFOs. Reset Value 0
Bits 15:0
Name THRA
Description Set the threshold level for ATTR data FIFO.
0xFFFF1424
FFTHRN
FIFO Threshold for ANCL FIFO
R/W
Sets the threshold detect level for the ANCL data channel. This value is compared with the empty/full count of the FIFO and is used to set interrupt conditions. If the ADV202 is used in Dedicated Chip Select mode the setting of this register will set the interrupt conditions and will drive the FSRQx/ signal.1 If the FIFO is in input mode then the threshold condition will be true whenever the empty count is greater than, or equal to, the threshold value. If the FIFO is in output mode then the threshold condition will be true whenever the full count is greater than, or equal to, the threshold value.The threshold count is in units of 32-bit words. Writing to this register will reset all data FIFOs.
Bits 15:0
Name THRN
Description Set the threshold level for ANCL data FIFO
Reset Value 0
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PRELIMINARY TECHNICAL DATA
0xFFFF1414 FFCNTP FIFO Full/Empty count for PIXEL FIFO
ADV202
RO
Returns the full/empty count of the PIXEL FIFO. If the FIFO is in input mode then this register will return the number of empty locations in the FIFO. If the FIFO is in output mode then this register will return the number of locations in the FIFO that contain valid data.The threshold count is in units of 32-bit words Reset Value ** undef
Bits 8:0 15:9
Name CNTP reserved
Description Full/Empty count for the PIXEL FIFO. **Reset value depends on mode Reserved for future use.
0xFFFF1428
FFCNTC
FIFO Full/Empty count for CODE FIFO
RO
Returns the full/empty count of the CODE FIFO. If the FIFO is in input mode then this register will return the number of empty locations in the FIFO. If the FIFO is in output mode then this register will return the number of locations in the FIFO that contain valid data.The threshold count is in units of 32-bit words Reset Value ** undef
Bits 9:0 15:10
Name CNTC reserved
Description Full/Empty count for the CODE FIFO. **Reset value depends on mode Reserved for future use.
0xFFFF142C
FFCNTA
FIFO Full/Empty count for ATTR FIFO
RO
Returns the full/empty count of the ATTR FIFO. If the FIFO is in input mode then this register will return the number of empty locations in the FIFO. If the FIFO is in output mode then this register will return the number of locations in the FIFO that contain valid data.The threshold count is in units of 32-bit words Reset Value ** undef
Bits 8:0 15:9
Name CNTA reserved
Description Full/Empty count for the ATTR FIFO. **Reset value depends on mode Reserved for future use,
0xFFFF1430
FFCNTN
FIFO Full/Empty count for ANCL FIFO
RO
Returns the empty/full count of the ANCL FIFO. If the FIFO is in input mode then this register will return the number of empty locations in the FIFO. If the FIFO is in output mode then this register will return the number of locations in the FIFO that contain valid data.The threshold count is in units of 32-bit words Reset Value ** undef
Bits 7:0 15:8
Name CNTN reserved
Description Full/Empty count for the ANCL FIFO. **Reset value depends on mode Reserved for future use,
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PRELIMINARY TECHNICAL DATA
9. START-UP CONFIGURATION
The "Getting Started..." Application Note contains detailed instructions how to program the ADV202 for specific applications, such as encode or decode for NTSC,1080i or custom specific format, and to run certain functionality tests. The following section contains a short overview only. Before configuring the ADV202 for specific applications it is recommended to verify the functionality of the ADV202 design in performing some basic functionality tests.
9.1. Verify Direct Register access functionality Direct Register access is achieved with Normal Host accesses, interfacing the ADV202 over: - ADDR<3:0> - CS/ - WE/ - RD/ - ACK/ - HDATA <31:0> or <15:0> All direct registers should be accessible regardless of which boot mode is use [except boot modes 0 and 1]. A hard reset [BOOT mode register] over several cycles is required before Direct Register access. A hard reset is applied in holding the RESET/ pin low. Until the ADV202 asserts ACK/, the host must hold the state of the ADDR<3:0>, CS/, WE/, RD/ and HDATA pins. Direct register access is not completed until after ACK/ is asserted. This only applies to Normal Host access read operations and is not required for any DMA modes. 9.2. Indirect Register access functionality The general procedure is to: 1. Configure the PLL registers PLL_HI and PLL_LO and wait for the PLL to lock. 2. Initiate a re-boot [No-Boot-Host mode] by writing to the BOOT mode register. 3. Configure the BUSMODE register to configure the HDATA bus. 4. Configure the MMODE register for indirect register access. 5. For 16-bit hosts, configure the STAGE register. 6. Set start address for the data values in writing to IADDR. 7. Load test data to memory in writing the IDATA. 8. Read test values back from their indirect register location.
9.3. Load and run a specific application for 32-bit host application 1. Configure the PLL registers PLL_HI and PLL_LO and wait for the PLL to lock. 2. Initiate a re-boot [No-Boot-Host mode] in writing to the BOOT mode register. 3. Configure the BUSMODE register to configure the HDATA bus. 4. Configure the MMODE register for indirect register access. 5. For 16-bit hosts, configure the STAGE register. 6. Set start address for the program in writing to IADDR.
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ADV202
7. Load program into memory in writing the program data to IDATA. 8. Initiate a re-boot [Co-Processor mode] to start the program. 9. Configure the BUSMODE register to configure the HDATA bus again. 10. Configure the MMODE register for indirect register access. 11. Load program specific parameters in writing to IADDR and IDATA. 12. Unmask the SWIRQ0 bit in the EIRQIE register and wait for the ADV202 to assert an interrupt. 13. Configure DMA channels 0 and 1 in the EDMOD0 and EDMOD1 registers using indirect register access. 14. Clear the SWIRQ0 bit in the EIRQFLG register and start the data flow process.
10. ESF and ADV202 firmware
The ADV202 is a System-on-Chip (SOC) implementation, which means that it incorporates dedicated hardware functions, a processor and on-board firmware/software. It also means that configuring and managing the operations of the chip can be handled by the on-chip processor and its software. Other than basic bus and I/O configuration which the user has to set up [see previous chapter], most of the configuration and control of the ADV202 is handled by the firmware. The firmware is responsible of setting other registers in different functional blocks of the ADV202, scheduling events etc. The user has no access to these functional blocks, they are entirely controlled by the firmware or ESF. There are two methods to operate the ADV202: 1. Load specific firmware to the ADV202 as described in the previous chapter. 2. Embedded Software Framework. The Embedded Software Framework resides in the on-chip ROM and contains all necessary support for all functions which might be performed by the software interface. It is controlled with a high-level command protocol, which simplifies processing. It supports plug-in updates loading which allows to keep up with up-to-date software features without the requirement to replace the ADV202 with a newer ROM-version ADV202. ESF will be available on the released version of the ADV202.
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11. APPLICATIONS
PRELIMINARY TECHNICAL DATA
11.1. Encode/decode in multi-chip applications Due to the data input rate limitation [ref. to tables 1 and 2] an 1080i application will require at least 2 ADV202s to encode or decode full resolution 1080i video. In encode mode the ADV202 accepts Y and CbCr data on separate buses. The input data must be in EAV/ SAV format. In decode mode a master/slave configuration, as shown in the figure below, or a slave/slave configuration can be used in order to synchronize the outputs of the two ADV202s. Refer to the technical note "ADV202 multi-chip application" for more detail on how to configure the ADV202s in a multi-chip application. This data sheet contains a brief outline of this procedure. Applications that have the two separate VDATA outputs send to an FPGA or buffer before they are send to an encoder, for example, do not require synchronization at the ADV202 outputs.
Encode mode
32-BIT HOST CPU DATA[31:0] ADDR[3:0] CS/ RD/ WR/ ACK/ IRQ/ ADV202_1_Slave HDATA[31:0] ADDR[3:0] CS RD WE ACK IRQ MCLK VCLK LLC ADV7402 10- bit SD/HD VIDEO DECODER
Y
VDATA[11:2] DREQ/ DACK/ DREQ DACK Y[9:0] C[9:0]
1080i Video In
CbCr
G I/O
SCOMM[5]
FIELD VSYNC HSYNC
ADV202_2_Slave HDATA[31:0] ADDR[3:0] CS/ RD/ WR/ ACK/ IRQ/ CS RD WE ACK IRQ HSYNC VSYNC FIELD VCLK
MCLK
DREQ/ DACK/
DREQ DACK VDATA[11:2]
CbCr
SCOMM[5]
Figure 22. ADV202 multi-chip application - Encode
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ADV202
In a master/slave configuration it is expected that the master HVF outputs are connected to the slave HVF inputs and that each SCOMM[5] pin is connected to the same GPIO on the host. In a slave /slave configuration the common HVF for both ADV202s is generated by an external house sync Decode Master/Slave configuration
32-BIT HOST CPU DATA[31:0] ADDR[3:0] CS/ RD/ WR/ ACK/ IRQ/
ADV202_1_Master HDATA[31:0] ADDR[3:0] CS RD WE ACK IRQ VDATA[11:2] DREQ DACK MCLK VCLK
74.25 MHz OSC
ADV730xA 10- bit SD/HD VIDEO ENCODER
CLKIN
Y
Y
Y[9:0] C[9:0]
DREQ/ DACK/
1080i Video Out
CbCr
G I/O
SCOMM[5]
FIELD VSYNC HSYNC
ADV202_2_Slave HDATA[31:0] ADDR[3:0] CS/ RD/ WR/ ACK/ IRQ/ CS RD WE ACK IRQ HSYNC VSYNC FIELD VCLK
MCLK
DREQ/ DACK/
DREQ DACK VDATA[11:2]
CbCr
SCOMM[5]
Figure 23. ADV202 multi-chip application in a decode master/slave configuration
and each SCOMM[5] is connected to the same GPIO output on the host. SWIRQ1, Software Interrupt 1 in the EIRQIE register must be unmasked on both devices to enable multi-chip mode. In a master/slave configuration the following must be considered also: Every slave ADV202 has a fixed timing delay form HSYNC/ active input to video data out. The necessary register to compensate for this delay is set via the firmware on the master ADV202. The value of this register is programmed into the 0xFFFF0440 register of the master device by the firmware when the part is configured in multi-sync mode [i.e. when SWIRQ1 is enabled].
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PRELIMINARY TECHNICAL DATA
11. 2. Digital Still Camera and Camcorder Applications
FPGA
ADV202 MCLK VCLK 16-BIT HOST CPU
AD9843A D[9:0]
10
Data Inputs [9:0]
VFRM VRDY VSTRB VDATA[11:2] HDATA[15:0] ADDR[3:0] CS
SDATA SCK SL
Serial Data Serial Clk Serial En
DATA[15:0] ADDR[3:0]
CS
RD WE ACK IRQ/
RD WE ACK IRQ/
Figure 24. ADV202 with pixel input for Digital Still Camera and Camcorder Applications
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PRELIMINARY TECHNICAL DATA
11.3 Encode/decode SDTV video
Encode mode
ADV202
ADV7189 10-BIT VIDEO DECODER Video In
VDATA[11:2] VCLK MCLK
P[19:10] LLC1
DATA[31:0]
HDATA[31:0]
INTR/ ADDR[3:0] CS RD 32-BIT HOST CPU WE ACK
IRQ/ ADDR[3:0] CS RD WE ACK
ADV7301A
Decode mode
ADV202 VDATA[11:2] VCLK MCLK
10-BIT VIDEO ENCODER
Video Out
P[9:0] CLKIN
DATA[31:0]
HDATA[31:0]
INTR/ ADDR[3:0] CS RD 32-BIT HOST CPU ACK WE
IRQ/ ADDR[3:0] CS RD WE ACK
27MHz OSC
Figure 25. ADV202 with 32-bit host interfaced and 10-bit CCIR656 video application [Normal host mode]
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PRELIMINARY TECHNICAL DATA
11.4 32-bit Host/ 32-bit ASIC application
ASIC
ADV7189 10-BIT VIDEO DECODER DREQ0 DACK0 DREQ0 DACK0 VDATA[11:2] VCLK HDATA[31:0] MCLK ADV202 P[19:10] LLC1 Video In
DATA[31:0]
DATA<31:0>
IRQ ADDR[3:0] CS 32-BIT HOST CPU RD WE ACK
IRQ ADDR[3:0] CS RD WE ACK
Encode mode
ASIC
ADV730xA 10-BIT VIDEO ENCODER DREQ0 DACK0 DREQ0 DACK0 VDATA[11:2] DATA[31:0] VCLK HDATA[31:0] MCLK P[9:0] CLKIN Video Out
DATA<31:0>
ADV202
IRQ ADDR[3:0] CS RD 31-BIT HOST CPU ACK WE
IRQ ADDR[3:0] CS RD WE ACK
27 MHz OSC
Decode mode
Figure 26. ADV202 with 32-bit host interfaced and 10-bit CCIR656 video application
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11.5 ADV202 in HIPI configuration [Host Interface Pixel Interface]
ADV202
32-bit Host
DATA<31:0>
Y0 Y0<6> Y0<5> Y0<4> Y0<3> Y0<2> Y0<1> Y0<0> Cb0 Cb0<6> Cb0<5> Cb0<4> Cb0<3> Cb0<2> Cb0<1> Cb0<0> Y1 Y1<6> Y1<5> Y1<4> Y1<3> Y1<2> Y1<1> Y1<0> Cr0 Cr0<6> Cr0<5> Cr0<4> Cr0<3> Cr0<2> Cr0<1> Cr0<0>
HDATA<31> HDATA<30> HDATA<29> HDATA<28> HDATA<27> HDATA<26> HDATA<25> HDATA<24> HDATA<23> HDATA<22> HDATA<21> HDATA<20> HDATA<19> HDATA<18> HDATA<17> HDATA<16> HDATA<15> HDATA<14> HDATA<13> HDATA<12> HDATA<11> HDATA<10> HDATA<9> HDATA<8> HDATA<7> HDATA<6> HDATA<5> HDATA<4> HDATA<3> HDATA<2> HDATA<1> HDATA<0>
ADV202
CS/ RD/ WR/ ACK/ IRQ/ DREQ/ DACK/ DREQ DACK/ 74.25MHz
CS/ RD/ WE/ ACK/ IRQ/ DREQ0/ DACK0/ DREQ1/ DACK1/ [Raw pixel data path] [Compressed data path]
MCLK
Figure 27. ADV202 in HIPI - Encode mode
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PRELIMINARY TECHNICAL DATA
11.6 ADV202 with JDATA interface
ADV202 YCrCb P[19:10] ADV7189 Video In
JDATA[7:0] HOLDO/ VALIDO/ ASIC
VDATA[11:2]
FIELD VSYNC HSYNC
FIELD VS HS
VCLK DATA[15:0] HDATA[15:0] MCLK
LLC1
IRQ ADDR[3:0] CS 16-BIT HOST CPU RD WE ACK
IRQ ADDR[3:0] CS RD WE ACK
Figure 28. ADV202 with 16-bit host, dedicated JDATA output and 10-bit CCIR656 input
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12. SPECIFICATONS
Specifications subject to change without notice. Table 14: Supply Voltage Symbol VDD IOVdd PLLVDD VInput Temp Parameter DC supply voltage, core DC supply voltage, I/O DC supply voltage, PLL Input range Operating ambient temperature range in free air Min 1.425 2.375 1.425 -0.3 -40 Typ 1.5 3.3 1.5
ADV202
Max 1.575 3.465 1.575 VddI/O + 0.3 +85
Unit V V V V
oC
Table 15: Input/Output Specifications Parameter VIH VIL VOH VOL IIH IIL IOZH IOZL IDD IDD CI CO Description Hi-Level Input Voltage Lo-Level Input Voltage Hi-Level Output Voltage Lo-Level Output Voltage Hi-Level Input Current Lo-Level Input Current Hi-Level Three-State Leakage Current Lo-Level Three-State Leakage Current Supply Current (Power Down) Supply Current (Active) Input Pin Capacitance Output Pin Capacitance Test Conditions VDD = max VDD = min VDD = min, IOH = -0.5mA VDD = min, IOL = 2mA VDD = max, VIN = VDD VDD = max, VIN = 0v VDD = max, VIN = VDD VDD = max, VIN = 0v VDD = max VDD = max Min 2.0 2.4 Typ 6 10 6 10 Max 0.8 0.4 100 100 8 8 Unit V V V V uA nA uA nA uA mA pF pF
Table 16: Input clocks and RESET/ Parameter tMCLK tMCLKL tMCLKH tVCLK tVCLKL Comments MCLK period MCLK Width Low MCLK Width High VCLK period VCLK Width Low Min 13.5 6.5 6.5 13.9 5.5 Typ Max 100.5 50.5 Unit nS nS nS nS nS
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Parameter tVCLKH tRST
PRELIMINARY TECHNICAL DATA
Comments VCLK Width High RESET Width Low Min 5 5 Typ Max Unit nS Mclk cycles*
* Refer to PLL section and figure 9 for definition of Mclk.
tMCLK tMCLKL MCLK tVCLK tVCLKL VCLK tVCLKH tMCLKH
FIGURE 29. Input Clocks
Table 17. Normal Host Mode - Read Operation [ internal registers only, does not apply to FIFO accesses] Parameter tACK tACK tDRD tDRD tHZRD tSC tSA tHC tHA tRH tRL tRCyc Comments RD to ACK [direct registers] RD to ACK [indirect registers] Read access time [direct registers] Read access time [indirect registers] Data hold CS to RD setup Address setup CS hold Address hold Read inactive pulse width Read active pulse width Read Cycle time [direct registers] Min 5.5ns 10.5xJclk + 5.5ns 5.5ns 10.5xJclk + 5.5ns 2 0 2.5 0 2.5 15.5 15.5 30.5 Typ Max 1.5xJclk + 5.5ns 15.5xJclk + 5.5ns 1.5xJclk + 5.5ns 15.5xJclk +5.5ns 8.5 nS nS nS nS nS nS nS nS Unit
* Refer to PLL section and figure 9 for definition of Jclk.
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ADV202
tSA ADDR tSC CS
tHA tHC tRCyc tRL tRH
RD tACK ACK HDATA tDRD valid tHZRD
FIGURE 30. Normal host mode - Read access
Table 18: Normal Host mode - write operation [internal registers only, does not apply to FIFO accesses] Parameter tACK[dir] tACK[ind] tSD tHD tSC tSA tHC tHA tWH tWL tWCyc Comments WE to ACK [direct registers] WE to ACK [indirect registers] Data setup Data hold CS to WE setup Address setup CS hold Address hold Write inactive pulse width [min. time until next WE/ pulse] Write active pulse width Write Cycle time Min 5.5ns 5.5ns 2.5 1.5 0 2.5 0 2.5 15.5* 15.5* 30.5* Typ Max 1.5xJclk + 5.5ns 2.5xJclk + 5.5ns nS nS nS nS nS nS nS nS nS Unit
* Specified for Jclk = 150MHz. Refer to PLL section for definition of Jclk.
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PRELIMINARY TECHNICAL DATA
tSA ADDR tSC CS
tHA tHC tWCyc tWL tWH
WE tACK ACK tHD HDATA tSD valid FIGURE 31. Normal host mode - Write Access Table 19: DREQ/DACK DMA mode - single FIFO write Parameter DREQpulse tDREQ tWEsu tSU tHD DACKlo DACKhi tWEhd WFSRQ TDREQrtn a. b. c. d. Comments DREQ pulse width
a
Min 1 2.5 0 2.5 2.5 8b 8c 0 1.5 2.5
Typ -
Max 15 3.5xJclk + 5.5ns 2.5xJclk + 5.5ns 3.5xJclk + 5.5ns
Unit Jclkcyclesd Jclkcyclesd ns ns ns ns ns ns Jclkcyclesd Jclkcyclesd
DACK assert to subsequent DREQ delay WE to DACK setup Data to DACK de-assert setup Data to DACK de-assert hold DACK assert pulse width DACK de-assert pulse width WE hold after DACK de-assert WE de-assert to FSRQ de-assert [FIFO full] WE to DREQ de-assert [DRxPULS=0]
Applies to assigned DMA channel if EDMOD0 or EDMOD1<14:11> is programmed to a value of 0. Assumes Jclk = 150MHz. Refer to PLL section for definition of Jclk. Assumes Jclk = 150MHz. Refer to PLL section for definition of Jclk. Refer to PLL section for definition of Jclk.
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ADV202
DREQpulse tDREQ DREQ DACKhi DACKlo DACK
tWEsu WE HDATA tSU 0 tHD 1 2
tWEhd
3
FIGURE 32. Single Write Cycle for DREQ/DACK DMA mode for assigned DMA channel EDMODx<14:11> NOT programmed to a value of 0.
tDREQ DREQ DACKhi DACKlo DACK
tWEsu WE HDATA tSU 0 tHD 1 2
tWEhd
3
FIGURE 33. Single Write Cycle for DREQ/DACK DMA mode for assigned DMA channel EDMODx<14:11> programmed to a value of 0.
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ADV202
PRELIMINARY TECHNICAL DATA
DREQpulse tDREQ DREQ* DACKhi DACKlo DACK
tWEsu RDFB HDATA tSU 0 tHD 1 2
tWEhd
FIGURE 34. Single Write Cycle in Fly_By DMA mode
* DREQ/ pulse width is programmable. Refer to Table 19 and figures 32 and 33.
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ADV202
FCS0 WE WFSRQ FIFO NOT FULL
FSRQ0
FIFO FULL
HDATA
0
1
2
Not written to FIFO
FIGURE 35. Single Write Cycle for DCS DMA mode This figure applies to ADV202 REV0.1 and upwards
FSC0
WE WFSRQ FSRQ0 FIFO NOT FULL FIFO FULL
HDATA
0
1
2
Not written to FIFO
FIGURE 36. Single Write Cycle for DCS DMA mode This figure applies to REV0.0 ADV202s
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ADV202
PRELIMINARY TECHNICAL DATA
Table 20 : DREQ/DACK DMA mode DMA - single FIFO read Parameter DREQpulse tDREQ tRDsu tRD tHD DACKlo DACKhi tRDhd RDFSRQ tDREQrtn Comments DREQ pulse width DACK assert to subsequent DREQ delay RD to DACK setup DACK to data valid Data hold DACK assert pulse width DACK de-assert pulse width RD hold after DACK de-assert RD assert to FSRQ de-assert [FIFO empty] RD to DREQ de-assert [DRxPULS=0] Min 1 2.5 0 2.5 1.5 8.0 8.0 0 2.0 3.0 Typ Max 15 3.5xJclk + 5.5ns 2.5xJclk + 5.5ns 3.5xJclk + 5.5ns Unit Jclkcyclesa Jclkcyclesa ns ns ns ns ns ns Jclkcycles Jclkcycles
a. Applies to assigned DMA channel if EDMOD0 or EDMOD1<14:11> is programmed to a value of 0. Refer to PLL section for definition of Jclk.
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ADV202
DREQpulse tDREQ DREQ DACKhi DACKlo DACK
tRDsu RD HDATA tRD 0 tHD 1 2
tRDhd
FIGURE 37. Single Read Cycle for DREQ/DACK DMA mode for assigned DMA channel EDMODx<14:11> NOT programmed to a value of 0.
tDREQ DREQ DACKhi DACKlo DACK
tRDsu RD HDATA tRD 0 tHD 1 2
tRDhd
FIGURE 38. Single Read Cycle for DREQ/DACK DMA mode for assigned DMA channel EDMODx<14:11>programmed to a value of 0.
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ADV202
PRELIMINARY TECHNICAL DATA
DREQpulse tDREQ DREQ* DACKhi DACKlo DACK
tWEsu WEFB HDATA tRD 0 tHD 1 2
tWEhd
* DREQ/ pulse width is programmable. Refer to table 20 and figures 37 and 38. FIGURE 39. Single Read cycle in Fly-By DMA mode
FCS0
RD RDFSRQ FIFO NOT EMPTY
FSRQ0
FIFO EMPTY
HDATA
0
1
FIGURE 40. Single Read cycle in DCS- DMA mode
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Table 21: External DMA - FIFO write - Burst mode Parameter DREQpulse tDREQrtn tDACKsu tSU tHD WElo WEhi tDREQwait Comments DREQ pulse widtha DACK to DREQ de-assert [DRxpulse=0] DACK to WE setup Data setup Data hold WE assert pulse width WE de-assert pulse width DACK de-assert to next DREQ Min 1 2.5 0 2.5 2.5 8.0 8.0 4.0 Typ Max 15 3.5 4.5
c
ADV202
Unit Jclkcyclesb Jclkcyclesb ns ns ns ns ns Jclkcyclesb
a. Applies to assigned DMA channel if EDMOD0 or EDMOD1<14:11> is programmed to a value of 0. b. Assumes Jclk = 150MHz. Refer to PLL section for definition of Jclk. c. If sufficient space is available in FIFO. DREQpulse DREQ DACK tDREQrtn tDREQwait
WE
tDACKsu tHD tSU 0 1
WElo
WEhi
HDATA
13
14
15
FIGURE 41. Burst Write Cycle for DREQ/DACK DMA mode for assigned DMA channel EDMODx<14:11> NOT programmed to a value of 0.
DREQ DACK
tDREQwait
WE
tDACKsu tHD tSU 0 1
WElo
WEhi
13
14
15
FIGURE 42. Burst write cycle for DREQ/DACK DMA mode for assigned DMA channel EDMODx <14:11> programmed to a value of 0.
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PRELIMINARY TECHNICAL DATA
tDREQrtn DREQ DACK
tDREQwait
tDACKsu RDFB tHD tSU HDATA 0 1
WElo
WEhi
13
14
15
* DREQ/ pulse width is programmable. Refer to table 21 and figures 41 and 42. FIGURE 43. Burst write cycles for Fly-by DMA mode
Table 22 : DREQ/DACK DMA mode - FIFO read - Burst mode Parameter DREQpulse tDREQrtn tDACKsu tRD tHD RDlo RDhi tDREQwait Comments DREQ pulse width
a
Min 1 2.5 0 2.5 2.5 8.0 8.0 2.5
Typ
Max 15
Unit* Jclkcyclesb Jclkcyclesb ns ns ns ns ns Jclkcycles
DACK to DREQ deassert [DRxPULS=0] DACK to WE setup DACK to Data valid Data hold RD assert pulse width RD de-assert pulse width DACK de-assert to next DREQ
-
3.5 3.5c
a. Applies to assigned DMA channel if EDMOD0 or EDMOD1<14:11> is programmed to a value of 0. b. Assumes Jclk = 150MHz. Refer to PLL section for definition of Jclk. c. If sufficient data is available in FIFO.
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DREQpulse tDREQrtn DREQ DACK
ADV202
tDREQwait
RD HDATA tRD 0 tHD 1 13 14 15
FIGURE 44. Burst Read Cycle for DREQ/DACK DMA mode for assigned DMA channel EDMODx<14:11> NOT programmed to a value of 0. tDREQwait DREQ DACK
RD HDATA tRD 0 tHD 1 13 14 15
FIGURE 45. Burst read cycle for DREQ/DACK DMA mode for assigned DMA channel EDMODx<14:11> programmed to a value of 0.
tDREQrtn DREQ* DACK
tDREQwait
WEFB HDATA tRD 0 tHD 1 13 14 15
* DREQ/ pulse width is programmable. Refer to table 22 and figures 41 and 42. FIGURE 46. Burst read cycle for Fly-by DMA mode
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ADV202
PRELIMINARY TECHNICAL DATA
Table 23: Streaming Mode [JDATA] - FIFO read/write Parameter JDATAtd VALIDtd HOLDsu HOLDhd JDATAsu JDATAhd Comments MCLK to JDATA valid MCLK to VALID assert/ de-assert HOLD setup to rising MCLK HOLD hold from rising MCLK JDATA setup to rising MCLK JDATA hold from rising MCLK Min 1.5 1.5 3.5 3.5 3.5 3.5 Typ Max 3.0 3.0 Unit Jclkcyclesa Jclkcyclesa ns ns ns ns
a. Refer to PLL section for definition of Jclk.
Encode Mode JDATA output MCLK JDATAtd JDATA VALIDtd VALID* HOLDsu HOLD* HOLDhd JDATAsu JDATAhd
Decode Mode JDATA input MCLK JDATAhd JDATAsu JDATA VALIDtd VALID* HOLDsu HOLD* * HOLD and VALID polarity is programmable in register EDMOD0. The figure above shows VALID and HOLD to be programmed to active high polarity. FIGURE 47 Streaming Mode timing HOLDhd
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Table 24: Video Mode Timing Parameter VDATAtd VDATAsu VDATAhd HSYNCsu HSYNChd VSYNCsu VSYNChd VSYNCtd FIELDsu FIELDhd SYNC DELAY SYNC DELAY SYNC DELAY SYNC DELAY Comments VCLK to VDATA valid delay (VDATA output) VDATA setup to rising VCLK (VDATA input) VDATA hold from rising VCLK (VDATA input) HSYNC setup to rising VCLK HSYNC hold from rising VCLK VSYNC setup to rising VCLK VSYNC hold from rising VCLK VCLK to VFRM valid delay VDATA setup to rising VCLK VDATA hold from rising VCLK Decode data sync delay for HD input with EAV/SAV codes Decode data sync delay for SD input with EAV/SAV codes Decode data sync delay for DUAL_LANE [Extended] input Decode data sync delay for HVF input [from first rising VCLK after HSYNC low to first data sample] 10 7 2 1 Min 2 2 1 2 1 2 Typ 7 9
ADV202
Max 4 4 3 4 3 4 4 3 VCLKcycles VCLKcycles VCLKcycles VCLKcycles VCLKcycles VCLKcycles VCLKcycles VCLKcycles VCLKcycles Unit VCLKcycles VCLKcycles VCLKcycles
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PRELIMINARY TECHNICAL DATA
VCLK VDATA(in) Cr VDATAhd VDATAsu Y Cb Y
FF
EAV
FF
SAV
Cb
Y
Cr
ENCODE CCIR-656 LINE (HORIZONTAL) TRANSFER TIMING
VCLK
VDATAtd
VDATA(out)
Cr
Y
Cb
Y
FF
EAV
FF
SAV
Cb
Y
Cr
DECODE MASTER CCIR-656 LINE (HORIZONTAL) TRANSFER TIMING
VCLK VDATAtd SYNC DELAY Y FF EAV HSYNChd FF SAV Cb Y
VDATA(out)
HSYNC
Y
Cr
Y Cb HSYNCsu
DECODE SLAVE CCIR-656 LINE (HORIZONTAL) TRANSFER TIMING
FIGURE 48 Video Mode -Horizontal Timing
19-Mar-2004
79
Rev. PrT
PRELIMINARY TECHNICAL DATA
Table 25: RAW Pixel Mode Timing Parameter VDATAtd VDATAsu VDATAhd VRDYtd VFRMsu VFRMhd VFRMtd VSTRBsu VSTRBhd Comments VCLK to PIXELDATA valid delay (PIXELDATA output) PIXELDATA setup to rising VCLK (PIXELDATA input) PIXELDATA hold from rising VCLK (PIXELDATA input) VCLK to VRDY valid delay VFRM setup to rising VCLK (VRAME input) VFRM hold from rising VCLK (VRAME input) VCLK to VFRM valid delay (VFRAME output) VSTRB setup to rising VCLK VSTRB hold from rising VCLK Min 2 2 1 2 2 1 Typ Max 4 4 3 4 4 3
ADV202
Unit* VCLKcycles VCLKcycles VCLKcycles VCLKcycles VCLKcycles VCLKcycles VCLKcycles VCLKcycles VCLKcycles
VCLK VDATAhd VDATAsu N 0
PIXEL DATA(in) V FRM(in) VRDY
N-1
1
2
VFRMhd VFRMsu VRDYtd VSTRBhd VSTRBsu
VSTRB VCLK PIXEL DATA VFRM(out) FIGURE 49. Raw pixel mode timing N-1 N VDATAtd 0 VFRMtd 1 2
Rev. PrT
80
19-Mar-2004
ADV202
PRELIMINARY TECHNICAL DATA
Table 26: SPI Timing Parameter SCLK_fall SCLK_ris SPIhd SPIsu NCSELhd NCSELsu CSELsu CSELhd DStime Th Tl OPh CLKov Comments S_CLK fall time S_CLK rise time Data input hold time Data input setup time Not active hold time Not active setup time Active setup time Active hold time Deselect time Clock high time Clock low time Output hold time Clock low to Output Valid Min Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
SPI Input timing SCLK_fall S_CLK SPIsu S_MOSI NCSELhd S_MISO CSELsu S_CSEL SPI Output timing S_CLK OPh S_MISO CLKov S_MOSI S_CSEL FIGURE 50. SPI timing ADDR LSB IN OE Th Tl LSB OUTN DStime CSELhd SPIhd SCLK_ris MSB IN LSB IN NCSELsu
19-Mar-2004
81
Rev. PrT
PRELIMINARY TECHNICAL DATA
ADV202
13. PIN ASSIGNMENT
Table 27. Pin assignment for ADV202 - 121-pin package PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 D1 D2 PIN DESCRIPTION DGND HDATA[2] VDD DGND HDATA[0] HDATA[1] VDATA[1] VDD DGND VDATA[0] DGND HDATA[3] HDATA[4] HDATA[5] HDATA[7] HDATA[8] IOVDD VDATA[6] VDATA[5] VDATA[4] VDATA[2] VDATA[3] DGND HDATA[6] HDATA[9] HDATA[10] HDATA[11] IOVDD VDATA[9] IOVDD VDATA[8] VDATA[7] DGND HDATA[12] HDATA[13]
Rev. PrT
82
19-Mar-2004
ADV202
PRELIMINARY TECHNICAL DATA
PIN DESCRIPTION HDATA[14] HDATA[15] IOVDD DGND VDD VSYNC HSYNC VDATA[10] VDATA[11] DGND HDATA[18]_VDATA[14] HDATA[17]_VDATA[13] HDATA[16]_VDATA[12] DGND DGND DGND IOVDD VCLK FIELD DGND DGND HDATA[19]_VDATA[15] HDATA[20]_VDATA[16] HDATA[21]_VDATA[17] DGND DGND DGND DREQ0/ DACK0/ DREQ1/ DGND DGND HDATA[22]_VDATA[18] HDATA[23]_VDATA[19] HDATA[24]_VDATA[20]_JDATA[0] DGND DGND DGND IOVDD
PIN NUMBER 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 D3 D4 D5 D6 D7 D8 D9 D10 D11 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 G1 G2 G3 G4 G5 G6 G7 G8
19-Mar-2004
83
Rev. PrT
PRELIMINARY TECHNICAL DATA
PIN NUMBER 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 G9 G10 G11 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 L3 PIN DESCRIPTION DACK1/ IRQ/ DGND HDATA[28]_JDATA[4] HDATA[27]_VDATA[23]_JDATA[3] HDATA[26]_VDATA[22]_JDATA[2] HDATA[25]_VDATA[21]_JDATA[1] IOVDD DGND VDD ACK/ RD/ ADDR[1] ADDR[3] DGND HDATA[31]_JDATA[7] HDATA[30]_JDATA[6] HDATA[29]_JDATA[5] IOVDD TEST1 WE/ CS/ ADDR[0] TEST3 DGND SCOMM[4] SCOMM[3] SCOMM[0] SCOMM[1] IOVDD IOVDD IOVDD ADDR[2] TEST2 TEST5 DGND DGND SCOMM[7] SCOMM[6]
ADV202
Rev. PrT
84
19-Mar-2004
ADV202
PRELIMINARY TECHNICAL DATA
PIN DESCRIPTION SCOMM[5] SCOMM[2] TEST4 RESET/ DGND MCLK PLLVDD DGND
PIN NUMBER 114 115 116 117 118 119 120 121 L4 L5 L6 L7 L8 L9 L10 L11
Table 28: Pin assignment for 144-pin package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 DGND HDATA[2] HDATA[1] HDATA[0] DGND DGND DGND DGND VDATA[2] VDATA[1] VDATA[0] DGND HDATA[5] HDATA[4] HDATA[3] IOVDD DGND VDD VDD DGND IOVDD VDATA[5] VDATA[4] VDATA[3] HDATA[8] HDATA[7] HDATA[6] IOVDD
19-Mar-2004
85
Rev. PrT
PRELIMINARY TECHNICAL DATA
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 C5 C6 C7 C8 C9 C10 C11 C12 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 DGND VDD VDD DGND IOVDD VDATA[8] VDATA[7] VDATA[6] HDATA[11] HDATA[10] HDATA[9] IOVDD DGND VDD VDD DGND IOVDD VDATA[11] VDATA[10] VDATA[9] HDATA[14] HDATA[13] HDATA[12] DGND DGND DGND DGND DGND FIELD VSYNC HSYNC VCLK HDATA[18]_VDATA[14] HDATA[17]_VDATA[13] HDATA[16]_VDATA[12] HDATA[15] DGND DGND DGND DGND
ADV202
Rev. PrT
86
19-Mar-2004
ADV202
69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 F9 F10 F11 F12 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12
PRELIMINARY TECHNICAL DATA
DACK1/ DREQ1/ DACK0/ DREQ0/ HDATA[22]_VDATA[18] HDATA[21]_VDATA[17] HDATA[20]_VDATA[16] HDATA[19]_VDATA[15] DGND DGND DGND DGND DGND IRQ/ ACK/ RD/ HDATA[26]_VDATA[22]_JDATA[2] HDATA[25]_VDATA[21]_JDATA[1] HDATA[24]_VDATA[20]_JDATA[0] HDATA[23]_VDATA[19] DGND DGND DGND DGND DGND WR/ CS/ ADDR[0] HDATA[30]_JDATA[6] HDATA[29]_JDATA[5] HDATA[28]_JDATA[4] HDATA[27]_VDATA[23]_JDATA[3] DGND VDD VDD DGND DGND ADDR[1] ADDR[2] ADDR[3]
19-Mar-2004
87
Rev. PrT
PRELIMINARY TECHNICAL DATA
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 SCOMM[1] SCOMM[0] HDATA[31]_JDATA[7] IOVDD DGND VDD VDD DGND IOVDD TEST3 TEST2 TEST1 SCOMM[4] SCOMM[3] SCOMM[2] IOVDD DGND VDD VDD DGND IOVDD TEST5 RESET/ MCLK DGND SCOMM[7] SCOMM[6] SCOMM[5] DGND DGND DGND DGND TEST4 PLLVDD DGND DGND
ADV202
Rev. PrT
88
19-Mar-2004
ADV202
PRELIMINARY TECHNICAL DATA
14. PACKAGE DIMENSIONS
Detail A
D D1
11 10 9 8 7 6 5 4 3 2 1
Detail B
A B C D E
E2
E
E1
F G H J K L
D2
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Detail A
ccc
Detail B
f 5 4 3 2 1 f
A3
bbb
A2 A1
A
e
ob
ddd
FIGURE 51. Package dimensions for 121-pin package
19-Mar-2004
89
Rev. PrT
PRELIMINARY TECHNICAL DATA
ADV202
Table 29: Dimensions for 121-pin package Reference A A1 A2 A3 D D1 D2 E E1 E2 b bbb ccc ddd e f M N a. All dimensions are in mm. 0.9 1.0 BSC 1.0 11 121 1.1 11.8 0.6 11.8 11.8 Minimum 1.54 0.47 0.42 0.65 11.8 Nominal 1.69 0.52 0.47 0.70 12.0 10.0 BSC 12.0 12.0 10.0 BSC 12.0 0.65 12.2 0.7 0.25 0.35 0.2 12.2 12.2 Maximum 1.84 0.57 0.52 0.75 12.2
Rev. PrT
90
19-Mar-2004
ADV202
PRELIMINARY TECHNICAL DATA
Detail 1
G R
12 11 10 9 8 7 6 5 4 3 2 1
Detail 2B
A B C D E
H
K
P
F G H J K L M
L
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Detail 1
Detail 2
5 4 3 2
u1 1 u2
V3
V7 V4
u3
V2 V1
ox=b
V6
FIGURE 52. Package dimensions for 144-pin package
19-Mar-2004
91
Rev. PrT
PRELIMINARY TECHNICAL DATA
Table 30: Package dimensions for 144-pin Reference V7 V1 V2 G R L K P H x V5 V4 V6 u3 u1 u2 b Reflow ball diameter package 0.5 0.6 0.7 1.11 1.21 0.2 1.0 1.31 13 11 13 13 11 13 V3 Minimum 1.36 0.25 Nominal 1.71 0.5 Maximum 1.85 -
ADV202
a. all dimensions in mm.
Rev. PrT
92
19-Mar-2004
PR04723-0-3/04(PrT)

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