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STE2001
65 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER
PRODUCT PREVIEW
s s s s s s
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65 x 128 bits Display Data RAM Configurable matrix: 65 x 128 or 33 x 128 Programmable (65/33) MUX rate Row by Row Scrolling Automatic data RAM Blanking procedure Selectable Input Interface: * I2C Bus Fast and Hs-mode (read and write) * Parallel Interface (write only) * Serial Interface (write only) Fully Integrated Oscillator requires no external components Fully Integrated Configurable LCD bias voltages generator with: * Selectable (5X, 4X, 3X, 2X) multiplication factor * Effective sensing for High Precision Output * Four selectable temperature compensation coefficients Designed for chip-on-glass (COG) applications Programmable bottom row pads mirroring and top row pads mirroring for compatible with both TCP and COG applications
s s s s
Low Power Consumption, suitable for battery operated systems Logic Supply Voltage range from 1.9 to 5V High Voltage Generator Supply Voltage range from 2.4 to 4.5V Display Supply Voltage range from 4.5 to 9V
DESCRIPTION
The STE2001 is a low power CMOS LCD controller driver. Designed to drive a 65 rows by 128 columns graphic display, provides all necessary functions in a single chip, including on-chip LCD supply and bias voltages generators, resulting in a minimum of externals components and in a very low power consumption. The STE2001 features three standard interfaces (Serial, parallel, I2C) for ease of interfacing with the host controller.
Type Bumped Wafers
Bumped Dice on Waffle Pack
Ordering Number STE2001DIE1 STE2001DIE2
Figure 1. Block Diagram
CO to C127 R0 to R64
OSC
OSC
TIMING GENERATOR CLOCK
COLUMN DRIVERS
ROW DRIVERS
VLCDIN
BIAS VOLTAGE GENERATOR
DATA LATCHES
SHIFT REGISTER
VLCDSENSE VLCDOUT
HIGH VOLTAGE GENERATOR
65 x 128 RAM
RESET
SCROLL LOGIC
RES VDD1,2,3 VSS1,2 SEL1,2
TEST_0_13 DATA REGISTER INSTRUCTION REGISTER
DISPLAY CONTROL LOGIC
TEST
BSY_FLG
I2CBUS
PARALLEL
SERIAL
SAO
SCL
SDA_IN
SDA_OUT
DB0 to DB7 E
PD/C
SCE
SDIN
SCLK
SD/C
D00IN1137
October 2001
This is preliminary information on a new product now in development. Details are subject to change without notice.
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PIN DESCRIPTION
N R0 to R64 Pad 1 to 16 145 to 177 257 to 272 17 to 144 227 to 238 186 to 191 192 to 201 246 to 251 239 to 244 245 Type O LCD Row Driver Output Function
C0 to C127 VSS1,2 VDD1 VDD2,3 VLCDIN VLCDOUT
VLCDSENSE
O GND Supply Supply Supply Supply Supply
LCD Column Driver Output Ground pads. VSS1 is GND for VDD1, VSS2 for VDD2 and VDD3 IC Positive Power Supply Internal Generator Supply Voltages. LCD Supply Voltages for the Column and Row Output Drivers. Voltage Multiplier Ouput Voltage Multiplier Regulation Input. VLCDOUT Sensing for Output Voltage Fine Tuning Interface Mode Selection I2C Bus Data In I2C Bus Data Out I2C bus Clock I2C Slave Address LSB External Oscillator Input Reset Input. Active Low. Parallel Interface 8 Bit Data Bus Parallel Interface Data Latch Signal. Data are Latched on the Falling EDGE. Parallel Interface Data/Command Selector Serial Interface Data Input Serial Interface Clock Serial Interface ENABLE. When Low the Incoming Data are Clocked In. Serial Interface Data/Command selection Active Procedure Flag. Notice if There is an ongoing Internal Operation. Active Low. Test Pads.
SEL1,2 SDA_IN SDA_OUT SCL SA0 OSC RES DB0 to DB7 E PD/C SDIN SCLK SCE SD/C BSYFLG T1 to T13
183, 184 223 222 224 225 185 221 211 to 218 220 219 207 210 209 208 206 178 to 181 202 to 205 226 252 to 256
I I O I I I I I I I I I I I O I/O
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ABSOLUTE MAXIMUM RATINGS
Symbol VDD1 VDD2,3 VLCD ISS Vi Iin Iout Ptot Po Tj Tstg Supply Voltage Range Supply Voltage Range LCD Supply Voltage Range Supply Current Input Voltage (all input pads) DC Input Current DC Output Current Total Power Dissipation (Tj = 85C) Power Dissipation per Output Operating Junction Temperature Storage Temperature Parameter Value - 0.5 to + 6.5 - 0.5 to + 5 - 0.5 to + 10 - 50 to +50 -0.5 to VDD2,3 + 0.5 - 10 to + 10 - 10 to + 10 300 30 -40 to + 85 - 65 to 150 Unit V V V mA V mA mA mW mW C C
ELECTRICAL CHARACTERISTICS DC OPERATION
(VDD1 = 1.9 to VDD2,3 + 0.5V; VDD2,3 = 2.4 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 9V; Tamb =-40 to 85C; unless otherwise specified)
Symbol Supply Voltages VDD1 Supply Voltage 1.9 Parameter Test Condition Min. Typ. Max. Unit
VDD2,3 + 0.5 VDD2,3 + 0.5
4.5 9 9 8 15
V
Tamb =-20 to 85C
VDD2,3 VLCDIN VLCDOUT I(VDD1) Supply Voltage LCD Supply Voltage LCD Supply Voltage Supply Current LCD Voltage Internally generated LCD Voltage Supplied externally Internally generated; note 1 VDD = 2.8V; V LCD = 7.6V; 4x charge pump; fsclk = 0; Tamb = 25C; note 3. with VOP = 0 and PRS = 0 with external VLCD = 7.6V VLCD =7.6V; VDD =2.8V; fsclk = 0; Tamb = 25C; no display load; 4x charge pump; note 3,6 Fosc = 0
1.8
V
2.4 4.5 4.5
V V V A
I(VDD2,3)
Voltage Generator Supply Current
10 70
15 115
A A
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ELECTRICAL CHARACTERISTICS (continued)
Symbol
I(VDD1,2,3)
Parameter Total Supply Current
Test Condition VLCD = 7.6V; V DD =2.8V; 4x charge pump; fsclk = 0; Tamb = 25C; no display load; note 3,6 Fosc = 0 VDD =2.8V; V LCD =7.6V;no display load; fsclk = 0; Tamb = 25C; note 3. Fosc = 0
Min.
Typ. 80
Max. 125
Unit A
I(VLDCIN)
External LCD Supply Voltage Current
15
25
A
Logic Inputs VIL VIH Logic LOW voltage level Logic HIGH Voltage Level VIN = Vih (tp < 10s) VIN = Vil (tp < 10s) VSS 0.7 VDD -1 0.3 VDD V V A
VDD2,3 + 0.5
1
Iin
Input Current
Vin = VSS1 or VDD1
Column and Row Driver Rrow R col Vcol Vrow ROW Output Resistance Column Output resistance Column Bias voltage accuracy Row Bias voltage accuracy No load -100 -100 12 12 20 20 100 100 kohm kohm mV mV
LCD Supply Voltage VLCD LCD Supply Voltage accuracy; Internally generated Temperature coefficient VDD = 2.8V; V LCD = 7.6V; fsclk=0; Tamb=25 C; no display load; note 2, 3, 6 & 7 00 01 10 11
Notes: 1. 2. 3. 4. 5. 6.
-300
300
mV
TC
-550 -1350 -1650 -2650
PPM/C PPM/C PPM/C PPM/C
The maximum possible VLCD voltage that can be generated is dependent on voltage, temperature and (display) load. Internal clock When fsclk = 0 there is no interface clock. Power-down mode. During power-down all static currents are switched-off. If external VLCD, the display load current is not transmitted to I DD Tolerance depends on the temperature; (typically zero at Tamb = 27C), maximum tolerance values are measured at the temperature range limit. 7. For TC0 to TC3
AC OPERATION
(VDD1 = 1.9 to VDD2,3 + 0.5V; VDD2,3 = 2.4 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 9V; Tamb =-40 to 85C; unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
INTERNAL OSCILLATOR FOSC FEXT Internal Oscillator frequency External Oscillator frequency VDD = 2.8V; 20 20 38 38 70 100 kHz kHz
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ELECTRICAL CHARACTERISTICS (continued)
Symbol FFRAME TVHRL Tw(RES) Parameter Frame frequency Vdd1 to RES Low RES LOW pulse width Reset Pulse Rejection Reset Pulse Rejection TSTART TVDD I2C BUS INTERFACE (See note 4) FSCL SCL Clock Frequency Fast Mode ; VDD1 =4.5V VDD1 =18V; Tamb = -20 to 70C High Speed Mode; Cb=100pF (max); note 6; VDD1 =4.5V High Speed Mode; Cb=400pF (max); note 6 ; VDD1 =4.5V TSCLL TSCLH TSCLL TSCLH TSU;DAT THD;DAT TSU;DAT THD;DAT TSU;STA TSU;STA THD;STA THD;STA TSU;STO TSU;STO TrCL TrCL TrCL1 TrCL1 TrDA TrDA TfCL TfCL Cb=100pF Cb=100pF Cb=400pF Cb=400pF Cb=100pF Cb=100pF Cb=400pF Cb=400pF Cb=100pF Cb=400pF Cb=100pF Cb=400pF Cb=100pF Cb=400pF Cb=100pF Cb=400pF Cb=100pF Cb=400pF Cb=100pF Cb=400pF Cb=100pF Cb=400pF Note 8 Note 8 Note 8 Note 8 Note 8 Note 8 Note 5, 8 Note 5, 8 Note 5, 8 Note 5, 8 Note 5, 8 Note 5, 8 Note 5, 8 Note 5, 8 DC DC 160 160 320 320 30 30 30 30 170 330 170 330 170 330 25 50 30 120 30 120 25 50 3.4 1.7 DC 400 400 kHz kHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Reset Pulse vs. Device Ready Test Condition fosc or fext = 38 kHz; note 1 note 2 and 10; CVLCD = 1F note 3 Tamb = 25C; note 11 note 11 1 0 0 600 370 200 Min. Typ. 73 5 Max. Unit Hz ms ns s s ms
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ELECTRICAL CHARACTERISTICS (continued)
Symbol TfDA TfDA Cb Cb T SW PARALLEL INTERFACE TCY(EN) TW(EN) TSU(A) TH(A) TSU(D) TH(D) Enable Cycle Time Enable Pulse width Address Set-up Time Address Hold Time Data Set-Up Time Data Hold Time VDD = 4.5V; Write VDD = 4.5V; Write VDD = 4.5V; Write VDD = 4.5V; Write VDD = 4.5V; Write VDD = 4.5V; Write 125 60 30 50 30 50 ns ns ns ns ns ns Cb=100pF Cb=400pF Capacitive load for SDAH and SCLH Capacitive load for SDAH + SDA line and SCLH + SCL line note 5 10 100 Parameter Test Condition Min. Typ. 25 120 400 400 Max. Unit ns ns pF pF ns
SERIAL INTERFACE FSCLK Clock Frequency VDD = 4.5V VDD1 = 1.8V TCYC TPWH1 TPWL1 TS2 TH2 TPWH2 TH5 TS3 TH3 TS4 TH4 Clock Cycle SCLK SCLK pulse width HIGH SCLK Pulse width LOW SCE setup time SCE hold time SCE minimum high time SCE start hold time SD/C setup time SD/C hold time SDIN setup time SDIN hold time f osc Note 8 VDD = 4.5V VDD = 4.5V VDD = 4.5V 125 70 70 50 50 60 60 60 40 40 40 8 5 MHz MHz ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. F frame = --------520
2. RES may be LOW or HIGH before VDD1 goes HIGH. 3. If T w(RES) is longer than 500ns (typical) a reset may be generated. 4. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to V IL and VIH with an input voltage swing of VSS to VDD 5. The rise and fall times specified here refer to the driver device and are part of general Hs-mode specification. 6. The device inputs SDA and SCL are filtered and will reject any spike on the bus-lines of with T SW 7. Cb is the capacitive load for each bus line. 8. T H5 is the time from the previous SCLK positive edge to the negative edge of SCE 9. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated 10.C VLCD is the filterin g capacitor on VLCDOUT 11.If T w(RES) is shorter than max. value a reset pulse is rejected.
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CIRCUIT DESCRIPTION Supplies Voltages and Grounds
VDD2 and VDD3 are supply voltages to the internal voltage generator (see below). They must be externally connected. If the internal voltage generator is not used, these should be connected to V pad. VDD1 supplies the rest of the IC. DD1 This supply voltage could be different form V DD2 and VDD3. VDD1 must be lower than VDD2,3 + 0.5V.
Internal Supply Voltage Generator
The IC has a fully integrated (no external capacitors required) charge pump for the Liquid Crystal Display supply voltage generation. The multiplyin g factor can be programmed to be: X5; X4; X3; X2, using the 'set CP Multiplica tion' Command. The output voltage (VLCDOUT) is tightly controlled through the VLCDSENSE pad. For this voltage, four different temperature coefficient s(TC, rate of change with temperature) can be programmed using the bits TC1 and TC0. This will ensure no contrast degradation over the LCD operating range. Using the internal charge pump, the VCDIN L and VLCDOUT pads must be connected together. An external supply could be connected to V LCDIN to supply the LCD without using the internal generator. In such event the V LDCOUT and VLCDSENSE must be connected to GND and the internal voltage generator must be programmed to zero (PRS = 0, Vop = 0 - Reset condition).
Oscillator
A fully integrated oscillator (requires no external components) is present to provide the clock for the Displa y System. When used the OSC pad must be connectedto VDD1 pad. An external oscilla torcould be used and fed into the OSC pin.
Display Data RAM
The STE2001, provides an 65X128 bits Static RAM to store Display data. This is organized into 8 (Bank0 to Bank7) banks with 128 Bytes and one Bank (Bank8) with 128 Bits to be used for icons. RAM access is accomplished in either one of the Bus Interfaces provided (see below). Allowed addresses are X0 to X127 (Horizontal) and Y0 to Y8 (Vertical). When writing to RAM, four addressing mode are provided:
* Normal Horizontal (MX = 0 and V = 0), having the column with address X = 0 located on the left of the memory map. The X pointer is increased after each byte written. After the last column address (X = 127), Y address pointer is modified to jump to next row. X restarts from X = 0 (Fig.2). * Normal Vertical (MX = 0 and V = 1), having the column with address X = 0 located on the left of the memory map. The Y pointer is increased after each byte written. After the last row address (Y = 8), the X pointer is modified to jump to next column and Y restarting from Y = 0. (Fig. 3). * Mirrored Horizontal (MX = 1 and V = 0), having the column with address X = 0 located on the right of the memory map. The X pointer is increased after each byte written. After the last column address (X = 127), Y address pointer is modified to jump to next row. X restarts from X = 0 (fig. 4). * Mirrored Vertical (MX =1 and V = 1), having the column with address X = 0 located on the right of the memory map. The Y pointer is increased after each byte written. After the last row address (Y = 8), the X pointer is modified to jump to next column and Y restarting from Y = 0. (Fig. 5).
After the last allowed address (X;Y) = (128;8), the address pointers always jump to the cell with address (X;Y) = (0;0). Data bytes in the memory could have the MSB either on top (D0 = 0, Fig. 6) or on the bottom (D0 = 1, Fig. 7).
Mux 65 Mode
The STE2001 provides also means to alter the normal output addressing. A mirroring of the Display along the X axis is enabled setting to a logic one the MY bit. This function is achieve d reading the matrix from physical row 63 to 0, since the relation between the physical memory rows and the output row drivers is only dependent on the memory reading sequence (1st row read output on R0, 2nd on R1... last on R65). This function doesn't affect the content of the memory map. It is only related to the visualizatio nprocess (Fig. 8 & Fig. 9). It is also possible to modify the why with which row drivers are connected with DDRAM memory. A flip along y-axis of each sub-block can be applied on both the Row Pads located on the Interface Side (the edge of the chip where the Interface Pads are located), setting the TRS bit to a logic one, and on the Row Pads located on the other edge, setting the BRS bit to a logic one. Figure 2 Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0) Figure 3 Automatic data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0)
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Figure 2. Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0)
0 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8
1
2
3
124
125
126
127
D00IN1138
Figure 3. Automatic data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0)
0 BANK BANK BANK BANK BANK BANK BANK BANK BANK 0 1 2 3 4 5 6 7 8
1
2
3
124
125
126
127
D00IN1139
Figure 4. Automatic data RAM writing sequence with V=0 and Data RAM Mirrored Format (MX=1)
127 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8
126
125
124
3
2
1
0
D00IN1140
Figure 5. Automatic data RAM writing sequence with V=1 and Data RAM Mirrored Format (MX=1)
127 BANK BANK BANK BANK BANK BANK BANK BANK BANK 0 1 2 3 4 5 6 7 8
126
125
124
3
2
1
0
D00IN1141
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Figure 6. Data RAM Byte organization with D0 = 0
MSB 0 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8
D00IN1142
1
2
3
124
125
126
127
LSB
Figure 7. Data RAM Byte organization with D0 = 1
LSB 0 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8
D00IN1143
1
2
3
124
125
126
127
MSB
Figure 8. Output drivers rows and physical memory rows correspondence with MY =0
ROW DRIVER PHYSICAL MEMORY ROW
0 R R R R R R 0 1 2 3 4 5 ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5
1
2
3
124
125
126
127
R 60 R 61 R 62 R 63 R 64
ROW 60 ROW 61 ROW 62 ROW 63 ROW 64
D00IN1144
Figure 9. Output drivers rows and physical memory rows correspondence with MY =1
ROW DRIVER PHYSICAL MEMORY ROW
0 R 63 R 62 R 61 R 60 R 59 R 58 ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5
1
2
3
124
125
126
127
R3 R2 R1 R0 R 64
ROW 60 ROW 61 ROW 62 ROW 63 ROW 64
D00IN1145
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MUX 33 Mode
When using the 1:33 MUX ratio (MUX bit Set), the memory map is changed so that the only "active" row drivers are the ones related to Bank4 to Bank7. When writing data RAM, as for Mux 65, four addressing mode are provided. The memory matrix is written as in mux 65 mode so the user must take care of updating X and Y pointers to fill the memory matrix in the correct way. In MUX 33 mode only the MUX 33 memory logic matrix is read. The MY bit control the reading process. If MY is set to a logic zero the row reading sequence is 0-1-2..........33 (fig.11). If MY is set to a logic one the reading sequence is 32....1-33 (Fig 12). The icon row (BANK8) is always the last being output either MY bit is a logic one or zero. The functions related to bit TRS is the same as in MUX 65 mode. In fig. 11 is shown the output drivers pad connection for MUX 33 mode. Note that the unused BANK 0-3 row drivers become columns drivers. If a 33x128 LCD matrix is driven, the output row drivers R0-R15 and R32-R47 must be floating.
Figure 10. Physical 65x128 memory matrix and 33x128 correspondence
01
14 15 16 17 18
109 110 111 112 113
126 127
BANK BANK BANK BANK BANK BANK BANK BANK BANK
0 1 2 3 4 5 6 7 8
NOT USED
D00IN1146
R16-R23 R24-R31 R48-R55 R56-R63 R64
D00IN1147
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C120 C121 C122 C123 C124 C125 C126 C127
C0 C1 C2 C3 C4 C5 C6 C7
STE2001
Figure 11. Output drivers rows and logical memory rows correspondence with MY = 0
ROW DRIVER MUX 33 PHYSICAL MEMORY ROW
01 R16 to R23 R24 to R31 R48 to R55 R56 to R63 R64 Row 0 to Row 7 Row 8 to Row15 Row 16 to Row 23 Row 24 to Row 31 Row 32
23
45
67
120 121 122 123 124 125 126 127
BANK 4 BANK 5 BANK 6 BANK 7 BANK 8
D00IN1148
Figure 12. Output drivers rows and logical memory rows correspondence with MY = 1
ROW DRIVER MUX 33 PHYSICAL MEMORY ROW
01 R16 to R23 R24 to R31 R48 to R55 R56 to R63 R64 Row 0 to Row 7 Row 8 to Row15 Row 16 to Row 23 Row 24 to Row 31 Row 32
23
45
67
120 121 122 123 124 125 126 127
BANK 4 BANK 5 BANK 6 BANK 7 BANK 8
D00IN1148
Instruction Set
Two different instructions formats are provided: - With D/C set to LOW commands are sent to the Control circuitry. - With D/C set to HIGH the Data RAM is addressed Instructions have the syntax summarized in Table.1.
Reset (RES)
At power-on, all internal registers and RAM content are not defined. A Reset pulse must be applied on RES pad (active low) to initialize the internal registers content (see Tables 3,4,5,&6). Every on-going communication with the host controller is interrupted. The IC after the reset pulse is programmed in Power Down mode. The Default configurations is: - Horizontal addressing (V = 0) - Normal instruction set (H = 0) - Normal display (MX = MY = TRS =BRS = 0) - MUX 65 mode (MUX = 0)
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- Display blank (E = D = 0) - Address counter X[6: 0] = 0 and Y[3 : 0] = 0 - Temperature coefficient (TC[1 : 0] = 0) - Bias system (BS[2 : 0] = 0) - VOP = 0 - Power Down (PD = 1) To clear the RAM content a MEMORY BLANK instruction should be executed.
Power Down (PD = 1)
When at Power Down, all LCD outputs are kept at VSS (display off). Bias generator and VLCD generator are OFF (VLCDOUT output is discharged to VSS, and then is possible to disconnect VLCDOUT). The internal Oscillator is in off state. An external clock can be provided. The RAM contents is not cleared.
Charge Pump Factor
The desired Charge Pump Multiplication Factor can be programmed though the S1 and S0 bits, as follows:
S1 0 0 1 1 S0 0 1 0 1 Multiplication Factor 2X 3X 4X 5X
At Reset the X2 factor is selected.
Bias Levels
To properly drive the LCD, six (Including VLCD and VSS) different voltage (Bias) levels are generated. The ratios among these levels and VLCD, should be selected according to the MUX ratio (m). They are established to be (Fig. 14):
n+3 n+2 2 1 -V LCD , ------------ VLCD , ---------- - VLCD , ------------ VL CD , ------------ V LCD ,V SS n+4 n+4 n+4 n+4 Figure 13. Bias level Generator
VLCD n+3 *VLCD n+4 R n+2 *VLCD n+4 nR 2 *VLCD n+4 R 1 *VLCD n+4 R VSS
D00IN1150
R
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thus providing an 1/(n+4) ratio, with n calculated from:
n=
For m = 65, n = 5 and an 1/9 ratio is set. For m = 33, n =3 and an 1/7 ratio is set.
m-3
The STE2001 provides three bits (BS0, BS1, BS2) for programming the desired Bias Ratio as shown below:
BS2 0 0 0 0 1 1 1 1 BS1 0 0 1 1 0 0 1 1 BS0 0 1 0 1 0 1 0 1 n 7 6 5 4 3 2 1 0
The following table Bias Level for m = 65 and m = 33 are provided:
Symbol V1 V2 V3 V4 V5 V6 m = 65 (1/9) V LCD 8/9*VLCD 7/9*VLCD 2/9*V VLCD 1/9 *VLCD VSS m = 33 (1/7) VLCD 6/7* VLCD 5/7* VLCD 2/7* VLCD 1/7* VLCD VSS
LCD Voltage Generation
The LCD Voltage at reference temperature (To = 35C) can be set using the VOP register content according to the following formula: VLCD(T=To) = VLCDo = (Ai+VOP * B) with the following values:
Symbol Ao A1 B To Value 2.90 6.91 0.034 35 Unit V V V C Note PRS = 0 PRS = 1
(i=0,1)
Note that the two PRS value produces two adjacent ranges for VLCD. If the register and PRS bit are set to zero
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the internal voltage generator is switched off. The proper value for the VLCD is a function of the Liquid Crystal Threshold Voltage (Vth) and of the Multiplexing Rate. A general expression for this is:
For MUX Rate m = 65 the ideal VLCD is:
1+ m V LCD = ------------------------------------ Vth 1 2 1 - -------- m
VLCD(to) = 6.85 * Vth
than:
( 6.85 Vth - Ai ) V o p = ----------------------------------------0.03
Temperature Coefficient
As the viscosity, and therefore the contrast, of the LCD are subject to change with temperature, there's the need to vary the LCD Voltage with temperature. The STE2001 provides the possibility to change the VLCD in a linear fashion against temperature with four different Temperature Coefficient selectable through the TC0 and TC1 bits.
TC1 0 0 1 1
TC0 0 1 0 1
Value -550 -1350 -1650 -2650
Unit PPM/C PPM/C PPM/C PPM/C
Figure 14. VLCD Slopes Cross Point with Different TC
VLCD
D01IN1256/mod
35C
TEMP
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Figure 15.
VLCD B
A1
A0
A0+B
7Ch 7Dh 7Eh 7Fh VO D01IN1257
00h 01h 02h 03h 04h 05h
PRS=0
7Ch 7Dh 7Eh 7Fh 00h 01h 02h 03h 04h 05h
PRS=1
Finally, the VLCD voltage at a given (T) temperature can be calculated as: VLCD(T) = VLCDo * [1 + (T-To) * TC]
Memory Blanking Procedure
This instruction allows to fill the memory with "blank" patterns, in order to delete patterns randomly generated in memory when starting up the device. This instruction substitutes (128X9) single "write" instructions. It is possible to program "Memory Blanking Procedure" only under the following conditions: - X address = 0 - Y address = 0 - V bit - PD bit - MX bit =0 =0 =0
The end of the procedure will be notified on the BSY_FLG pad going HIGH (while LOW the procedure is running). Any instruction programmed with BSY_FLG LOW will be ignored that is, no instruction can be programmed for a period equivalent to 128X9 internal write cycles (128X9X1/fclock). The start of Memory blanking procedure will be between one and two fclock cycles from the last active edge (E rising edge for the parallel interface, last SCLK rising edge for the Serial interface, last SCL rising edge for the I2C interface).
Checker Board Procedure
This instruction allows to fill the memory with "checker-board" pattern. It is mainly intended to developers, who can now simply obtain complex module test configuration by means of a single instruction. It is possible to program "Checker Board Procedure" only under the following conditions: - X address = 0 - Y address = 0 - V bit - PD bit - MX bit =0 =0 =0
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The end of the procedure will be notified on the BSY_FLG pad going HIGH, while LOW the procedure is running. Any instruction programmed with BSY_FLG LOW will be ignored, that is, no instruction can be programmed for a period equivalent to 128X9 internal write cycles (128X9X1/fclock). The start of Memory blanking procedure will be between one and two fclock cycles from the last active edge (E rising edge for the parallel interface, last SCLK rising edge for the Serial interface, last SCL rising edge for the I2C interface).
Scroll
The STE2001 can scroll the graphics display in units of raster-rows. The scrolling function is achieved changing the correspondence between the rows of the logical memory map and the output row drivers. The scroll function doesn't affect the data ram content. It is only related to the visualization process. The information output on the drivers is related to the row reading sequence (the 1st row read is output on R0, the 2nd on R1 and so on). Scrolling means reading the matrix starting from a row that is sequentially increased or decreased. After every scrolling command the offset between the memory address and the memory scanning pointer is increased or decreased by one. The offset range is between 0 to 63 in mux 65 mode and 0-31 in mux 33 mode. After the 64th scrolling command in mux 65 mode and after the 32th in mux 33 mode, the offset between the memory address and the memory scanning pointer is again zero (Cyclic Scrolling). Bank8 is always accessed last in each frame, and so isn't scrolled.
If the DIR Bit is set to a logic zero the offset register is increased by one and the raster is scrolled from top down. If the DIR Bit is set to a logic one the offset register is decreased by one and the raster is scrolled from bottom-up.
Bus Interfaces
To provide the widest flexibility and ease of use the STE2001 features three different methods for interfacing the host Controller. To select the desired interface the SEL1 and SEL2 pads need to be connected to a logic LOW (connect to GND) or a logic HIGH (connect to VDD). All the I/O pins of the unused interfaces must be connected to GND. If I/O pins voltage is lower than VDD interfaces could sink more current than expected. All interfaces are working while the STE2001 is in Power Down.
SEL2 0 0 1 1 SEL1 0 1 1 0 Interface I2C Serial Parallel Not Used Note Read and Write; Fast and High Speed Mode Write only Write only
I2C Interface
The I2C interface is a fully complying I2C bus specification, selectable to work in both Fast (400kHz Clock) and High Speed Mode (3.4MHz). This bus is intended for communication between different Ics. It consists of two lines: one bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via an active or passive pull-up. The following protocol has been defined: - Data transfer may be initiated only when the bus is not busy. - During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as control signals. Accordingly, the following bus conditions have been defined:
BUS not busy: Both data and clock lines remain High. Start Data Transfer: A change in the state of the data line, from High to Low, while the clock is High, define the START condition.
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STE2001
Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock signal is High, defines the STOP condition. Data Valid: The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the High period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and the stop conditions is not limited. The information is transmitted bytewide and each receiver acknowledges with the ninth bit. By definition, a device that gives out a message is called "transmitter", the receiving device that gets the signals is called "receiver". The device that controls the message is called "master". The devices that are controlled by the master are called "slaves"
Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA_IN line during the acknowledge clock pulse. Of course, setup and hold time must be taken into account. A master receiver must signal an endof-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave the data line High to enable the master to generate the STOP condition.
Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line. Having the acknowledge output (SDAOUT) separated from the serial data line is advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from the SDAOUT pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that during the acknowledge cycle the STE2001 will not be able to create a valid logic 0 level. By splitting the SDA input from the output the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDACK pad to the system SDA line to guarantee a valid LOW level.
To be compliant with the I2C-bus Hs-mode specification the STE2001 is able to detect the special sequence "S00001xxx". After this sequence no acknowledge pulse is generated. Since no internal modification are applied to work in Hs-mode, the device is able to work in Hs-mode without detecting the master code.
Figure 16. Bit transfer and START,STOP conditions definition
DATA LINE STABLE DATA VALID CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
D00IN1151
STOP CONDITION
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STE2001
Figure 17. Acknowledgment on theI2C-bus
START SCLK FROM MASTER CLOCK PULSE FOR ACKNOWLEDGEMENT 1 2 8 9
DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER
MSB
LSB
D00IN1152
Figure 18. I2C-bus timings
Sr tfDA trDA Sr P
SDAH tHD;DAT tSU;STA SCLH tfCL trCL tHIGH tLOW RES tSTART
= MCS current source pull-up = Rp resistor pull-up
tSU;DAT
t HD;STA
trCL1
(1)
trCL1
(1)
tLOW tHIGH
D00IN1153
Communication Protocol
The STE2001 is an I2C slave. The access to the device is bi-directional since data write and status read are allowed. Two are the devic e addresses availabl e for the device. Both have in common the first 6 bits (011110). The least significa nt bit of the slave address is set by connecting the SA0 input to a logic 0 or to a logic 1. To start the communication between the bus master and the slav e LCD driver, the master must initiate a START condition. Followin g this, the master sends an 8-bit byte, shown in Fig. 18, on the SDA bus line (Most signif icant bit first). This consists of the 7-bit Device select Code, and the 1-bit Read/Write Designator (R/ W). All slaves with the corresponding address acknowledge in parallel, all the others will ignore the2IC-bus transfer.
Writing Mode.
If the R/W bit is set to logic 0 the STE2001 is set to be a receiver. After the slaves acknowledge one or more command word follows to define the status of the device. A command word is composed by two bytes. The first is a control byte which defines the Co and D/C values, the second is a data byte (fig 18). The Co bit is the command MSB and defines if after this command will follow one data byte and an other command word or if will follow a stream of data (Co = 1 Command word, Co = 0 Stream of data). The D/C bit defines whether the data byte is a command or RAM data (D/C = 1 RAM Data, D/ C = 0 Command). If Co =1 and D/C = 0 the incoming data byte is decoded as a command, and if Co =1 and D/C =1, the following data byte will be stored in the data RAM at the location specified by the data pointer. E very byte of a command word must be acknowledged by all addressed units. After the last control byte, if D/C is set to a logic 1 the incoming data bytes are stored inside the STE2001 Display RAM starting at the address specified by the data pointer. The data pointer is automatically updated after every byte written and in the end points to the last RAM location written. Every byte must be acknowledged by all addressed units.
Reading Mode.
If the R/W bit is set to logic 1 the chip will output data immediately after the slave address. If the D/C bit sent during the last write access, is set to a logic 0, the byte read is the status byte.
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STE2001
Figure 19. communication protocol
WRITE MODE STE2001 ACK STE2001 ACK STE2001 ACK STE2001 ACK STE2001 ACK
S S 0 1 1 1 1 0 A 0 A 1 DC Control Byte A 0 R/W Co SLAVE ADDRESS READ MODE STE2001 ACK S S011110A1A 0 R/W
D01IN1247
DATA Byte
A 0 DC Control Byte A
DATA Byte
AP
Co COMMAND WORD
LAST CONTROL BYTE
N> 0 BYTE MSB........LSB
MASTER SR 011110A/ 0W STE2001 SLAVE ADDRESS
P
CD0 00000A oC
CONTROL BYTE
SERIAL INTERFACE
The STE2001 serial Interface is a unidirectional link between the display driver and the application supervisor. It consists of four lines: one for data signals (SDIN), one for clock signals (SCLK), one for the peripheral enable (SCE) and one for mode selection (SD/C). The serial interface is active only if the SCE line is set to a logic 0. When SCE line is high the serial peripheral power consumption is zero. The STE2001 is always a slave on the bus and receive the communication clock on the SCLK pin from the master. The STE2001 is only able to receive data. Information are exchanged byte-wide. During data transfer, the data line is sampled on the positive SCLK edge. While SCE pin is high the serial interface is kept in reset. SD/C line status indicates whether the byte is a command (SD/C =0) or RAM data (SD/C =1);it is read on the eighth SCLK clock pulse during every byte transfer. If SCE stays low after the last bit of a command/data byte, the serial interface expects the MSB of the next byte at the next SCLK positive edge. A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM and all the internal registers are cleared. If SCE is low after the positive edge of RES, the serial interface is ready to receive data.
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STE2001
Figure 20. Serial bus protocol - one byte transmission
SCE
D/C
SCLK
SDIN
MSB
LSB
D00IN1159
Figure 21. Serial bus protocol - several byte transmission
SCE
D/C
SCLK
SDIN
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
D00IN1160
Figure 22. RESET effect on the serial interface
tS2 SCE tS3 tH3 t(H5) tH2 tPWH2
tH5
D/C tCYC tPWL1 SCLK tS4 SDIN tH4 tWH1 tS2
RES
tSTART
D00IN1161
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STE2001
Parallel Interface
The STE2001 parallel Interface is a unidirectional link between the display driver and the application supervisor. It consists of ten lines: eight data lines (from DB7 to DB0) and two control lines. The control lines are: enable (E) for data latch and PD/C for mode selection. The data lines and the control line values are internally latched on E rising edge (fig. 23).
Figure 23. Parallel interface timing
PD/C tSU(A) E tSU(D) tHO(D) tCY(en) DB0-DB7 tW(en) th(A)
RES
tSTART
D00IN1162
Table 1. Instruction Set
Instruction D/C R/W B7 H=0 or H=1 NOP Function Set Read Status Byte Write Data H=0 Memory Blank Scroll
VLCD Range Setting
Description B6 B5 B4 B3 B2 B1 B0
0 0 0 1
0 0 1 0
0 0 PD D7
0 0
0 1
0 MX D D4
0 MY E D3
0 PD MX D2
0 V MY D1
0 H DO D0
No Operation Power Down Management; Entry Mode; Extended Instruction Set ( I2C interface only ) Writes data to RAM
TRS BRS
D6
D5
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 1
0 0 0 0 0 1 X6
0 0 0 0 0 0 X5
0 0 0 0 1 0 X4
0 0 0 1 0 Y3 X3
0 0 1 D 0 Y2 X2
0 1 0 0 S1 Y1 X1
1 DIR
Starts Memory Blank Procedure
Scrolls by one Row UP or DOWN
PRS VLDC programming range selection
Display Control Set CP Factor Set RAM Y Set RAM X H=1 Checker Board Multiplex Select TC Select Output Address Bias Ratios Reserved Set VOP
E S0 Y0 X0
Select Display Configuration
Charge Pump Multiplication Factor
Set Horizontal (Y) RAM Address Set Vertical (X) RAM Address
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 1
0 0 0 0 0 1
0 0 0 0 0 X
0 0 0 0 1 X
0 0 0 1 0 X
0 0 1 DO
0 1
1
MUX
Starts Checker Board Procedure Selects MUX factor
TC1 TC0 Set Temperature Coefficient for VLDC
TRS BRS
Set Row Order on Output Pads Set desired Bias Ratios Not to be used VOP register Write instruction
BS2 BS1 BS0 X X X
OP6 OP5 OP4 OP3 OP2 OP1 OP0
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Table 2. Explanations of Table 6 symbols
BIT DIR H PD V MX MY TRS BRS DO PRS MUX 0 Scroll by one down Use basic instruction set Device fully working Horizontal addressing Normal X axis addressing Image is displayed not vertically mirrored No top rows mirroring No bottom rows mirroring MSB on TOP VLCD = 2.94V 1:65 multiplexing ratio 1 Scroll by one up Use extended instruction set Device in power down Vertical addressing X axis address is mirrored. Image is displayed vertically mirrored Top rows mirroring (row pads 16-31 & 48-64) Bottom rows mirroring (row pads 0-15 & 32-47) MSB on BOTTOM V LCD = 6.75V 1:33 multiplexing ratio 0 1 0 0 0 0 0 0 0 0 RESET STATE
Table 3.
D 0 1 0 1 E 0 0 1 1 display blank normal mode all display segments on inverse video mode D=0 E=0 DESCRIPTION RESET STATE
Table 4.
S1 0 0 1 1 S0 0 1 0 1 DESCRIPTION Multiplication Factor 2X Multiplication Factor 3X Multiplication Factor 4X Multiplication Factor 5X 0 RESET STATE
Table 5.
TC1 0 0 1 1 TC0 0 1 0 1 DESCRIPTION VLCD temperature Coefficient 0 VLCD temperature Coefficient 1 VLCD temperature Coefficient 2 VLCD temperature Coefficient 3 00 RESET STATE
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Table 6.
BS2 0 0 0 0 1 1 1 1 BS1 0 0 1 1 0 0 1 1 BS0 0 1 0 1 0 1 0 1 DESCRIPTION Bias Ratio equal to 7 Bias Ratio equal to 6 Bias Ratio equal to 5 Bias Ratio equal to 4 Bias Ratio equal to 3 Bias Ratio equal to 2 Bias Ratio equal to 1 Bias Ratio equal to 0 000 RESET STATE
Figure 24. Application Schematic Using an External LCD Voltage Generator
I/O VDD2,3 VDD VDD1 100nF VSS VSS2 VSS1 1F VLCDSENSE VLCDOUT VLCD VLCDIN 33 128 65 x 128 DISPLAY 32
D00IN1157
Figure 25. Application Schematic using the Internal LCD Voltage Generator and two separate supplies
I/O VDD2 VDD1 100nF VSS VDD2,3 VDD1 100nF VSS2 VSS1 1F VLCDSENSE VLCDOUT VLCDIN 33 128 65 x 128 DISPLAY 32
D00IN1158
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Figure 26. Application Schematic using the Internal LCD Voltage Generator and a single supply
I/O
VDD
VDD2,3 VDD1
32
100nF VSS VSS2 VSS1 1F VLCDSENSE VLCDOUT VLCDIN 33 128
65 x 128 DISPLAY
D00IN1156
Figure 27. Pad Configuration with I2C interface
TEST_13 TEST_12 TEST_11 TEST_10 TEST_8 VSS2 VSS1 TEST 9 SA0 SCL SDAIN SDAOUT RES E PD/C D0 D1 D2 D3 D4 D5 D6 D7
GND
VDD1/GND/VSSOUT
STE2001
P
VDD1
SCLK SCE SD/C SDIN BSY_FLG TEST_7 TEST_6 TEST_5 TEST_4 VDD3 VDD2 VDD1 OSCIN SEL1 SEL2 VSSOUT TEST_3 TEST_2 TEST_1 TEST_0
D01IN1261
GND/VSSOUT
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STE2001
Figure 28. Pad Configuration with Parallel interface
TEST_13 TEST_12 TEST_11 TEST_10 TEST_8 VSS2 VSS1 TEST 9 SA0 SCL SDAIN SDAOUT
GND VDD1/GND/VSSOUT VDD1
STE2001
RES E PD/C D0 D1 D2 D3 D4 D5 D6 D7 SCLK SCE SD/C SDIN BSY_FLG TEST_7 TEST_6 TEST_5 TEST_4 VDD3 VDD2 VDD1 OSC SEL1 SEL2 VSSOUT TEST_3 TEST_2 TEST_1 TEST_0
D01IN1262
P
VDD1
GND/VSSOUT VDD1
Figure 29. Pad Configuration with Serial interface
TEST_13 TEST_12 TEST_11 TEST_10 TEST_8 VSS2 VSS1 TEST 9 SA0 SCL SDAIN SDAOUT
GND
VDD1/GND/VSSOUT VDD1
STE2001
RES E PD/C D0 D1 D2 D3 D4 D5 D6 D7 SCLK SCE SD/C SDIN BSY_FLG TEST_7 TEST_6 TEST_5 TEST_4 VDD3 VDD2 VDD1 OSCIN SEL1 SEL2 VSSOUT TEST_3 TEST_2 TEST_1 TEST_0
D01IN1263
P
VDD1
VDD1 GND/VSSOUT
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Figure 30. Power OFF Timing Diagram
VDD2/3 tVDD VDD1
RES
INPUTS
D01IN1264
Figure 31. Power OFF Sequence
POWER OFF SEQUENCE
SET by Software (PD=0) or (Vop=0 & PRS=[0;0])
Force Active Input Lines Low
REMOVE VDD1
REMOVE VDD2/3
END OF POWER OFF SEQUENCE
D01IN1265
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Figure 32. Power-Up & RESET timing diagram
VDD2/3 tVDD
VDD1
tW(RES) RES
INPUTS
D01IN1189
Figure 33. Power-Up & RESET timing diagram
VDD2/3 t tVDD VHRL VDD1
tW(RES) RES
INPUTS
D01IN1190
Figure 34. Power Up Sequence
POWER UP SEQUENCE
Set Active Input lines low
Apply VDD2/3
Apply VDD1
Apply a RESET Pulse
END OF POWER UP SEQUENCE (STE2001 in Reset State)
D01IN1266
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Figure 35. Chip Mechanical Drawing
ROW 0 ALIGNEMENT MARK ROW 16
STE2001
ROW 15 COL 0
ALIGNEMENT MARK
ROW 31
TEST
VLCDIN
VLCDSENSE
VLCDOUT
VSS2
VSS1
TEST SA0 SCL SDAIN SDAOUT RES E PD/C D0 D1 D2 D3 D4 D5 D6 D7 SCLK SCE SD/C SDIN BSY_FLG TEST
COL 63 COL 64
(0,0)
Y X
VDD2
VDD3
VDD1
OSC SEL1 SEL2 VSSOUT TEST COL 127 ROW 47 ALIGNEMENT MARK ROW 64
ROW 32
ALIGNEMENT MARK
ROW 48
D01IN1191
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Figure 36. Improved ALTH & PLESKO Driving Method
VLCD V2 V3 ROW 0 R0 (t) V4 V5 VSS VLCD V2 V3 ROW 1 R1 (t) V4 V5 VSS VLCD V2 V3 COL 0 C0 (t) V1(t) V2(t)
V4 V5 VSS
VLCD V2 V3 COL 1 C1 (t) V4 V5 VSS VLCD - VSS V3 - VSS VLCD - V2 0V V3 - VSS V4 - V5 0V VSS - V5 V4 - VLCD VSS - VLCD
Vstate1(t)
VLCD - VSS V3 - VSS VLCD - V2 0V V3 - VSS
Vstate2(t)
V4 - V5 0V VSS - V5
V4 - VLCD VSS - VLCD
0 1 2 3 4 5 6 7 8 9 ....... ..... 64 0 1 2 3 4 5 6 7 8 9 ....... ..... 64
FRAME n V1(t) = C1(t) - R0(t) V2(t) = C1(t) - R1(t)
FRAME n + 1
D00IN1154
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Figure 37. DATA RAM to display Mapping
DISPLAY DATA RAM
bank 0
GLASS TOP VIEW
bank 1
DISPLAY DATA RAM = "1" DISPLAY DATA RAM = "0"
bank 2
LCD
bank 3
bank 7
bank 8
ICOR ROW
D00IN1155
Table 7. Test Pin Configuration
Test Numb. TEST_0 TEST_1 TEST_2 TEST_3 TEST_4 TEST_5 TEST_6 TEST_7 T8 T9 TEST_10 TEST_11 TEST_12 TEST_13 Pin GND GND GND GND OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN
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Table 8. Mechanical Dimensions
Die Size Pad Pitch Pad Size Bump Dimensions WFS Thickness 2.12mmX12.5mm 70 m 62m X 100 m 50mX88mX17.5 500m
Table 9. Pad Coordinates (continued)
NAME C13 C14 C15 C16 C17 C18 PAD 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 X (m) -3,681.8 -3,611.8 -3,541.8 -3,471.8 -3,401.8 -3,331.8 -3,261.8 -3,191.8 -3,121.8 -3,051.8 -2,981.8 -2,911.8 -2,841.8 -2,771.8 -2,701.8 -2,631.8 -2,561.8 -2,491.8 -2,421.8 -2,351.8 -2,281.8 -2,211.8 -2,141.8 -2,071.8 -2,001.8 -1,931.8 -1,861.8 -1,791.8 -1,721.8 -1,651.8 -1,581.8 -1,511.8 -1,441.8 -1,371.8 -1,301.8 -1,231.8 -1,161.8 Y(m) -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2
Table 9. Pad Coordinates
NAME R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 X (m) -5,994 -5,924 -5,854 -5,784 -5,714 -5,644 -5,574 -5,504 -5,434 -5,364 -5,294 -5,224 -5,154 -5,084 -5,014 -4,944 -4,591.8 -4,521.8 -4,451.8 -4,381.8 -4,311.8 -4,241.8 -4,171.8 -4,101.8 -4,031.8 -3,961.8 -3,891.8 -3,821.8 -3,751.8 Y(m) -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2
C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49
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Table 9. Pad Coordinates (continued)
NAME C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 PAD 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 X (m) -1,091.8 -1,021.8 -951.8 -881.8 -811.8 -741.8 -671.8 -601.8 -531.8 -461.8 -391.8 -321.8 -251.8 -181.8 175.44 245.44 315.44 385.44 455.44 525.44 595.44 665.44 735.44 805.44 875.44 945.44 1,015.44 1,085.44 1,155.44 1,225.44 1,295.44 1,365.44 1,435.44 1,505.44 1,575.44 1,645.44 1,715.44 Y(m) -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2
Table 9. Pad Coordinates (continued)
NAME C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100 C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C121 C122 C123 PAD 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 X (m) 1,785.44 1,855.44 1,925.44 1,995.44 2,065.44 2,135.44 2,205.44 2,275.44 2,345.44 2,415.44 2,485.44 2,555.44 2,625.44 2,695.44 2,765.44 2,835.44 2,905.44 2,975.44 3,045.44 3,115.44 3,185.44 3,255.44 3,325.44 3,395.44 3,465.44 3,535.44 3,605.44 3,675.44 3,745.44 3,815.44 3,885.44 3,955.44 4,025.44 4,095.44 4,165.44 4,235.44 4,305.44 Y(m) -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2
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Table 9. Pad Coordinates (continued)
NAME C124 C125 C126 C127 R47 R46 R45 R44 R43 R42 R41 R40 R39 R38 R37 R36 R35 R34 R33 R32 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 PAD 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 X (m) 4,375.44 4,445.44 4,515.44 4,585.44 4,943.84 5,013.84 5,083.84 5,153.84 5,223.84 5,293.84 5,363.84 5,433.84 5,503.84 5,573.84 5,643.84 5,713.84 5,783.84 5,853.84 5,923.84 5,993.84 6,021.92 5,951.92 5,881.92 5,811.92 5,741.92 5,671.92 5,601.92 5,531.92 5,461.92 5,391.92 5,321.92 5,251.92 5,181.92 5,111.92 5,041.92 4,971.92 4,901.92 Y(m) -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 -898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2
Table 9. Pad Coordinates (continued)
NAME TEST_3 TEST_2 TEST_1 TEST_0 VSSOUT SEL2 SEL1 OSC VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD3_1 VDD3_2 VDD3_3 VDD2_1 VDD2_2 VDD2_3 VDD2_4 VDD2_5 VDD2_6 VDD2_7 TEST_7 TEST_6 TEST_5 TEST_4
BSY_FLAG
PAD 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214
X (m) 4,640.52 4,500.68 4,360.84 4,221 4,151 4,011.16 3,871.32 3,731.48 3,661.48 3,591.48 3,521.48 3,451.48 3,381.48 3,311.48 3,223.08 3,153.08 3,083.08 2,994.68 2,924.68 2,854.68 2,784.68 2,714.68 2,644.68 2,574.68 2,033.84 1,894 1,754.16 1,614.32 1,474.48 1,333.2 1,193.36 1,053.52 913.68 773.84 634 494.16 354.32
Y(m) 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2
SDIN SD/C SCE SCLK D7 D6 D5 D4
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STE2001
Table 9. Pad Coordinates (continued)
NAME D3 D2 D1 D0 PD/C E RES
SDA_OUT
Table 9. Pad Coordinates (continued)
Y(m) 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 NAME TEST_12 TEST_13 TEST_10 TEST_11 TEST_8 R31 R30 R29 R28 R27 R26 R25 R24 R23 R22 R21 R20 R19 R18 R17 R16 PAD 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 X (m) -4,460.48 -4,540.48 -4,620.48 -4,700.48 -4,780.48 -4,971.92 -5,041.92 -5,111.92 -5,181.92 -5,251.92 -5,321.92 -5,391.92 -5,461.92 -5,531.92 -5,601.92 -5,671.92 -5,741.92 -5,811.92 -5,881.92 -5,951.92 -6,021.92 Y(m) 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2 898.2
PAD 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251
X (m) 214.48 74.64 -65.2 -205.04 -344.88 -484.72 -624.56 -764.4 -904.24 -1,044.08 -1,183.92 -1,722.04 -1,795.48 -1,865.48 -1,935.48 -2,075.88 -2,145.88 -2,215.88 -2,356.28 -2,426.28 -2,496.28 -2,636.68 -2,706.68 -2,776.68 -3,545.64 -3,615.64 -3,685.64 -3,755.64 -3,825.64 -3,895.64 -3,968.08 -4,040.48 -4,110.48 -4,180.48 -4,250.48 -4,320.48 -4,390.48
SDA_IN SCL SA0 TEST9 VSS1_1 VSS1_2 VSS1_3 VSS1_4 VSS1_5 VSS1_6 VSS2_1 VSS2_2 VSS2_3 VSS2_4 VSS2_5 VSS2_6
VLCDOUT1 VLCDOUT2 VLCDOUT3 VLCDOUT4 VLCDOUT5 VLCDOUT6 VLCSENSE
Table 10. Alignment marks coordinates
X 4806.2 -4876.2 -6092.6 6092.6 Y 901.8 901.8 -901.8 -901.8 MARKS mark1 mark2 mark3 mark4
Figure 38. Alignment marks dimensions
VLCDIN_1 VLCDIN_2 VLCDIN_3 VLCDIN_4 VLCDIN_5 VLCDIN_6
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Figure 39.
50.60.25 SCHNITT B-B B DETAIL X 45.90 DETAIL X MASSTAB 5:1
Figure 40. Tray Information
2.54 x 45?
10.75
2 x 14.59 = 29.180.25
4.60 10 2.39
R16
1 0.90
13 x 3.19 = 41.470.25
FLUOROWARE GmbH
DIE IDENTIFICATION
STE2001
STATPROT. 50 1 B NOTES: ENGRAVING TO BE 20 CHAIR x 0.3 WIDE x 0.05 RAISED CENTER ON CENTERLINE 1 0.3 MATERIAL: STATPRO150 BUILD TOOL TO 0.009 MM/MM SHRINK TRAY OR WAFFLE PACK OF STE2000/STE2001 KNOCKDUTS NOT TO EXCEED 0.08 PAD A
D01IN1249
A
DETAIL Y
+0.13 45.59 -0.25
SCHNITT A-A
10
+0.08 2.46 -0.10
12.80
+0.08 3.94 -0.13
D01IN1248
2.18
DETAIL Y MASSTAB 5:1
STE2001
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STE2001
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. N o license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http:/ /www.st.com
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