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2.5 V/3.3 V, 2:1 Multiplexer/ Demultiplexer Bus Switch ADG3248
FEATURES 225 ps Propagation Delay through the Switch 4.5 Switch Connection between Ports Data Rate 1.244 Gbps 2.5 V/3.3 V Supply Operation Level Translation 3.3 V to 2.5 V 2.5 V to 1.8 V Small Signal Bandwidth 610 MHz 6-Lead SC70 Package APPLICATIONS 3.3 V to 2.5 V Voltage Translation 2.5 V to 1.8 V Voltage Translation Bus Switching Docking Stations Memory Switching Analog Switch Applications FUNCTIONAL BLOCK DIAGRAM
ADG3248
A0 B A1
IN
SWITCHES SHOWN FOR A LOGIC 0 INPUT
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG3248 is a 2.5 V or 3.3 V, high performance 2:1 multiplexer/demultiplexer. It is designed on a low voltage CMOS process, which provides low power dissipation yet gives high switching speed and very low on resistance. This allows the input to be connected to the output without additional propagation delay or generating additional ground bounce noise. Each switch of the ADG3248 conducts equally well in both directions when on. The ADG3248 exhibits break-before-make switching action, preventing momentary shorting when switching channels. The ADG3248 is available in a tiny 6-lead SC70 package.
1. 2. 3. 4.
3.3 V or 2.5 V supply operation. Extremely low propagation delay through switch. 4.5 switches connect inputs to outputs. Tiny SC70 package.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
ADG3248-SPECIFICATIONS1
Parameter Symbol DC ELECTRICAL CHARACTERISTICS Input High Voltage VINH VINH Input Low Voltage VINL VINL Input Leakage Current II OFF State Leakage Current IOZ ON State Leakage Current Maximum Pass Voltage VP CAPACITANCE3 A Port Off Capacitance B Port Off Capacitance A, B Port On Capacitance Control Input Capacitance SWITCHING CHARACTERISTICS3 Propagation Delay A to B or B to A, tPD4 Propagation Delay Matching5 Transition Time Break-before-Make Time Maximum Data Rate Channel Jitter DIGITAL SWITCH On Resistance
(VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.)
B Version Typ2 Max
Conditions VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V 0 A, B VCC 0 A, B VCC VA/VB = VCC = 3.3 V, IO = -5 A VA/VB = VCC = 2.5 V, IO= -5 A f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz CL = 50 pF, VCC = 3 V RL = 510 , CL = 50 pF RL = 510 , CL = 50 pF VCC = 3.3 V; VA/VB = 2 V VCC = 3.3 V; VA/VB = 2 V VCC = 3 V, VA = 0 V, IBA = 8 mA VCC = 3 V, VA = 1.7 V, IBA = 8 mA VCC = 2.3 V, VA = 0 V, IBA = 8 mA VCC = 2.3 V, VA = 1 V, IBA = 8 mA VCC = 3 V, VA = 0 V, IA = 8 mA
Min 2.0 1.7
Unit V V V V A A A V V pF pF pF pF
2.0 1.5
0.01 0.01 0.01 2.5 1.8 3.5 4.5 8.5 4
0.8 0.7 1 1 1 2.9 2.1
CA OFF CB OFF CA, CB ON CIN tPHL, tPLH tTRANS tBBM
5
16 10 1.244 45 4.5 12 5 9 0.1
0.225 5 29
ns ps ns ns Gbps ps p-p V A
RON
On Resistance Matching POWER REQUIREMENTS VCC Quiescent Power Supply Current
RON
8 28 9 18 0.5 3.6 1
2.3 ICC Digital Inputs = 0 V or VCC 0.01
NOTES 1 Temperature range is as follows: B Version: -40C to +85C. 2 Typical values are at 25C, unless otherwise stated. 3 Guaranteed by design, not subject to production test. 4 The digital switch contributes no propagation delay other than the RC delay of the typical R ON of the switch and the load capacitance when driven by an ideal voltage source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 5 Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF. Specifications subject to change without notice.
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ADG3248
ABSOLUTE MAXIMUM RATINGS*
(TA = 25C, unless otherwise noted.)
PIN CONFIGURATION 6-Lead SC70
A0 1
6
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +4.6 V Digital Inputs to GND . . . . . . . . . . . . . . . . . -0.5 V to +4.6 V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . -0.5 V to +4.6 V DC Output Current . . . . . . . . . . . . . . . . . 25 mA per Channel Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150C JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 332C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300C IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . . 235C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
IN VCC
ADG3248
GND
2 5
TOP VIEW A1 3 (Not to Scale) 4 B
Table I. Pin Function Descriptions
Pin No. 1 2 3 4 5 6
Mnemonic A0 GND A1 B VCC IN
Description Port A0, Input or Output Ground Reference Port A1, Input or Output Port B, Input or Output Positive Power Supply Voltage Channel Select
Table II. Truth Table
IN L H
Function B = A0 B = A1
ORDERING GUIDE
Model ADG3248BKS-R2 ADG3248BKS-REEL ADG3248BKS-REEL7
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description SC70 (Thin Shrink Small Outline Transistor Package) SC70 (Thin Shrink Small Outline Transistor Package) SC70 (Thin Shrink Small Outline Transistor Package)
Package KS-6 KS-6 KS-6
Branding SMA SMA SMA
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG3248 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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ADG3248
TERMINOLOGY
VCC GND VINH VINL II IOZ IOL VP RON RON CX OFF CX ON CIN ICC tPLH, tPHL tBBM tTRANS Max Data Rate Channel Jitter
Positive Power Supply Voltage. Ground (0 V) Reference. Minimum Input Voltage for Logic 1. Maximum Input Voltage for Logic 0. Input Leakage Current at the Control Inputs. OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state. ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state. Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device when the switch input voltage is equal to the supply voltage. Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified amount of current through the switch. ON Resistance Match between Any Two Channels, i.e., RON max - RON min. OFF Switch Capacitance. ON Switch Capacitance. Control Input Capacitance. This consists of IN. Quiescent Power Supply Current. This current represents the leakage current between the VCC and ground pins. It is measured when all control inputs are at a logic high or low level and the switches are OFF. Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant RON x CL, where CL is the load capacitance. On or Off time measured between the 90% points of both switches when switching from one to another. Time taken to switch from one channel to the other, measured from 50% of the IN signal to 90% of the OUT signal. Maximum Rate at which Data Can Be Passed through the Switch. Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel.
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Typical Performance Characteristics-ADG3248
40 35 30 TA = 25 C
40
VCC = 3V
20
TA = 25 C VCC = 2.3V
VCC = 3.3V
35 30
15
RON ( )
20 15 10 5 0 VCC = 3.6V
RON ( )
VCC = 3.3V
RON ( )
25
25 VCC = 2.5V 20 15 VCC = 2.7V 10 5
10 85 C
5
25 C 40 C
0
0.5
1.0
2.0 1.5 VA/VB (V)
2.5
3.0
3.5
0
0
0.5
1.0
1.5 2.0 VA/VB (V)
2.5
3.0
0
0
0.5
1.0 VA/VB (V)
1.5
2.0
TPC 1. On Resistance vs. Input Voltage
TPC 2. On Resistance vs. Input Voltage
TPC 3. On Resistance vs. Input Voltage for Different Temperatures
15 VCC = 2.5V
3.0 2.5 TA = 25 C IO = -5 A
VCC = 3.6V
2.5 TA = 25 C IO = -5 A 2.0 VCC = 2.7V
RON ( )
VOUT (V)
VOUT (V)
10 85 C
2.0 1.5
VCC = 3.3V VCC = 3V
1.5
VCC = 2.5V VCC = 2.3V
1.0
5 40 C 25 C
1.0
0.5
0.5
0
0
0.5 VA/VB (V)
1.0
1.2
0
0
0.5
1.0
2.0 1.5 VA/VB (V)
2.5
3.0
3.5
0
0
0.5
1.0
2.0 1.5 VA/VB (V)
2.5
3.0
TPC 4. On Resistance vs. Input Voltage for Different Temperatures
TPC 5. Pass Voltage vs. VCC
TPC 6. Pass Voltage vs. VCC
3.0 2.5 TA = 25 C VA = 0V
3.0 2.5 TA = 25 C VA = VCC
0 -0.2 -0.4
QINJ (pC)
TA = 25 C ON = OFF CL = 1nF
VCC = 2.5V
2.0
2.0 VOUT (V)
VCC = 3.3V
VOUT (V)
-0.6 -0.8 -1.0 VCC = 3.3V -1.2 -1.4
1.5
VCC = 2.5V
1.5
1.0
1.0 V = 2.5V CC 0.5
VCC = 3.3V
0.5 0 0 0.02 0.04 0.06 IO (A) 0.08 0.10
0 -0.10
-0.08
-0.06 -0.04 IO (A)
-0.02
0
0
0.5
1.0
1.5 2.0 2.5 VA/VB (V)
3.0
3.5
TPC 7. Output Low Characteristic
TPC 8. Output High Characteristic
TPC 9. Charge Injection vs. Source Voltage
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ADG3248
1 0 -1 ATTENUATION (dB) -2 -3 -4 -5 -6 -7 TA = 25 C VCC = 3.3V/2.5V VIN = 0dBm N/W ANALYZER: RL = RS = 50 0 -10 -20 ATTENUATION (dB) -30 -40 -50 TA = 25 C VCC = 3.3V/2.5V VIN = 0dBm N/W ANALYZER: RL = RS = 50 0 -10 -20 ATTENUATION (dB) -30 -40 -50 TA = 25 C VCC = 3.3V/2.5V VIN = 0dBm N/W ANALYZER: RL = RS = 50
-60 -70 -80 -90
-60 -70 -80 -90
-8 0.03 0.1
1.0 10 100 FREQUENCY (MHz)
1000
-100 0.03 0.1
1.0 10 100 FREQUENCY (MHz)
1000
-100 0.03 0.1
1.0 10 100 FREQUENCY (MHz)
1000
TPC 10. Bandwidth vs. Frequency
TPC 11. Crosstalk vs. Frequency
TPC 12. Off Isolation vs. Frequency
25
100 VCC = 3.3V VA = 1.5V p-p 80 20dB ATTENUATION 90
100 95 VCC = 3.3V 90 V = 1.5V p-p A 85 20dB ATTENUATION 80 75 70 65 60 55
0.7 0.9 1.1 1.3 1.5 1.7 DATA RATE (Gbps) 1.9
20
VCC = 2.5V
JITTER (ps p-p)
15
VCC = 3.3V
60 50 40 30
10
5
20 10
EYE WIDTH (%)
70
tTRANS (ns)
% EYE WIDTH = ((CLOCK PERIOD - JITTER p-p)/CLOCK PERIOD) 100% 0.7 0.9 1.1 1.3 1.5 1.7 DATA RATE (Gbps) 1.9
0 -40
-20
0 20 40 TEMPERATURE ( C)
60
80 85
0 0.5
50 0.5
TPC 13. Transition Time vs. Temperature
TPC 14. Jitter vs. Data Rate; PRBS 31
TPC 15. Eye Width vs. Data Rate; PRBS 31
VCC = 3.3V 38.7mV/DIV 133.7ps/DIV VIN = 2V p-p
20dB ATTENUATION TA = 25 C
VCC = 2.5V 20mV/DIV 166.3ps/DIV VIN = 1V p-p
20dB ATTENUATION TA = 25 C
TPC 16. Eye Pattern; 1.244 Gbps, VCC = 3.3 V, PRBS 31
TPC 17. Eye Pattern; 1 Gbps, VCC = 2.5 V, PRBS 31
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ADG3248
BUS SWITCH APPLICATIONS Mixed Voltage Operation, Level Translation
VOUT 2.5V
SWITCH OUTPUT
3.3V SUPPLY
Bus switches can provide an ideal solution for interfacing between mixed voltage systems. The ADG3248 is suitable for applications where voltage translation from 3.3 V technology to a lower voltage technology is needed. This device can translate from 2.5 V to 1.8 V, or bidirectionally from 3.3 V directly to 2.5 V. Figure 1 shows a block diagram of a typical application in which a user needs to interface between a 3.3 V ADC and a 2.5 V microprocessor. The microprocessor may not have 3.3 V tolerant inputs, therefore placing the ADG3248 between the two devices allows the devices to communicate easily. The bus switch directly connects the two blocks, thus introducing minimal propagation delay, timing skew, or noise.
3.3V 3.3V 2.5V
0V
SWITCH INPUT
VIN 3.3V
Figure 3. 3.3 V to 2.5 V Voltage Translation
2.5 V to 1.8 V Translation
When VCC is 2.5 V and the input signal range is 0 V to VCC, the maximum output signal will, as before, be clamped to within a voltage threshold below the VCC supply. In this case, the output will be limited to approximately 1.8 V, as shown in Figure 5.
2.5V
ADG3248
3.3V ADC
2.5V MICROPROCESSOR
2.5V
ADG3248
1.8V
Figure 1. Level Translation between a 3.3 V ADC and a 2.5 V Microprocessor
3.3 V to 2.5 V Translation
When VCC is 3.3 V and the input signal range is 0 V to VCC, the maximum output signal will be clamped to within a voltage threshold below the VCC supply. In this case, the output will be limited to 2.5 V, as shown in Figure 3. This device can be used for translation from 2.5 V to 3.3 V devices and also between two 3.3 V devices.
3.3V
Figure 4. 2.5 V to 1.8 V Voltage Translation
VOUT 1.8V 2.5V SUPPLY
SWITCH OUTPUT
0V
SWITCH INPUT
VIN 2.5V
3.3V
2.5V
Figure 5. 2.5 V to 1.8 V Voltage Translation
Analog Switching
ADG3248
2.5V 2.5V
Figure 2. 3.3 V to 2.5 V Voltage Translation
Bus switches can be used in many analog switching applications, for example, video graphics. Bus switches can have lower on resistance, smaller ON and OFF channel capacitance, and thus improved frequency performance than their analog counterparts. The bus switch channel itself, consisting solely of an NMOS switch, limits the operating voltage (see TPC 1 for a typical plot), but in many cases, this does not present an issue.
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ADG3248
Multiplexing
Many systems, such as docking stations and memory banks, have a large number of common bus signals. Common problems faced by designers of these systems include * * Large delays caused by capacitive loading of the bus Noise due to simultaneous switching of the address and data bus signals
MEMORY ADDRESS
MEMORY BANK A
DATA
MEMORY BANK B
MEMORY BANK C
Figure 6 shows an array of memory banks in which each address and data signal is loaded by the sum of the individual loads. If a bus switch is used as shown in Figure 7, the output load on the memory address and data bits is halved. The speed at which the selected bank's data can flow is much improved because the capacitance loading is halved and the switches introduce negligible propagation delay. Bus noise is also reduced.
MEMORY BANK D
Figure 6. All Memory Banks Are Permanently Connected to the Bus
ADG3248 ADG3248
MEMORY BANK A
MEMORY ADDRESS
DATA
MEMORY BANK B
MEMORY BANK C
MEMORY BANK D
Figure 7. ADG3248 Used to Reduce Both Access Time and Noise
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ADG3248
OUTLINE DIMENSIONS 6-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-6)
Dimensions shown in millimeters
2.00 BSC
6
5 2
4
1.25 BSC
1 3
2.10 BSC
PIN 1 0.65 BSC 1.30 BSC 1.00 0.90 0.70 1.10 MAX 0.22 0.08 0.30 0.15 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-203AB SEATING PLANE 8 4 0
0.10 MAX
0.46 0.36 0.26
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C04404-0-10/03(0)

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