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HANBit
HMS12864F8VL
SRAM MODULE 1MByte (128K x 64 bit), 120-Pin SMM, 3.3V Part No. HMS12864F8VL
GENERAL DESCRIPTION
The HMS12864F8VL is a high-speed static random access memory (SRAM) module containing 131,072 words organized in a x 64-bit configuration. The module consists of eight 128K x 8 SRAMs mounted on a 120-pin, both-sided, FR4-printed circuit board. Byte write enable inputs,(/WE0,/WE1,/WE2,/WE3,/WE4,/WE5,/WE6,/WE7) are used to enable the module's 8 bits independently. Output enable(/OE) and write enable(/WE) can set the memory input and output. Data is written into the SRAM memory when write enable (/WE) and chip enable (/CE) inputs are both LOW. accomplished when /WE remains HIGH and /CE and output enable (/OE) are LOW. For reliability, this SRAM module is designed as multiple power and ground pin. All module components may be powered from a single +3.3V DC power supply and all inputs and outputs are fully TTL-compatible. Reading is
FEATURES
w Access times : 70 and 100ns w High-density 1MByte design w High-reliability, high-speed design w Single + 3.3V 0.3V power supply w Easy memory expansion with /CE and /OE functions w All inputs and outputs are TTL-compatible w Industry-standard pin-out w FR4-PCB design PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Vcc DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 Vcc DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 Vcc /WE0 /WE1 /WE2 /WE3 /WE4 Vcc /WE5 /WE6 /WE7 /CS2 Vcc P1 Symbol
PIN ASSIGNMENT
P2 Symbol Vss DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Vss DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 Vss A0 A1 A2 A3 A4 Vss A5 A6 A7 /CS1 Vss PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol Vcc DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 Vcc DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 Vcc A16 A15 A14 A13 A12 Vcc A11 A10 A9 A8 Vcc PIN 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Symbol Vss DQ63 DQ62 DQ61 DQ60 DQ59 DQ58 DQ57 DQ56 Vss DQ55 DQ54 DQ53 DQ52 DQ51 DQ50 DQ49 DQ48 Vss NC NC /OE NC NC Vss NC NC NC NC Vss 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 PIN
OPTIONS
w Timing 70ns access 100ns access
MARKING
- 70 -100
w Packages 120-pin SMM F
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FUNCTIONAL BLOCK DIAGRAM
64 17
A0 - A16 A0-16 DQ 0-7 /CE /OE /WE /WE0 A0-16 DQ 8-15 /CE /OE /WE /WE1 A0-16 DQ16-23 /CE /OE /WE /WE2 A0-16 DQ24-31 /CE /OE /CE /OE /WE /WE3 A0-16 A0-16 A0-16
HMS12864F8VL
DQ0 - DQ63
DQ 32-39 /CE /OE /WE U5
U1
A0-16 DQ 40-47 /CE /OE /WE
U2
U6
DQ48-55 /CE /OE /WE
U3
U7
DQ56-63 /CE /OE /WE
U4
U8
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ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature Operating Temperature SYMBOL VIN,OUT VCC PD TSTG TA
HMS12864F8VL
RATING -0.5V to Vcc+0.5V -0.3V to 4.6V 8.0W oC to +150oC -65 0oC to +70oC
w Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS ( TA=0 to 70 o C )
PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage * SYMBOL VCC VSS VIH VIL MIN 3.0V 0 2.2 -0.3* TYP. 3.3V 0 MAX 3.6V 0 Vcc+0.3V** 0.6V
VIL(Min.) = -2.0V ac (Pulse Width 10ns) for I 20 mA
** VIH(Min.) = Vcc+2.0V ac (Pulse Width 10ns) for I 20 mA
DC AND OPERATING CHARACTERISTICS (1)(0oC TA 70 oC ; Vcc = 3.3V 10% )
PARAMETER Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage * Vcc=3.3V, Temp=25 oC TEST CONDITIONS VIN=Vss to Vcc /CE=VIH or /OE =VIH or /WE=VIL VOUT=Vss to VCC IOH = -4.0Ma IOL = 8.0mA SYMBOL ILI IL0 VOH VOL MIN -8 -8 2.4 0.4 MAX 8 8 UNITS A A V V
DC AND OPERATING CHARACTERISTICS (2)
DESCRIPTION TEST CONDITIONS Min. Cycle, 100% Duty /CE=VIL, VIN=VIH or VIL, IOUT=0mA Min. Cycle, /CE=VIH f=0MHZ, /CEVCC-0.2V, VIN VCC-0.2V or VIN0.2V ISB ISB1 2.4 80 2.4 80 mA uA ICC 32 32 mA SYMBOL MAX 70 100 UNIT
Power Supply Current:Operating Power Supply Current:Standby
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CAPACITANCE (TA =25 oC , f= 1.0Mhz)
DESCRIPTION Input /Output Capacitance Input Capacitance TEST CONDITIONS VI/O=0V VIN=0V SYMBOL CI/O CIN
HMS12864F8VL
MAX 80 64
UNIT pF pF
* NOTE : Capacitance is sampled and not 100% tested
AC CHARACTERISTICS (0oC TA 70 oC ; Vcc = 3.3V 0.3V, unless otherwise specified) Test conditions
PARAMETER Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Output Load VALUE 0.4V to 2.2V 5ns 1.5V See below Output Load (B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
Output Load (A)
VL=1.5V
+3.3V
50 DOUT Z0=50 30pF DOUT 353
319 5pF*
READ CYCLE
70 PARAMETER Read Cycle Time Address Access Time Chip Select to Output Output Enable to Output Output Enable to Low-Z Output Chip Enable to Low-Z Output Output Disable to High-Z Output Chip Disable to High-Z Output Output Hold from Address Change Chip Select to Power Up Time Chip Select to Power Down Time SYMBOL MIN tRC tAA tCO tOE tOLZ tLZ tOHZ tHZ tOH tPU tPD 5 10 0 0 10 25 25 70 70 70 35 5 10 0 0 15 30 30 MAX MIN 100 100 100 50 MAX ns ns ns ns ns ns ns ns ns ns ns 100 UNIT
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WRITE CYCLE
PARAMETER Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End of Write to Output Low-Z SYMBOL tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW 70 MIN 70 60 0 60 55 0 0 30 0 5 25 MAX
HMS12864F8VL
100 MIN 100 80 0 80 70 0 0 40 0 5 30 MAX
UNIT ns ns ns ns ns ns ns ns ns ns
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(Address Controlled) ( /CE =/ OE = VIL , /WE = VIH)
tRC Address tAA tOH Data out Previous Data Valid Data Valid
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TIMING WAVEFORM OF READ CYCLE ( /CE Controlled )
tRC Address tAA /CE tLZ(4,5) /OE tOLZ Data Out High-Z tPU 50% tOE tCO
HMS12864F8VL
tHZ(3,4,5)
tOHZ
tOH
Vcc Supply Current Notes (Read Cycle)
lCC lSB
tPD 50%
1. /WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ (max.) is less than tLZ (min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with /CE = VIL. 7. Address valid prior to coincident with /CE transition low.
TIMING WAVEFORM OF WRITE CYCLE (/OE=Clock )
tWC Address tAW /OE tCW(3) /CE tAS(4) /WE tDW High-Z Data In tOHZ(6) Data Out
High-Z
tWR(5)
tWP(2)
tDH Data Valid tOW
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TIMING WAVEFORM OF WRITE CYCLE ( /OE Low Fixed )
HMS12864F8VL
Address tAW tCW(3) /CE tAS(4) /WE tWP(2) tDW Data In High-Z Data Valid tWHZ(6,7) Data Out HightOW
(10) (9)
tWR(5)
tOH
tDH
Notes(Write Cycle) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among /CE going low and /WE going low: A write ends at the earliest transition among /CE going high and /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CE going low to the end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CE, or /WE going high. 6. If /OE,/CE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state. 9. DOUT is the read data of the new address. 10. When /CE is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
/CE H L L L /WE X* H H L /OE X H L X MODE Not Select Output Disable Read Write I/O PIN High-Z High-Z DOUT DIN SUPPLY CURRENT l SB, l SB1 lCC lCC lCC
Note: X means Don't Care
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PACKAGING INFORMATION
FRONT SIDE
HMS12864F8VL
REAR SIDE
1.00.08 mm
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ORDERING INFORMATION
HMS12864F8VL
Part Number
Density
Org.
Package
Component Number 8EA 8EA
Vcc
SPEED
HMS12864F8VL-70 HMS12864F8VL-100
1MByte 1MByte
X 64 X 64
120 Pin-SMM 120 Pin-SMM
3.3V 3.3V
70ns 100ns
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