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CT2500 MIL-STD-1397 Type D & E Low Level Serial Interface Protocol Chip
Features
* Performs Source and Sink functions * Implements Type D & E protocols * Burst Mode Capability
A E RO
CIRCUIT TECHNOLOGY
www.aeroflex.com
* Built in System Integrity Features * Double Buffered Communications * Low power CMOS * Available in a PGA Package * Operates over full Military temperature range -55C to +125C
F
LE
X LA
C
ISO 9001
E
RTIFIE D
B
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General Description
The CT2500 provides a complete interface between the MIL-STD-1397 transceiver chip set (CT1698) and most microprocessor based systems. The unit is monolithic and fabricated in CMOS technology, thereby having very low power requirements. The unit handles all protocols of Type D & E interfaces including Burst Mode Data and forced EF functions. Screened per individual test methods of MIL-STD-883. Aeroflex Circuit Technology is an 80,000ft2 MIL-PRF-38534 certified facility in Plainview, N.Y.
BIT4IN
CMDIN DTAIN CFRMSYNC RSTERR
Received SOS/SIS
RXDATA RXCLOCK
Serial Input
Received Data Shift Register
Check Logic
32 BIT BIDIRECTIONAL PARALLEL DATA BUS D0 - D31 CLK SO/SI PAREN POE BURST FIFOEN D/E POR TEST
Received Data Latch
RCVDATA RCVCNTRL ERR1 ERR2 OVRFLOW SYNCIN WIIN PRTYIN STR1
XMIT Data Latch
I/O Contrl
STR2 FIFORD RDYFORDTA G20MHZ TXDMXD TXCMXD ENV
Mode Control Logic
XMIT Data Shift Register Serial Output SOS/SIS for XMIT
WIOUT LDCNTRL BIT4OUT CMDOUT DTAOUT TXSELECT
Figure 1 - Block Diagram eroflex Circuit Technology - Data Bus Modules For The Future (c) SCDCT2500 REV A 6/12/98
I/O CONTROL
The CT2500 is very flexible in it's I/O architecture. The unit can handle 16 bit and 32 bit data and command word loading. In addition, data words can be preloaded into an external FIFO and the unit will load data words from the FIFO directly without subsystem intervention. Similarly, data can be received and automatically loaded into a FIFO. This frees up the subsystem until the data transfer is complete. These options are desirable especially when operating under burst mode transmissions. Control frames are sent by strobing LDCNTRL and data is sent by strobing STR2.
SOURCE AND SINK MODES
Both Source and Sink Mode operations are available in the CT2500. Selection of modes is accomplished through the Source/Sink pin. In the Source Mode, the unit will transmit control frames, 32 bit command and data words including burst mode data. It will receive control frames only. In Sink Mode, the unit will transmit control frames only and receive control frames, 32 bit command and data words, and burst mode data.
SYSTEM INTEGRITY FEATURES
The CT2500 has built in system integrity features. The unit can generate and send parity with all 32 bit transmissions. For reception of 32 bit words, the unit can check for parity, frame, overrun, sync, and bit count errors.
DATA TRANSFERS
The CT2500 is built to send and receive Type D and E Control frames. It can transmit and receive 32-bit command and data word. All 32-bit communications are double buffered for maximum flexibility. This allows the subsystem to respond with less critical timing constraints. Burst mode data transmission can be initiated by setting the "Burst Mode" pin high. Automatic FIFO operation is enabled by setting "FIFOEN" pin high. The serial data out is automatically formatted for the CT1698 to send out along the cable.
ELECTRICAL CHARACTERISTICS
(VDD = 5V 10%, TC = -55 C to +125C, unless otherwise specified)
SYMBOL PARAMETER LIMIT
IDD PDS Iin Ioz VIH VIL VOH VOL
Quiescent current Power Dissipation Input leakage Tri-state leakage Input high level Input low level Output high level Output low level
100uA max 200mW max 10uA max 10uA max 2.0V min 0.8V max 2.4V min @ IOH = -4mA 0.4V max @ IOL = 4mA
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SCDCT2500 REV A 6/12/98 Plainview NY (516) 694-6700
I/O FUNCTION LISTING
NAME SO/SI I/O I DESCRIPTION Source / Sink Mode Select Determines the overall Functioning Mode of the Device. "1"= Source emulation. This mode enables the chip to send control frames, single command and data words and burst data. It is able to receive control frames. "0" = Sink emulation. In this mode, the chip can only send control frames. It can receive control frames, command words, single data words and burst data. Parallel Bi-directional Data Bus (Internal Pullups) Source Mode: Input to 32 bit transmit data latch Sink Mode: Tri-state output from 32 bit received data latch Type D / Type E Control Frame Length Select (Internal Pulldown) "1" = Three bit control frames are transmitted and the received control frame is checked for a proper three bit length. "0" = Four bit control frames are transmitted and the received control frame is checked for a proper four bit length. Parity Enable (Internal Pullup) "1" = Parity bit is generated in Source mode and checked for in Sink mode. "0" = No parity is generated or checked for. Parity Odd or Even Select (Internal Pullup) "1" = Odd parity "0" = Even parity System Clock 20 megahertz with 50% duty cycle Burst Mode Select "1" = Data transmission and Reception can be done in Burst mode "0" = Normal operation Source Mode: Data words loaded during the transmission of another will be concatenated to the transmission without addition of SYNC or WI bits. The first word will have a SYNC bit of "1" and and a WI bit, which must be set to "0". The Burst line must remain stable for the entire duration of the loading and transmission of the data. Sink Mode: During a Burst data reception, after the SYNC and WI bits, data words are picked off at bit count multiples of 32, or 33 with parity enabled, and loaded into the output latch. The transmission is considered ended when a gap is detected. The line must be stable during the entire reception. Strobe One Bar and Strobe Two Bar Control Strobes for Reading and Writing the Parallel I/O data Latches Source Mode: STR1 loads data present on DO-D15 into the lower 16 bit input latch and STR2 loads data on D16-D31 into the upper 16 bit input latch. Upon completion of STR2, a sequence is initiated to load the entire 32 bits into a shift register and start a transmission. The lower 16 bits must be loaded prior to or during the load of the upper 16 bits. For a 32 bit load, STR1 and STR2 can be tied together. Sink Mode: STR1 enables the lower 16 bits of a received word to be output on D0-D15. STR2 enables the upper 16 bits of a received word to be output on D16-D31. The entire 32 bits of data must be read before another data reception or it will be overwritten. If this occurs, the overflow flag, OVRFLOW, will go high. The data is considered completely read upon the completion of STR2. Command In Third bit of the Received Control Frame. Valid during RCVCNTRL. Data In Second bit of the Received Control Frame. Valid during RCVCNTRL.
DO-D31
I/O
D/E
I
PAREN
I
POE
I
CLK BURST
I I
STR1 and STR2
I
CMDIN DTAIN
O O
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SCDCT2500 REV A 6/12/98 Plainview NY (516) 694-6700
I/O FUNCTION LISTING (Continued)
NAME RCVCNTRL RCVDTA ERR1, ERR2 I/O O O O DESCRIPTION Received Control Bar Pulses low upon reception of a Control Frame in both Sink and Source modes. Received Data/Command Word Bar Pulses low upon reception of a Data or Command word Error Bit One and Error Bit Two
ERR1 ERR2 0 1 0 1
0
0 1 1
No Error Bit Count Error in Received Data/Command word or Control Frame Parity Error in Received Data Sync Error in Received Data/Command word or Control Frame
OVRFLOW RSTERR POR
O I I
Overflow Error "1" = Overflow occurred in the Received Data Latch. Data not read in time. Reset Error Flags Bar (Internal Pullup) A low pulse on this line resets the ERR1, ERR2 and OVRFLOW error flags. Power on Reset Bar A Master reset. A low pulse on this line resets the internal sequences and error flags. It does not reset the I/O Data latches. Word Identifier Bit Out The value on this line is latched during STR2 for the WI bit position in the word to be transmitted. A "0" indicates a Data word and a "1" indicates a Command/Interrupt word. Word Identifier Bit In The WI bit of the received word is present on this line during RCVDTA and indicates whether the word is a Data word or a Command/Interrupt word. The value is latched at the first RCVDTA for an entire Burst Mode reception. Command Out Third bit of the transmitted Control Frame. Data Out Second bit of the transmitted Control Frame. Load Control Frame Bar This loads the status of CMDOUT, DTAOUT and BIT4OUT into the Control Frame to be transmitted. Transmission will commence when the loading is completed. This applies to both Sink and Source modes. FIFO Enable Source Mode: When FIFOEN is held high ("1"), FIFORD's (FIFO Read Bars) will be generated when the input data latch is empty (RDYFORDTA = 1). During the FIFORD, data presented to the parallel bus will be loaded into the input data latch and transmitted when ready. In a non-burst (single word) condition, FIFOEN must be removed before RDYFORDTA comes back. A positive pulse of 100 ns duration satisfies this requirement. Sink Mode: The parallel data bus goes active during RCVDTA and will hold for approximately 25 ns after its rising edge. With a FIFO directly connected to the data bus, RCVDTA can be used to load all received words into the FIFO. Gating RCVDTA with WIIN selects only the data words for loading.
WIOUT
I
WIIN
O
CMDOUT DTAOUT LDCNTRL
I I I
FIFOEN
I
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I/O FUNCTION LISTING (Continued)
NAME FIFORD I/O O DESCRIPTION FIFO Read Bar When the device is configured as a Source, this output pulses low during FIFOEN mode enabling data from a FIFO to be loaded into the input data latch for transmission. Ready For Data This signal is high when the input data latch is available for new data to be loaded in. When the data is loaded, RDYFORDTA goes low until the word is dumped into the output shift register. Envelope This output envelopes the serial output data by being high during transmission. Transmit Data / Manchester Data Serial NRZ data out or Manchester Data out depending on the TXSELECT mode. Transmit Clock / Manchester Data Bar Output shift clock or Manchester Data Bar depending on the TXSELECT mode. Gated 20 Mhz A gated 20 Mhz clock used in conjunction with Transmit Data, Transmit Clock and Envelope to generate Manchester data using other Aeroflex encoders such as the CT1698. Transmit Mode Select. (Internal Pulldown) "1" = Serial output format is Manchester Data and Data Bar. "0" = Output will be NRZ Data and Shift Clock. Received Data Received serial NRZ Data in. Received Clock Received Shift Clock In. Test Mode Bar (Internal Pullup) A low on this pin puts the device into an internal wrap-around test mode. Transmit Data and Transmit Clock are internally connected to Received Data and Received Clock. The circuit must be in Source mode and only 32 bit data loads and reads are allowed. In this mode, STR2 loads the full 32 bits for transmission. When this word is wrapped back, RCVDTA will pulse low indicating reception of a data or command word. STR1 enables the received data latch to be read out. Transmission of control frames can also be tested in this mode using the regular LDCNTRL and RCVCNTRL signals. Bit Four In Fourth bit of received Type E control frame. Bit Four Out (Internal Pullup) Fourth bit of Type E control frame to be transmitted. Sync In Sync position of the Received Data Latch. Control Frame Sync In Sync position of the Received Control Frame Latch Parity In Parity bit position of the Received Data Latch.
RDYFORDTA
O
ENV TXDMXD TXCMXD G20MHZ
O O O O
TXSELECT
I
RXDATA RXCLOCK TEST
I I I
BIT4IN BIT4OUT SYNCIN CFRMSYNC PRTYIN
O I O O O
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SCDCT2500 REV A 6/12/98 Plainview NY (516) 694-6700
100ns min
STR1,STR2 LDCNTRL
tF tS tR tH
tF = 10ns min tR = 10ns min
D0-D31, WIOUT CMDOUT, DTAOUT
VALID
15ns max
tS = 20ns min tH = 5ns min 270ns typ
RDYFORDTA
TXDMXD TXCMXD
350ns max
SYNC
100ns
ENV
G20MHZ
50ns
Figure 2 - Transmit Timing Diagram
N N N N = = = = 3 D Type Control Frame 4 E Type Control Frame 34 Data without Parity 35 Data with Parity
RXDATA
N-2
N-1
N
RXCLOCK
100ns
RCVDTA, RCVCNTRL
300ns typ 370ns max
ERR1, ERR2, OVRFLOW
15ns 100ns
VALID
RCVCNTRL, RCVDTA, FIFORD
tF tR
tF = 5ns typ tR = 5ns typ
100ns
STR1, STR2
100ns min
15ns max tF = 10ns max tR = 10ns max
15ns max
RSTERR, POR
tF tR
D0-D31
VALID
Figure 3 - Receive Timing Diagram
Aeroflex Circuit Technology 6 SCDCT2500 REV A 6/12/98 Plainview NY (516) 694-6700
CLK
LDCNTRL
TXDMXD
TXCMXD
ENV
RXDATA
RXCLOCK RCVCNTRL
Figure 4 - Control Frame Transfer Diagram
CLK
STR1
STR2
RDYFORDTA
DATABUS
TXDMXD
TXCMXD
ENV
Figure 5 - Source Data Frame Example Diagram
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SCDCT2500 REV A 6/12/98 Plainview NY (516) 694-6700
CLK STR1 STR2 DATABUS ENV RXDATA RXCLOCK RCVDTA RCVCNTRL ERR1 ERR2 OVERFLOW WIIN SYNCIN PRTYIN PAREN POE
Figure 6 - Sink Data Frame Example Diagram
32 Bit Data Bus
32 Bit Register
Internal Bus
CT2500 Protocol Chip
CT1698 Transceiver
Manchester Encoded Data
32 Bit FIFO
Protocol Control Signals FIFO & Reg. Controls
Logic Sequencer
Address Bits
Address Decoder
System Interrupts
Figure 7 - Typical I/O Board Configuration (Source and Sink Mode)
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PIN OUTS - 84 PIN PGA (CT2500) Pin B2 C2 B1 C1 D2 D1 E3 E2 E1 F2 F3 G3 G1 G2 F1 H1 H2 J1 K1 J2 L1 K2 K3 L2 L3 K4 L4 J5 K5 L5 K6 J6 J7 L7 K7 L6 L8 K8 L9 L10 K9 L11 BURST CLK CMDOUT DTAOUT BIT4OUT RSTERR FIFOEN LDCNTRL POR GND GND SYNCIN RXCLOCK RXDATA SO/SI STR1 STR2 TEST WIOUT D31 CFRMSYNC VDD PAREN D30 D29 D28 D27 D26 D25 D24 BIT4IN VDD VDD D23 D22 D21 D20 D19 D18 D17 D16 GND Signal Pin K10 J10 K11 J11 H10 H11 F10 G10 G11 G9 F9 F11 E11 E10 E9 D11 D10 C11 B11 C10 A11 B10 B9 A10 A9 B8 A8 B6 B7 A7 C7 C6 A6 A5 B5 C5 A4 B4 A3 A2 B3 A1 GND POE D15 D14 D13 D12 D11 D10 D9 GND GND D8 D7 D6 D5 D4 D3 D2 D1 PRTYIN VDD VDD D/E D0 CMDIN DTAIN ENV ERR1 ERR2 FIFORD VDD VDD TXSELECT OVRFLOW RCVCNTRL RCVDTA RDYFORDTA TXCMXD TXDMXD WIIN G20MHZ GND Signal
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SCDCT2500 REV A 6/12/98 Plainview NY (516) 694-6700
CIRCUIT TECHNOLOGY
Ordering Information
Model Number
CT2500
Package
PGA Package
Package Outline - 84 Pin PGA Top View
.100 MAX
o .018
.600 SQ REF LID .002 TYP
.100 TYP Pin #1 Designator (White) .050 REF
Bottom View
1 2 3 4 5
.130 REF
1.120 1.080 SQ
6 7 8 9 10 11 A B C D E F G H J K L
1.010 SQ MAX
Aeroflex Circuit Technology 35 South Service Road Plainview New York 11830
Specifications subject to change without notice.
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Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: 1-(800)THE-1553
SCDCT2500 REV A 6/12/98 Plainview NY (516) 694-6700

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