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| HANBit HMN4M8DV(N) Non-Volatile SRAM MODULE 32Mbit (4,096K x 8-Bit), 40Pin-DIP, 3.3V Part No. HMN4M8DV(N) GENERAL DESCRIPTION The HMN4M8DV Nonvolatile SRAM is a 33,554,432-bit static RAM organized as 4,194,304 bytes by 8 bits. The HMN4M8DV has a self-contained lithium energy source provide reliable non -volatility coupled with the unlimited write cycles of standard SRAM and integral control circuitry which constantly monitors the single 3.3V supply for an out-oftolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the memory until after V CC returns valid and write protection is unconditionally enabled to prevent garbled data. In addition the SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source is switched on to sustain t he memory until after V CC returns valid. The HMN4M8DV uses extremely low standby current CMOS SRAM's, coupled with small lithium coin cells to provide non volatility without long write-cycle times and the write-cycle limitations associated with EEPROM. FEATURES w Access time : 55, 70ns w High-density design : 32Mbit Design w Battery internally isolated until power is applied w Industry-standard 40-pin 4,096K x 8 pinout w Unlimited write cycles w Data retention in the absence of VCC w 5-years minimum data retention in absence of power w Automatic write-protection during power-up/power-down cycles w Data is automatically protected during power loss PIN ASSIGNMENT A21 A20 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VCC A19 NC A15 A17 /WE A13 A8 A9 A11 /OE A10 /CE DQ7 DQ6 DQ5 DQ4 DQ3 NC A21 A20 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NC VCC A19 NC A15 A17 /WE A13 A8 A9 A11 /OE A10 /CE DQ7 DQ6 DQ5 DQ4 DQ3 NC 36-pin Encapsulated Package w Package Option - HMN4M8DV - HMN4M8DVN - 36 Pin DIP Package - 40 Pin DIP Package 40-pin Encapsulated Package URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 1 HANBit Electronics Co.,Ltd HANBit FUNCTIONAL DESCRIPTION HMN4M8DV(N) The HMN4M8DV executes a read cycle whenever /WE is inactive(high) and /CE is active(low). The address specified by the address inputs(A 0-A19) defines which of the 4,194,304 bytes of data is accessed. Valid data will be a vailable to the eight data output drivers within t ACC (access time) after the last address input signal is stable. When power is valid, the HMN4M8DV operates as a standard CMOS SRAM. During power -down and power-up cycles, the HMN4M8DV acts as a nonvolatile memory, automatically protecting and preserving the memory contents. The HMN4M8DV is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs are stable. The later occurring falling edge of /CE or /WE will d etermine the start of the write cycle. The write cycle is terminated by the earlier rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (t WR) before another cycle can be initiated. The /OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled (/CE and /OE active) then /WE will disable the outputs in t ODW from its falling edge. The HMN4M8DV provides full functional capability for V cc greater than 4.5 V and write protects by 4.37 V nominal. Power-down/power-up control circuitry constantly monitors the V cc supply for a power-fail-detect threshold V PFD. When VCC falls below the V PFD threshold, the SRAM automatically write -protects the data. All inputs to the RAM become "don't care" and all outputs are high impedance. As V cc falls below approximately 3 V, the power switching circuit connects the lithium energy soure to RAM to retain d ata. During power-up, when Vcc rises above approximately 3.0 volts, the power switching circuit connects external V cc to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after Vcc exceeds 4.5 volts. BLOCK DIAGRAM PIN DESCRIPTION A0-A19 /OE /WE Power /CE A20-A21 Power - Fail Control Lithium Cell (1M x 8) x 4 SRAM Block CE2 /CE1 /CE CON VCC DQ0-DQ7 A0-A21 : Address Input /CE : Chip Enable VSS : Ground DQ0-DQ7 : Data In / Data Out /WE : Write Enable /OE : Output Enable VCC: Power (+5V) NC : No Connection URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 2 HANBit Electronics Co.,Ltd HANBit TRUTH TABLE MODE Not selected Output disable Read Write /OE X H L X /CE H L L L CE2 X H H H /WE X H H L HMN4M8DV(N) I/O OPERATION High Z High Z DOUT DIN POWER Standby Active Active Active ABSOLUTE MAXIMUM RATINGS PARAMETER DC voltage applied on V CC relative to VSS DC Voltage applied on any pin excluding V CC relative to VSS Operating temperature Storage temperature Temperature under bias Soldering temperature NOTE: SYMBOL VCC VT RATING -0.5V to VCC +0.2V -0.2V to 4.6V 0 to 70C -40 to 85C -65C to 150C -40C to 85C 260C For 10 second Commercial Industrial CONDITIONS TOPR TSTG TBIAS TSOLDER Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. RECOMMENDED DC OPERATING CONDITIONS ( TA= TOPR ) PARAMETER Supply Voltage Ground Input high voltage Input low voltage NOTE: SYMBOL VCC VSS VIH VIL MIN 3.0V 0 2.2 -0.2 2) TYPICAL 3.3V 0 - MAX 3.6V 0 VCC+0.3V 0.6V 1) 1. Overshoot: VCC+2.0V in case of pulse width 20ns. 3. Overshoot and undershoot are sampled, not 100% tested. 2. Undershoot: -2.0V in case of pulse width 20ns. URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 3 HANBit Electronics Co.,Ltd HANBit CAPACITANCE (TA=25 , f=1MHz) DESCRIPTION Input Capacitance Input/Output Capacitance CONDITIONS Input voltage = 0V Output voltage = 0V SYMBOL CIN CI/O MAX 8 10 HMN4M8DV(N) MIN - UNIT pF pF NOTE: 1. Capacitance is sampled, not 100% tested. DC AND OPERATION CHARACTERISTICS (TA= TOPR, VCCmin VCC VCCmax ) PARAMETER Input Leakage Current Output Leakage Current Output high voltage Output low voltage Standby supply current CONDITIONS VIN=VSS to VCC /CE=VIH or /OE=VIH or /WE=VIL IOH=-1.0 mA IOL= 2.1 mA /CE VCC-0.2V Cycle time=Min, 100% duty, II/O=0 , /CE CHARACTERISTICS (Test Conditions) PARAMETER Input pulse levels Input rise and fall times Input and output timing reference levels Output load (including scope and jig) See Figure 1 and 2 VALUE 0 to 3V < 5 ns 1.5V ( unless otherwise specified) Figure 1. Output Load A 1K DOUT 1.9K +5V DOUT 100 +5V 1.9K 5 1K Figure 2. Output Load B URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 4 HANBit Electronics Co.,Ltd HANBit READ CYCLE (TA= TOPR, VCCmin VCC VCCmax ) PARAMETER Read Cycle Time Address Access Time Chip enable access time Output enable to Output valid Chip enable to output in low Z Output enable to output in low Z Chip disable to output in high Z Output disable to output high Z Output hold from address change SYMBOL tRC tACC tACE tOE tCLZ tOLZ tCHZ tOHZ tOH Output load A Output load A Output load A Output load B Output load B Output load B Output load B Output load A CONDITIONS -70 MIN 70 5 5 0 0 10 MAX 70 70 35 25 25 MIN 85 5 0 0 0 10 -85 MAX 85 85 45 35 25 - HMN4M8DV(N) -120 MIN 120 5 0 0 0 10 MAX 120 120 60 45 35 - -150 MIN 150 10 5 0 0 10 MAX 150 150 70 60 50 - UNIT ns ns ns ns ns ns ns ns ns WRITE CYCLE (TA= TOPR, Vccmin Vcc Vccmax ) PARAMETER Write Cycle Time Chip enable to end of write Address setup time Address valid to end of write Write pulse width Write recovery time (write cycle 1) Write recovery time (write cycle 2) Data valid to end of write Data hold time (write cycle 1) Data hold time (write cycle 2) Write enabled to output in high Z Output active from end of write SYMBOL tWC tCW tAS tAW tWP tWR1 tWR2 tDW tDH1 tDH2 tWZ tOW Note 4 Note 4 Note 5 Note 5 Note 1 Note 2 Note 1 Note 1 Note 3 Note 3 CONDITIONS -70 MIN 70 65 0 65 55 5 15 30 0 10 0 5 MAX 25 MIN 85 75 0 75 65 5 15 35 0 10 0 0 -85 MAX 30 -120 MIN 120 100 0 100 85 5 15 45 0 10 0 0 MAX 40 -150 Min 150 100 0 90 90 5 15 50 0 0 0 5 Max 50 UNI T ns ns ns ns ns ns ns ns ns ns ns ns NOTE: 1. A write ends at the earlier transition of /CE going high and /WE going high. 2. A write occurs during the overlap of allow /CE and a low /WE. A write begins at t he later transition of /CE going low and /WE going low. 3. Either t WR1 or tWR2 must be met. 4. Either t DH1 or tDH2 must be met. 5. If /CE goes low simultaneously with /WE going low or after /WE going low, the outpu ts remain in highimpedance state. URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 5 HANBit Electronics Co.,Ltd HANBit DATA RETENTION CHARACTERISTICS (TA= TOPR, VCC=5V) PARAMETER Vcc for data retention Data retention current Data retention set-up time Recovery time SYMBOL VDR IDR tSDR tRDR See CONDITIONS CEVcc-0.2V Vcc=3.0V, CEVcc data retention 0 tRC MIN 1.5 HMN4M8DV(N) TYP. 2 - MAX 3.6 24 - UNIT V uA waveform ms - POWER-DOWN/POWER-UP CYCLE (TA= TOPR, VCC=3.3V) PARAMETER VPFD(max) to VPFD(min) VCC Fail Time VPFD(max) to VSS VCC Fail Time VPFD(max) to VPFD(min) VCC Rise Time Write Protect Time SYMBOL tF tFB tR Delay after Vcc slews down tWPT past VPFD before SRAM is Write-protected. Chip Enable Recovery VSS to VPFD (min) VCC Rise Time tCER 40 120 ms 40 250 ms CONDITIONS MIN 300 150 10 TYP. MAX UNIT ms ms ms tRB 1 - - ms TIMING WAVEFORM - READ CYCLE NO.1 (Address Access)* 1,2 tRC Address tACC tOH DOUT Previous Data Valid Data Valid URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 6 HANBit Electronics Co.,Ltd HANBit - READ CYCLE NO.2 (/CE Access) /CE tACE tCLZ DOUT High-Z *1,3,4 HMN4M8DV(N) tRC tCHZ High-Z - READ CYCLE NO.3 (/OE Access) *1,5 tRC Address tACC /OE tOE DOUT tOLZ High-Z tOHZ Data Valid High-Z NOTES: 1. /WE is held high for a read cycle. 2. Device is continuously selected: /CE = /OE =V IL. 3. Address is valid prior to or coincident with /CE transition low. 4. /OE = V IL. 5. Device is continuously selected: /CE = V IL - WRITE CYCLE NO.1 (/WE-Controlled) *1,2,3 tWC Address tAW tCW /CE tAS /WE tDW DIN tWZ DOUT Data Undefined (1) URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 7 tWR1 tWP tDH1 Data-in Valid tOW High-Z HANBit Electronics Co.,Ltd HANBit HMN4M8DV(N) - WRITE CYCLE NO.2 (/CE-Controlled) *1,2,3,4,5 Address tAS /CE tWP /WE tDW DIN tWZ DOUT Data Undefined (2) High-Z Data-in tDH2 tAW tCW tWR2 NOTE: 1. /CE or /WE must be high during address transition. 2. Because I/O may be active (/OE low) during this period, data input signals of opp osite polarity to the outputs must not be applied. 3. If /OE is high, the I/O pins remain in a state of high impedance. 4. Either t WR1 or tWR2 must be met. 5. Either t DH1 or tDH2 must be met. POWER-DOWN/POWER-UP TIMING VCC 4.75 VPFD tPF VPFD 4.25 VSO tFS tWPT tDR VSO tPU tCER /CE URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 8 HANBit Electronics Co.,Ltd HANBit PACKAGE DIMENSION Dimension A B C D E F G H I J Min 2.070 0.710 0.365 0.015 0.008 0.590 0.017 0.090 0.080 0.120 Max 2.100 0.740 0.375 0.013 0.630 0.023 0.110 0.110 0.150 HMN4M8DV(N) J A I G C D H B E F All dimensions are in inches. ORDERING INFORMATION H M N 4 M 8 D V N - 70 I Temperature Option : Blank : Commercial(0 to 70C) I : Industrial : -40 to 85C Speed Option : 70 = 70ns 85 = 85ns 120 = 120ns 150 = 150ns Package Option : Blank : 36 Pin Dip Package N : 40 Pin Dip Package Operation Voltage : 3.3V Dip type package Device : 4,096K x 8 bit Nonvolatile SRAM HANBit Memory Module URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 9 HANBit Electronics Co.,Ltd |
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