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MC74VHC259 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter
with LSTTL-Compatible Inputs
The MC74VHC259 is an 8-bit Addressable Latch fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL devices while maintaining CMOS low power dissipation. The VHC259 is designed for general purpose storage applications in digital systems. The device has four modes of operation as shown in the mode selection table.. In the addressable latch mode, the data on Data In is written into the addressed latch. The addressed latch follows the data input with all non-addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous state and are unaffected by the Data or Address inputs. In the one-of-eight decoding or demultiplexing mode, the addressed output follows the state of Data In with all other outputs in the LOW state. In the Reset mode, all outputs are LOW and unaffected by the address and data inputs. When operating the VHC259 as an addressable latch, changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode. The MC74VHC259 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the MC74VHC259 to be used to interface 5 V circuits to 3 V circuits. * High Speed: tPD = 7.6 ns (Typ) at VCC = 5 V * Low Power Dissipation: ICC = 2 A (Max) at TA = 25C * High Noise Immunity: VNIH = VNIL = 28% VCC * CMOS-Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load * Power Down Protection Provided on Inputs and Outputs * Balanced Propagation Delays * Pin and Function Compatible with Other Standard Logic Families * Latchup Performance Exceeds 300 mA * ESD Performance: HBM > 2000 V
A0 A1 A2 Q0 Q1 Q2 Q3 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RESET ENABLE DATA IN Q7 Q6 Q5 Q4 MC74VHC259MEL Device MC74VHC259D MC74VHC259DR2 MC74VHC259DT Package SOIC-16 SOIC-16 TSSOP-16 Shipping 48 Units/Rail 2500 Units/Reel 96 Units/Rail 2500 Units/Reel 50 Units/Rail 2000 Units/Reel
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16
9
SOIC-16 D SUFFIX CASE 751B
VHC259 AWLYYWW
1 8
16
9
TSSOP-16 DT SUFFIX CASE 948F
VHC259 AWLYWW
1 8
16
9
SOIC EIAJ-16 M SUFFIX CASE 966
VHC259 ALYW
1 8
A L, WL Y, YY W, WW
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
MC74VHC259DTR2 TSSOP-16 MC74VHC259M SOIC EIAJ-16 SOIC EIAJ-16
Figure 1. Pin Assignment
(c) Semiconductor Components Industries, LLC, 2001
1
April, 2001 - Rev. 2
Publication Order Number: MC74VHC259/D
MC74VHC259
1 2 3 13 4 5 6 7 9 10 11 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NONINVERTING OUTPUTS
ADDRESS INPUTS
A0 A1 A2
DATA IN
RESET ENABLE
15 14
PIN 16 = VCC PIN 8 = GND
Figure 2. Logic Diagram
A0 A1 A2
1 2 3
BIN/OCT 1 2 4 0 1 2 3 4 ID EN R 5 6 7
4 5 6 7 8 10 11 12
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
A0 A1 A2
1 2 3
DMUX 0 2 0 G 7 0 1 2 3 4 ID EN R 5 6 7
4 5 6 7 8 10 11 12
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
13 14 15
13 14 15
Figure 3. IEC Logic Symbol
LATCH SELECTION TABLE Address Inputs
C L L L L H H H H B L L H H L L H H A L H L H L H L H
MODE SELECTION TABLE Enable
L H L H
Latch Addressed
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Reset
H H L L
Mode
Addressable Latch Memory 8-Line Demultiplexer Reset
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MC74VHC259
DATA INPUT
13
D
4
Q0
D
5
Q1
D
6
Q2
D A0 ADDRESS INPUTS 3 TO 8 DECODER D A2
7
Q3
A1
9
Q4
D ENABLE 14
10
Q5
D
11
Q6
D
12
Q7
RESET
15
Figure 4. Expanded Logic Diagram
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MC74VHC259
MAXIMUM RATINGS (Note 1.)
Symbol VCC VIN VOUT IIK IOK IOUT ICC PD TSTG VESD Positive DC Supply Voltage Digital Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Range ESD Withstand Voltage Human Body Model (Note 2.) Machine Model (Note 3.) Charged Device Model (Note 4.) Above VCC and Below GND at 125C (Note 5.) SOIC Package TSSOP SOIC Package TSSOP Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC +0.5 -20 $20 $25 $75 200 180 -65 to +150 >2000 >200 >2000 $300 143 164 Unit V V V mA mA mA mA mW C V
ILATCH-UP qJA
Latch-Up Performance
mA C/W
Thermal Resistance, Junction to Ambient
1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. 2. Tested to EIA/JESD22-A114-A 3. Tested to EIA/JESD22-A115-A 4. Tested to JESD22-C101-A 5. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN VOUT TA tr, tf DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature Range, all Package Types Input Rise or Fall Time VCC = 3.3 V + 0.3 V VCC = 5.0 V + 0.5 V Characteristics Min 2.0 0 0 -55 0 Max 5.5 5.5 VCC 125 20 Unit V V V C ns/V
DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES
Junction Temperature C 80 90 100 110 120 130 140 Time, Hours 1,032,200 419,300 178,700 79,600 37,000 17,800 8,900 Time, Years 117.8 47.9 20.4 9.4 4.2 2.0 1.0 NORMALIZED FAILURE RATE FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 110 C TJ = 130 C TJ = 100 C TJ = 120 C TJ = 80 C 100 TIME, YEARS TJ = 90 C
1 1 10 1000
Figure 5. Failure Rate vs. Time Junction Temperature
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MC74VHC259
DC CHARACTERISTICS (Voltages Referenced to GND)
VCC Symbol VIH VIL VOH Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Maximum High-Level Output Voltage VIN = VIH or VIL IOH = -50 A VIN = VIH or VIL IOL = 4 mA IOL = 8 mA VOL Maximum Low-Level Output Voltage VIN = VIH or VIL IOL = 50 A VIN = VIH or VIL IOL = 4 mA IOL = 8 mA IIN ICC Input Leakage Current Maximum Quiescent Supply Current VIN = 5.5 V or GND VIN = VCC or GND Condition (V) 2.0 3.0to 5.5 2.0 3.0to 5.5 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 0 to 5.5 5.5 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.36 0.36 0.1 4.0 0.1 0.1 0.1 2.0 3.0 4.5 Min 1.5 VCCX 0.7 0.5 VCCX 0.3 1.9 2.9 4.4 2.48 3.8 0.1 0.1 0.1 0.44 0.44 1.0 40.0 A A V TA = 25C Typ Max -55C TA 125C Min 1.5 VCCX 0.7 0.5 VCCX 0.3 Max Unit V V V
V
V
IIIIIIIIIIIIIIIIIIIIIIIIII III IIIII I I I IIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIII III IIIII II IIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII IIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII III IIIII III IIIII II IIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIII I I III I I I I I I I III IIIII III IIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIII I I III I I I I I I I III IIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I III IIIII III IIIII I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25C Typ 6.0 8.5 4.9 7.0 6.0 8.5 4.9 7.0 6.0 8.5 4.9 7.0 6.0 8.5 4.9 7.0 6 TA 85C -55C TA 125C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Symbol Parameter Test Conditions Min Max Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max Max Unit ns tPLH, tPHL Maximum Propagation Delay, g y Data to Output Dt t Ot t (Figures 6 and 11) VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF 8.5 12.5 8.0 10.0 8.5 12.5 8.0 10.0 8.5 12.5 8.0 10.0 8.5 12.5 8.0 10.0 10 11.5 14.5 9.5 11.5 11.5 14.5 9.5 11.5 tPLH, tPHL Maximum Propagation Delay, Address Select to Output (Figures 7 and 11) Maximum Propagation Delay, g y E bl t O t t Enable to Output (Figures 8 and 11) Maximum Propagation Delay, g y Reset to Output R tt O t t (Figures 9 and 11) Maximum Input Capacitance 11.5 14.5 9.5 11.5 11.5 14.5 9.5 11.5 ns tPLH, tPHL 11.5 14.5 9.5 11.5 11.5 14.5 9.5 11.5 ns tPHL 11.5 14.5 9.5 11.5 10 11.5 14.5 9.5 11.5 10 ns CIN pF Typical @ 25C, VCC = 5.0V 30 CPD Power Dissipation Capacitance (Note 6.) pF 6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
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MC74VHC259
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I I II I I II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I I II I I II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I I II I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I II II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII IIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I
TA = 25C TA = 85C Min 5.5 5.5 4.5 3.0 2.0 2.0 Max TA = 125C Min 5.5 5.5 4.5 3.0 2.0 2.0 Max Min Typ SymbolIIIIIIIIIIII Test ConditionsIII Parameter Minimum Pulse Width, Reset or Enable , (Figure 10) (Fi VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V 5.0 5.0 4.5 3.0 2.0 2.0 Max Unit ns ns ns ns tw tsu th Minimum Setup Time, Address or Data to Enable , (Figure 10) (Fi Minimum Hold Time, Enable to Address or Data , (Figure 8 or 9) (Fi Maximum Input, Rise and Fall Times , (Fi (Figure 6) tr, tf 400 200 300 100 300 100 VCC tr tf DATA IN GND VCC GND VCC tPHL 50% GND VCC 50% DATA IN tPLH 50% OUTPUT Q OUTPUT Q tPHL 50% tPHL GND ADDRESS SELECT 50%
Figure 6. Switching Waveform
VCC DATA IN tw ENABLE 50% tPHL OUTPUT Q tw 50% 50% tPHL GND OUTPUT Q GND VCC DATA IN RESET
Figure 7. Switching Waveform
VCC GND tw 50% tPHL 50% VCC GND
Figure 8. Switching Waveform
Figure 9. Switching Waveform
DATA IN OR ADDRESS SELECT ENABLE
50% tsu 50% th(H) tsu th(H)
VCC GND VCC GND
TEST POINT OUTPUT DEVICE UNDER TEST CL*
*Includes all probe and jig capacitance
Figure 10. Switching Waveform
Figure 11. Test Circuit
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MC74VHC259
PACKAGE DIMENSIONS
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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CCC EE CCC EE
-W-
MC74VHC259
PACKAGE DIMENSIONS
SOIC EIAJ-16 M SUFFIX CASE 966-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
DIM A A1 b c D E e HE L LE M Q1 Z
MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --0.78
INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.031
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MC74VHC259/D

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