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EM MICROELECTRONIC - MARIN SA
V6116
Digitally Programmable 2, 4 and 8 Mux LCD Driver
Description The V6116 is a universal low multiplex LCD driver. The 2, 4 and 8 way multiplex is digitally programmable by the command byte. The display refresh is handled on chip via 2 selectable 8 x 40 RAMs which holds the LCD content driven by the driver. LCD pixels (or segments) are addressed on a one to one basis with the 8 x 40 bit RAM (a set bit corresponds to an activated LCD pixel). Due to the very low driver impedance, the V6116 is designed to be proved in large pixel size applications. Using the TAB tools, the V6116 can be easily cascaded and it can be provided in very large display applications by using the column only driver command COL . The very low current consumption, the extremely large voltage range and the extremely wide temperature range give the V6116 a real advantage for a wide range of applications. Versions V6116 060 with internal bias resistor V6116 020 without internal bias resistor When using the version 020 (without internal bias resistor) in mux mode 4, V3 has to be connected to VSS Features V6116 mux mode 2 with 2 rows and 38 columns V6116 mux mode 4 with 4 rows and 36 columns V6116 mux mode 8 with 8 rows and 32 columns Low dynamic current, 250 A max. Low standby current, 1 A max. at +25C Voltage bias and mux signal generation on chip 2 display RAMs addressable as 8 x 40 words Display refresh on chip, dual RAM for display storage: 2 x (2x38; 4x36; 8x32) Column driver only mode to have 40 column outputs Dual RAM for display storage: 2x (2; 4; 8x40) Crossfree cascadable for large LCD applications Separate logic and LCD supply voltage pins Wide power supply range: VDD: 2 to 6V, VLCD: 2 to 9V Blank function for LCD blanking by data, BLANK bit and STR signal (STR only if internal bias) All segments ON by data and SET bit Bit mapped Serial interface No busy state LCD updating synchronized to the LCD refresh signal TAB and bumped die form delivery. Other form delivery on request -40 to + 85 C temperature range
Typical Operating Configuration
Pad Assignment QFP52
See Fig. 16 for TAB pinout
Fig. 1 Fig. 2
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Absolute Maximum Ratings Parameter Symbol Conditions Supply voltage range VDD -0.3V to 9V LCD supply voltage range VLCD -0.3V to 9.5V Voltage at DI, DO, CLK, STR, -0.3V to VLOGIC VDD+0.3V FR, COL -0.3V to VLCD + Voltage at V1 to V3, S1 to S40 VDISP 0.3V Storage temperature range TSTO -65 to +150C Electrostatic discharge max. to MIL-STD-883C method 3015.7 VSmax 1000V with ref. to VSS Maximum soldering conditions TSmax 290C x 10s
Table 1
Handling Procedures This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the voltage range. Unused inputs must always be tied to a defined logic voltage level. Operating Conditions Parameter Symbol Min Operating TA -40 Temperature Logic supply voltage VDD 2 LCD supply voltage VLCD 2 Typ 5 5 Max Unit +85 C 6 9 V V
Table 2
Stresses above these listed maximum ratings may cause permanent damages to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction.
Electrical Characteristics VDD = 5V 10%, VLCD = 2 to 7V and TA = -40 to +85C, unless otherwise specified Parameter Symbol Test Conditions Min. Dynamic supply current ILCD See note 1 Dynamic supply current IDD See note 1 at TA = 25C Dynamic supply current IDD See note 1 Dynamic supply current IDD See note 2 Standby supply current ISS See note 3 at TA = 25C Control Signals DI, CLK, STR, FR and COL Input leakage IIN 0 < VIN < VDD Input capacitance CIN at TA = 25C Low level input voltage VIL 0 High level input voltage for DI, STR, VIH 2.0 FR and COL High level input voltage for CLK VIH 3.0 Data Output DO High level output voltage VOH IH = 4 mA 2.4 Low level output voltage VOL IL = 4 mA Driver Outputs S1 ... S40 Driver impedance (note 4) ROUT IOUT = 10A, VLCD = 7V Driver impedance (note 4) ROUT IOUT = 10A, VLCD = 3V Driver impedance (note 4) ROUT IOUT = 10A, VLCD = 2V Bias impedance V1, V2, V3 (note 5) RBIAS IOUT = 10A, VLCD = 7V Bias impedance V1, V2, V3 (note 5) RBIAS IOUT = 10A, VLCD = 3V Bias impedance V1, V2, V3 (note 5) RBIAS IOUT = 10A, VLCD = 2V DC output component VDC see Tables 4a & 4b, VLCD = 5V Note 1: Note 2: Note 3: Note 4:
Typ. 150 0.1 3 200 0.1
Max. 250 1 12 250 1
Units A A A A A
1 8
1000 0.8 VDD VDD
nA pF V V V V V k k k k k k mV
Table 3
0.4 1.0 2.6 7 18 20 24 30 1.5 3.5 24 27 50
All outputs open, STR at VSS, FR = 400 Hz, all other inputs at VDD. All outputs open, STR at VSS, FR = 400 Hz, fCLK = 1 MHz, all other inputs at VDD. All outputs open, all inputs at VDD. This is the impedance between of the voltage bias level pins (V1, V2 or V3) and the output pins S1 to S40 when a given voltage bias level is driving the outputs (S1 to S40) Note 5: This is the impedance seen at the segment pin. Outputs measured one at a time.
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Column Drivers Outputs FR Polarity S1 to S40 logic 1 S1 to S40 logic 0 S1 to S40 S1 to S40 logic 1 logic 0
COL logic 0 logic 0
Column Data logic 1 logic 1 logic 0 logic 0

Measured* Sx* - VSS VLCD - Sx* VLCD - Sx* Sx* - VSS
Guaranteed
logic 0 logic 0
| VLCD - Sx* | = | Sx* - VSS | 25 mV | VLCD - Sx* | = | Sx* - VSS | 25 mV
Table 4a
*Sx = the output number (ie. S1 to S40) Row Drivers Outputs S1 to Sn* S1 to Sn* S1 to Sn* S1 to Sn*
FR Polarity logic 1 logic 0 logic 1 logic 0
COL logic 1 logic 1
Column Data logic 1 logic 1 logic 0 logic 0

Measured* VLCD - Sx Sx - VSS Sx - VSS VLCD - Sx
Guaranteed
logic 1 logic
| VLCD - Sx | = | Sx - VSS | 25 mV | VLCD - Sx | = | Sx - VSS | 25 mV
Table 4b
*n = the V6116 mux programme number (ie. 2, 4 or 8) Timing Characteristics VDD = 5V 10%, VLCD = 2 to 7V and TA = -40 to +85C Parameter Symbol Test Conditions Clock high pulse width tCH Clock low pulse width tCL Clock and FR rise time tCR Clock and FR fall time tCF Data input setup time tDS Data input hold time tDH Data output propagation tPD CLOAD = 50pF STR pulse width tSTR CLK falling to STR rising tP STR falling to CLK falling tD FR frequency (2/4/8) fFR (note 2) TA = 25C
Min. 120 120
Typ.
Max.
200 200 20 (note 1) 30 (note 1) 100 100 10 200 128/256/512
Units ns ns ns ns ns ns ns ns ns ns Hz
Table 5a
Note 1: tDS + tDH minimum must be 100 ns. If tDS = 20 ns then tDH 80ns. Note 2: V6116 n, FR = n times the desired LCD refresh rate where n is the V6116 mux mode number. VDD = 2 to 6V, VLCD = 2 to 8V and TA = -40 to +85C Parameter Symbol Test Conditions Clock high pulse width tCH Clock low pulse width tCL Clock and FR rise time tCR Clock and FR fall time tCF Data input setup time tDS Data input hold time tDH Data output propagation tPD CLOAD = 50pF STR pulse width tSTR CLK falling to STR rising tP STR falling to CLK falling tD FR frequency (2/4/8) FFR (note 2)
Min. 500 500
Typ.
Max.
200 200 100 (note 1) 150 (note 1) 400 500 10 1 128/256/512
Units ns ns ns ns ns ns ns ns ns s Hz
Table 5b
Note 1: tDS + tDH minimum must be 500 ns. If tDS = 100 ns then tDH 400ns. Note 2: V6116 n, FR = n times the desired LCD refresh rate where n is the V6116 mux mode number.
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Timing Waveforms
Fig. 3
Programmation Data Bits
0 1 Multiplex Ratio
Command Bits 0 to 7 2 3 4 5 W RAM Address (see Fig. 5)
6 SET
7 Blank
0 0 0 1 1
Mux Ratio (bit 0, 1) 1 Mux Mode 0 2 1 4 0 1 8
Bit 6: SET bit forces all column outputs ON Bit 7: Blank bit forces all column outputs OFF Bit 2: When "0", write RAM 1 and read RAM 2. When "0" and RAM-Add = 0 and STR, write RAM 1 and read RAM 1. When "1", write RAM 2 and read RAM1. When "1" and RAM-Add = 0 and STR, write RAM 2 and read RAM 2.
Fig. 4
Data Transfer Cycle V6116 as a row and column driver, 48 bit load cycle, RAM selected address provided by command bits 3 to 5. Command Bits 3 to 5 Mux Mux Mux Mode 2 Mode 4 Mode 8 000 000 000 001 001 001 010 010 011 011 100 101 110 111 Display RAM 1 or 2 LCD Address Row 10000000 Row 1 01000000 Row 2 00100000 Row 3 00010000 Row 4 00001000 Row 5 00000100 Row 6 00000010 Row 7 00000001 Row 8
All mux mode programmations or COL states need 48 bit load cycle.
Fig. 5
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Block Diagram
Note 1: When falling edge of STR and RAM-Add = 0 and FR arrives, then the display selected RAM address 10000000 (which corresponds to row 1) has to be selected by the 8 bit sequencer. Cascaded V6116s are synchronized in this way. The LCD picture restarts from row 1 each time full RAM data are written.
Fig. 6
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Pin Assignment
Name S1..S40 V3 V2 V1 VLCD FR DI DO CLN STR VDD COL VSS Function LCD outputs, see Table 7 LCD voltage bias level 3 (note 1, 2) LCD voltage bias level 2 (note 1) LCD voltage bias level 1 (note 1) Power supply for the LCD AC input signal for LCD driver output Serial data input Serial data output Data clock input Data strobe, blank, synchronize input Power supply for logic Column only driver mode Supply GND
Table 9
Name
COL inactive
V6116 (2) Row1 Row2 Col1 Col2 Col3 Col4 Col5 Col7...38 V6116 (4) Row1 Row2 Row3 Row4 Col1 Col2 Col3 Col5...36 V6116 (8) Row1 Row2 Row3 Row4 Row5 Row6 Row7 Col1...32
COL active
Col1 Col2 Col3 Col4 Col5 Col6 Col7 Col9...40 Table 7
S1 S2 S3 S4 S5 S6 S7 S9-S40
Note 1: The V6116 has internal voltage bias level generation. When driving large pixels, an external resistor divider chain can be connected to the voltage bias level inputs to obtain enhanced display contrast (see Fig. 12, 13 and 14). The external resistor divider ratio should be in accordance with the internal resistor ratio (see Table 8). Note 2: V3 is connected internally to VSS on the V6116 060 mux mode 4.
LCD Voltage Bias Levels
LCD Drive Type
VLCD 0.43R V1 R V2 R V3 0.43R VSS
LCD Bias Configuration
VOP (note 1) VOFF (rms)
VON (rms) VOFF (rms)
V6116 (2) n=2 1:2 MUX
2n
5 Levels
1 1- n
= 3.69
n +1 = 2.41 n -1
V6116 (4) n=4 1:4 MUX
1/3 Bias 4 Levels
3
1+
8 = 1.73 n
VLCD R V1 R V2 R V3 R VSS
V6116 (8) n=8 1:8 MUX
1/4 Bias 5 Levels
4 1+ 3 n
= 3.4
n + 15 = 1.446 n+3
Table 8
Note 1: VOP = VLCD - VSS
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V6116
Row and Column Multiplexing Waveform V6116 (2)
VOP = VLCD - VSS, VSTATE = VCOL - VROW
Fig. 7
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Row and Column Multiplexing Waveform V6116 (4)
VOP = VLCD - VSS, VSTATE = VCOL - VROW
Fig. 8
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Row and Column Multiplexing Waveform V6116 (8)
VOP = VLCD - VSS, VSTATE = VCOL - VROW
Fig. 9
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V6116
Functional Description Supply Voltage VLCD, VDD, VSS The voltage between VDD and VSS is the supply voltage for the logic and the interface. The voltage between VLCD and VSS is the supply voltage for the LCD and is used for the generation of the internal LCD bias levels. The internal LCD bias levels have a maximum impedance of 25 k for a VLCD voltage from 3 to 8V. Without external connections to the V1, V2, V3 bias level inputs, the V6116 can drive most medium sized LCD (pixel area up to 4'000 mm2). For displays with a wide variation in pixel sizes, the configuration shown in Fig. 13 can give enhanced contrast by giving faster pixel switching times. On changing the row polarity (see Fig. 7, 8 and 9) the parallel capacitors lower the impedance of the bias level generation to the peak current, giving faster pixel charge times and thus a higher RMS "on" value. A higher RMS "on" value can give better contrast. IF for a given LCD size and operating voltage, the "off" pixels appear "on", or there is poor contrast, then an external bias level generation circuit can be used with the V6116. An external bias generation circuit can lower the bias level impedance and hence improve the LCD contrast (see Fig. 12). The optimum values of R, Rx and C, vary according to the LCD size used and VLCD. They are best determined through actual experimentation with the LCD. For LCD with very large average pixel area (eg. up to 10'000 mm2), the bias level configuration shown in Fig. 14 should be used. When V6116s are cascaded, connect the V1, V2 and V3 bias inputs as shown in Fig. 10. The pixel load is averaged across all the cascaded drivers. This will give enhanced display contrast as the effective bias level source impedance is the parallel combination of the total number of drivers. For example, if two V6116 are cascaded as shown in Fig. 10, then the maximum bias level impedance becomes 12.5 k for a VLCD voltage from 3 to 8V. Table 8 shows the relationship between V1, V2 and V3 for the multiplex rates 2, 4 and 8. Note that VLCD > V1 > V2 > V3 for the V6116 2 and V6116 8, and for the V6116 4, VLCD > V1 > V2 and V3 = VSS. Data Input /Output The data input pin, DI, is used to load serial data into the V6116. The serial data word length is 48 bits. Data are loaded in inverse numerical order, the data for bit 48 is loaded first and the data for bit 1 last. The column data bits are loaded first and then the command bits (see Fig. 5). The data output pin, DO, is used in cascaded applications (see Fig. 10). DO transfers the data to the next cascaded chip. The data at DO is equal to the data at DI delayed by 48 clock periods. In order to cascade V6116s, the DO of one chip must be connected to DI of the following chip (see Fig. 10). In cascaded applications the data for the last V6116 (the one that does not have DO connected) must be loaded first and the data for the first V6116 (its DI is connected to the processor) loaded last (see Fig. 10). The display selected RAM word length is 40 bits (see Fig. 6). Each LCD row has a corresponding display RAM address which provides the column data (on or off) when the row is selected (on). When downloading data to the V6116, any display selected RAM address can be chosen. Display selected RAM address is given by command bits 3 to 5, the RAM is selected with the command bit 2. If bit 2 = 0, then RAM 1 can be written and RAM 2 is read. When falling edge of STR and RAMCopyright (c) 2005, EM Microelectronic-Marin SA
Add = 0, then RAM 1 will be read. If bit 2 = 1, then RAM 2 can be written and RAM 1 is read. When falling edge of STR and RAM-Add = 0, then RAM 2 will be read. This last sequence synchronizes the V6116s when cascaded. Bit 7 forces all column outputs at 0L (display OFF). Bit 6 forces all column outputs at 1L (display ON). When bit 6 (SET) and bit 7 (BLANK) are active, the BLANK function has priority. The command bits, bit 6 and bit 7, are activated when logic 1. The command bits, bit 1 and bit 0, define the mux mode (see Fig. 4).
CLK Input The CLK input is used to clock the DI serial data into the shift register and to clock the DO serial data out. Loading and shifting of the data occurs at the falling edge of this clock, outputting of the data at the rising edge (see Fig. 3). When cascading devices, all CLK lines should be tied together (see Fig. 10). STR Input The STR input is used to write to the display RAM, to blank the LCD (V6116 060), and to synchronize cascaded V6116s. The STR input writes the data loaded into the shift register, on the DI input, to the display selected RAM on the falling edge of the STR signal. The STR input when high blanks the LCD by disconnecting the internal voltage bias generation from the VSS potential (V6116 060). Segment outputs S1 to S40 (rows and columns) are pulled up to VLCD. The delay to driving the LCD with VLCD on S1 to S40, is dependent on the capacitive load of the LCD and is typically 1 s. An LCD pixel responds to RMS voltage and takes approximately 100 ms to turn on or off. The delay from putting STR high to the LCD being blank is dependent on the LCD off time and is typically 100 ms. In applications which have a long STR pulse width (10 s) the LCD is driven by VLCD on both the rows and columns during this time. As the time is short (1 s), it will have zero measurable effect on the RMS "on" value (over 100 ms) of an LCD pixel and also zero measurable effect on the pixel DC component. Such STR pulses will not be visible to the human eye on an LCD. Note: if an external voltage bias generation circuit is used as shown in Fig. 12 to 14, the LCD blank function (STR high) will not blank the LCD. Fig. 15 (only available for the V6116 060, with internal resistor) shows how to do a BLANK with the external resistor divider bias by STR signal. When STR is high, the LCD will be driven by the parallel combination of the external voltage bias generation circuit and part of the internal voltage bias generation circuit. The STR input is used also to synchronize the V6116's circuit when cascaded. The synchronization occurs on the falling edge of the STR signal, provided bit 6 and 7 preset to 11. The synchronization will set effective on the next falling edge of the FR signal. A time frame begins with row 1 and so the LCD picture is rebuilt from row 1 each time cascaded V6116s are synchronized. When cascading devices, all STR lines must be tied together (see Fig. 10). FR Input The FR signal controls the segment output frequency generation (see Fig. 7, 8 and 9). To avoid having DC on the display, the FR signal must have a 50% duty cycle. The frequency of the FR signal must be n times the desired display refresh rate, where n is the V6116 mux mode no. (2, 4 or 8). For example, if the desired refresh rate is 40 Hz, the FR signal frequency must be 320 Hz for
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the V6116 8. A selected row (on) is in phase with the FR signal (see Fig. 7, 8 and 9). It is recommended that data transfer to the V6116 should be synchronized to the FR signal to avoid a falling or rising edge on the FR signal while writing data to the V6116. The LCD pixels change polarity with the FR signal. On the edges of the FR signal current spikes will appear on the VSS and VLCD supply lines. If the supply lines have high impedance then voltage spikes will appear. These voltage spikes could interfere with data loading on the DI and CLK pins. The V6116 has filters in order to reduce perturbation on the input signals. It is also recommended that data transfer to the V6116 should be synchronized to the FR signal to avoid DC component which may especially appear during Blink function.
Driver Outputs S1 to S40 There are 40 LCD driver outputs on the V6116. When COL is inactive, the outputs S1 to Sn function as row drivers and the outputs S(n+1) to S40 function as column drivers, where n is the V6116 mux mode no. (2, 4 or 8). When COL is active, all 40 outputs function as column drivers (see Table 6). There is a one to one relationship between the display selected RAM and the LCD driver outputs. Each pixel (segment) driven by the V6116 on the LCD has a display RAM bit which corresponds to it. Setting the bit turns the segment "on" and clearing it turns it "off".
COL Input The V6116 functions as a row and column driver while the COL input is inactive. When active, the COL input configures the V6116 to function as a column driver only. The former row outputs function as column outputs. In cascaded applications, one V6116 should be used in the row and column configuration ( COL inactive) and the rest
as pure column drivers ( COL active) (see Fig. 10). Note: when cascading V6116s never cascade one mux mode no. with another. If a V6116 mux mode 8 is used to drive the rows, then only V6116s mux mode 8 can be cascaded with it (see Fig. 10).
Power Up On power up the data in the shift registers, the two display RAMs and the 40 bit display latches are undefined. The STR input and the command bit 7 should be taken high on power up to blank the display, then the display data written to the display selected RAM (see Fig. 11). When finished the initial write to the display selected RAM, take the STR input low to display the display selected RAM contents (see also section "STR Input").
Applications Two V6116 Mux Mode 8 Cascaded
By connecting the V1, V2 and V3 bias outputs as shown, the pixel load is averaged across all the drivers. The effective bias level source impedance is the parallel combination of the total number of drivers. For example, if two V6116 are cascaded as above, then the maximum bias level impedance becomes 12.5 k.
Fig. 10
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Microprocessor Interface and LCD Blanking
1) When the microprocessor is reset, the port pin will be configured as an input and so the STR line would float. The pull-up resistor will ensure that the LCD is blank while the system reset line is active and after until the port pin is set up by software.
Writing Data to the Display RAM while keeping the LCD Blank
Fig. 11
V6116 with External Resistor Divider Bias Generation
Example set values: R = 3.3 - 10 k C = 2.2 - 47 nF Rx is given by the formula: Rx = 4R ((VDISP/VLCD)-1) = 10 - 30 k
Fig. 12
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Enhancing Switching from the V6116 Temperature compensation/ Contrast adjustment Bias Configuration for Large LCD
Large LCD example: VOP = 5V, average pixel active area = up to 10'000 mm2, display refresh rate = 64 Hz C = 1F Rx is given by the formula Rx = 4(24 k) ((VDISP/VLCD)-1)
Fig. 13
For a single V6116 mux mode 4 driving of such an LCD, the voltage follower buffer (opamp) requirement is: peak current 1.8 mA steady state current typically 150 A
Fig. 14
LCD Blank with External Resistor Divider Bias Generation (only available for the V6116 060)
Fig. 15
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Package and Ordering Information
Dimensions of TAB Package
All dimensions in mm
Fig. 16
Dimensions of QPF Package
All dimensions in mm
Fig. 17
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V6116
Dimensions of the Chip
All dimensions in micron Bump height : 25 microns Chip size is X = 3784 by Y = 2946 microns or X = 149 by Y = 116 mils Note: The origin (0,0) is the lower left coordinate of center pads The lower left corner of the chip shows the distances to the origin
Fig. 18
Ordering Information When ordering, please specify the complete Part Number Part Number Package / Die Form Delivery Form Bumping With gold bumps With gold bumps /
V6116V6WP11E V6116V6WP27E V6116V60TBA-3041
Die in waffle pack, 11 mils thickness Die in waffle pack, 27 mils thickness TAB (Tape Automated Bonding), film A
For other delivery form (QFP52 package or version 20), please contact EM Microelectronic-Marin S.A. Minimum order quantity might apply.
EM Microelectronic-Marin SA (EM) makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in EM's General Terms of Sale located on the Company's web site. EM assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of EM are granted in connection with the sale of EM products, expressly or by implications. EM's products are not authorized for use as components in life support devices or systems. (c) EM Microelectronic-Marin SA, 03/05, Rev. H Copyright (c) 2005, EM Microelectronic-Marin SA 15 www.emmicroelectronic.com

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