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White Electronic Designs
W3HG64M72EER-AD7
ADVANCED*
512MB - 64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM
FEATURES
244-pin, very low profile dual in-line memory module (VLP Mini-DIMM) Fast data transfer rates: PC2-3200, PC2-4200, PC2-5300*, and PC2-6400* Supports ECC error detection and correction VCC = VCCQ = 1.8V 0.1V VCCSPD = 1.7V to 3.6V Differential data strobe (DQS, DQS#) option Four-bit prefetch architecture Programmable CAS# latency (CL) Posted CAS# additive latency (AL) On-die termination (ODT) Programmable burst lenghts: 4 or 8 Serial Presence Detect (SPD) with EEPROM Auto and Self Refresh Capability (64ms: 8,192 cycle refresh) Gold (Au) edge contacts RoHS compliant Single Rank Package option * 244 Pin Mini-DIMM * PCB - 18.29mm (0.72")
DESCRIPTION
The W3HG64M72EER is a 64Mx72 Double Data Rate DDR2 SDRAM high density module. This memory module consists of nine 64Mx8 bit with 4 banks DDR2 Synchronous DRAMs in FBGA packages, mounted on a 244-pin DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. NOTE: Consult factory for availability of: * Vendor source control options * Industrial temperature option * Parity option
OPERATING FREQUENCIES
PC2-3200 Clock Speed CL-tRCD-tRP
* Contact factory for availability
PC2-4200 266MHz 4-4-4
PC2-5300* 333MHz 5-5-5
PC2-6400* 400MHz 6-6-6
200MHz 3-3-3
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PIN CONFIGURATION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Symbol VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS RESET# NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3# DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8# DQS8 VSS CB2 CB3 VSS NC VCCQ CKE0 VCC NC NC/ERR_ OUT VCCQ A11 A7 VCC A5 Pin No. 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 Symbol A4 VCCQ A2 VCC VSS VSS NC/PAR_IN VCC A10/AP BA0 VCC WE# VCCQ CAS# VCCQ NC NC VCCQ NC VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7# DQS7 VSS DQ58 DQ59 VSS SA0 SA1 Pin No. 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 Symbol VSS DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS NC NC VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8 NC VSS CB6 CB7 VSS NC VCCQ NC VCC NC NC VCCQ A12 A9 VCC A8 A6 Pin No. 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 Symbol VCCQ A3 A1 VCC CK0 CK0# VCC A0 BA1 VCC RAS# VCCQ S0# VCCQ ODT0 A13 VCC NC VSS DQ36 DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS NC NC VSS DM6 NC VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS SDA SCL VCCSPD
W3HG64M72EER-AD7
ADVANCED
PIN NAMES
Pin Name A0-A13 BA0,BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS8 DQS0#-DQS8# ODT0 CK0,CK0# CKE0 S0# RAS# CAS# WE# RESET# DM (0-8) VCCSPD VCC VCCQ A10/AP VSS PAR_IN ERR_OUT SA0-SA2 SDA SCL NC VREF Function Address Inputs SDRAM Bank Address Data Input/Output Check Bits Data strobes Data strobes complement On-die termination control Clock Inputs, positive line Clock Enables Chip Selects Row Address Strobe Column Address Strobe Write Enable Register Reset Input Data Masks SPD Power Core Power I/O Power Address Input/Auto Precharge Ground Parity bit for the addess and control bus Parity error found on the address and control bus SPD address SPD Data Input/Output Clock Input No connect Input/Output Reference
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FUNCTIONAL BLOCK DIAGRAM
RS0# DQS0 DQS0# DM0
DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS# DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
W3HG64M72EER-AD7
ADVANCED
DQS4 DQS4# DM4
DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS#
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQS1 DQS1# DM1
DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS#
DQS5 DQS5# DM5
DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS#
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQS2 DQS2# DM2
DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS#
DQS6 DQS6# DM6
DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS#
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQS3 DQS3# DM3
DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS#
DQS7 DQS7# DM7
DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS#
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQS8 DQS8# DM8
DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS#
VCCSPD VCC/VCCQ VREF VSS
Serial PD DDR SDRAMs DDR SDRAMs DDR SDRAMs
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
Serial PD SCL WP A0 A1 A2 SDA
S0# BA0 - BA1 A0 - A13 RAS# CAS# WE# CKE0 ODT0 RESET# CK CK#
R E G I S T E R
RST#
RS0#
S0# DDR2 SDRAMs BA0 - BA1 DDR2 SDRAMs A0 - A13 DDR2 SDRAMs DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM Register
RBA0 - RBA1 RA0 - RA13 RRAS# RCAS# RWE# RCKE0 RODT0
SA0 SA1 SA2
RAS# DDR2 SDRAMs RCAS# DDR2 SDRAMs WE# DDR2 SDRAMs CKE0 DDR2 SDRAMs ODT0 DDR2 SDRAMs CK0# RESET# CK0 P L L OE
NOTE: All resistor values are 22 ohms 5% unless otherwise specified.
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DC OPERATING CONDITIONS
All voltages referenced to VSS Parameter Supply voltage I/O Supply voltage VCCL Supply voltage I/O Reference voltage I/O Termination voltage Symbol VCC VCCQ VCCL VREF VTT Min 1 .7 1 .7 1 .7 0.49 x VCCQ VREF-0.04 Typical 1 .8 1 .8 1 .8 0.50 x VCCQ VREF
W3HG64M72EER-AD7
ADVANCED
Max 1 .9 1 .9 1 .9 0.51 x VCCQ VREF + 0.04
Unit V V V V V
Notes 1 4 4 2 3
Notes: 1. VCC and VCCQ must track each other. VCCQ must be less than or equal to VCC. 2. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not excedd 1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed 2 percent of VREF (DC). This measurement is to be taken at the nearest VREF bypass capacitor. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 4. VCCQ tracks with VCC; VCCL track with VCC.
ABSOLUTE MAXIMUM DC RATINGS
Symbol VCC VCCQ VCCL VIN, VOUT TSTG TCASE TOPR Parameter Voltage on VCC pin relative to VSS Voltage on VCCQ pin relative to VSS Voltage on VCCL pin relative to VSS Voltage on any pin relative to VSS Storage temperature Device operating temperature Operating temperature (ambient) Command/Address, RAS#, CAS#, WE#, CS#, CKE CK, CK# DM DQ, DQS, DQS# MIN -1.0 -0.5 -0.5 -0.5 -55 0 0 -5 -5 -5 -5 -18 MAX 2.3 2.3 2.3 2.3 100 85 55 5 5 5 5 18 U nit V V V V C C C A A A A A
IL
Input leakage current; Any input 0VIOZ IVREF
Output leakage current; 0VINPUT/OUTPUT CAPACITANCE
TA=25 0 C, f=1 00MHz Parameter Input capacitance (A0 - A1 3, BA0 - BA1 ,RAS#,CAS#,WE#) Input capacitance ( CKE0), (ODT0) Input capacitance (CS0#) Input capacitance (CK0, CK0#) Input capacitance (DM0 - DM8), (DQS0 - DQS8) Input capacitance (DQ0 - DQ63), (CB0 - CB7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 COUT1 Min Max Unit pF pF pF pF pF pF
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W3HG64M72EER-AD7
ADVANCED
OPERATING TEMPERATURE CONDITION
Parameter Operating temperature Symbol TOPER Rating 0C to 85C Units C Notes V
Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. Forthe measurement conditions, please refer to JEDEC JESD51 .2 2. At 0 - 85C, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS Parameter Input High (Logic 1 ) Voltage Input Low (Logic 0) Voltage Symbol VIH(DC) VIL(DC) Min VREF + 125 -300 Max VREF + 300 VREF - 125 Unit mV mV
INPUT AC LOGIC LEVEL
All voltages referenced to VSS Parameter AC Input High (Logic 1 ) Voltage (DDR2-400/533) AC Input High (Logic 1) Voltage (DDR2-667) AC Input Low (Logic 0) Voltage Symbol VIH(AC) VIH(AC) VIL(AC) Min VREF + 250 VREF + 200 -- VREF - 250 Max -- Unit mV mV mV
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W3HG64M72EER-AD7
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only; TA = 0C, VCC = 1.9V Symbol Parameter ICCO* Operating one bank active-precharge; Operating one bank active-readprecharge; Precharge powerdown current; Precharge quite standby current; Precharge standby current; Active power-down current; Active standby current; Operating burst write current; Condition tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING IOUT = OmA; BL = 4; CL = CL(ICC); tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING; Data pattern is sames as ICC4W. All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING All banks idle; tCK = tCK(ICC); CKE is HIGH; CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING All banks idle; tCK = tCK(ICC); CKE is HIGH; CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are SWITCHING Fast PDN Exit All banks open; tCK = tCK(ICC), CKE is LOW; MRS(12) = 0 Other control and address bus inputs are Slow PDN Exit STABLE; Data bus inputs are FLOATING MRS(12) = 1 All banks open; tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING All banks open; Continuous burst writes; BL = 4; CL = CL(ICC); AL = 0; tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING All banks open; Continuous burst reads; TOUT = OmA; BL = 4; CL = CL(ICC); AL = 0; tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W. tCK = tCK(ICC); Refresh command at every tRC(ICC) interval; CKE is HIGH; CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING CK and CK# at OV; CKE < 0.2V; Other control and address bus inputs are FLOATING; Data Normal bus inputs are FLOATING All bank interleaving reads; IOUT = OmA; BL = 4; CL = CL(ICC); AL = tRCD(ICC) - 1*tCK(ICC); tCK = tCK(ICC); tRC = tRC(ICC); tRRD = tRRD MIN(ICC) = 1*tCK(ICC); CKE is HIGH; CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING 806
TBD
667 810
534 720
403 720
Unit mA
ICC1*
TBD
945
855
810
mA
ICC2P** ICC2Q** ICC2N**
TBD
45 450 495 315 90 585
45 360 405 270 90 495
45 315 360 225 90 405
mA mA mA mA mA mA
TBD
TBD
TBD
ICC3P**
TBD
ICC3N**
TBD
ICC4W*
TBD
1,395
1,170
990
mA
ICC4R*
Operating burst read current; Burst auto refresh current; Self refresh current;
TBD
1,575
1,305
1,035
mA
ICC5**
TBD
1,890
1,800
1,710
mA
ICC6**
TBD
45
45
45
mA
ICC7*
Operating bank interleave read curent;
TBD
2,520
2,340
2,070
mA
Notes: ICC specification is based on MICRON components. Other DRAM manufacturers specification may be different. * Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P ( CKE LOW) mode. ** Value calculated reflects all module ranks in this operating condition.
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AC TIMING PARAMETERS
W3HG64M72EER-AD7
ADVANCED
0C TCASE < +85C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V AC CHARACTERISTICS PARAMETER CL = 6 Clock cycle time Clock CL = 5 CL = 4 CL = 3 CK high-level width CK low-level width Half clock period SYMBOL tCK (6) tCK (5) tCK (4) tCK (3) tCH tCL tHP
TBD TBD
806 MIN
TBD TBD TBD TBD TBD TBD
667 MAX
TBD TBD TBD TBD TBD TBD
534 MAX MIN MAX MIN
403 MAX UNIT ps Notes 16, 24 16, 24 16, 24 16, 24 18 18 19
MIN
3,000 3,750 5,000 0.45 0.45 MIN (tCH, tCL) -450
8,000 8,000 8,000 0.55 0.55 3,750 5,000 0.45 0.45 MIN (tCH, tCL) +450 tAC (MAX) -500 +500 tAC MAX tAC (MIN) 350 350 100 225 0.35 340 400 tHPtQHS tQHtDQSQ 0.35 0.35 +400 -450 0.2 0.2 240 300 0.9 1.1 0.9 +450 tHPtQHS tQHtDQSQ 0.35 0.35 -500 0.2 0.2 350 1.1 +500 tAC (MAX) tAC (MIN) 400 400 150 275 0.35 450 8,000 8,000 0.55 0.55 5,000 5,000 0.45 0.45 MIN (tCH, tCL) -600 +600 tAC MAX tAC (MAX) 8,000 8,000 0.55 0.55
ps ps ps tCK tCK ps
DQ output access time from CK/CK# Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# DQ and DM input setup time relative to DQS DQ and DM input hold time relative to DQS Data DQ and DM input setup time relative to DQS DQ and DM input hold time relative to DQS DQ...DQS hold, DQS to first DQ to go nonvalid, per access relative to DQS Data hold skew factor DQ-DQS hold, DQS to first DQ to go nonvalid, per access Data valid output window (DVW) DQS input high pulse width DQS input low pulse width DQS output access time from CK/CK# Data Strobe DQS falling edge to CK rising- setup time DQS falling edge from CK rising - hold time DQS-DQ skew, DQS to last DQ valid, per group, per access DQS read preamble
tAC tHZ tLZ tDSa tDHa tDSb tQHb tDIPW tQHS tQH tDVW tDQSH tDQSL tDQSCK tDSS
TBD TBD
TBD TBD
ps ps ps ps ps tCK ps ps 8, 9 8, 10 7, 15, 21 7, 15, 21 7, 15, 21 7, 15, 21
TBD
TBD
tAC (MIN) 300 300 100 175 0.35
tAC (MAX)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD TBD TBD
TBD TBD TBD
tHPtQHS tQHtDQSQ 0.35 0.35 -400 0.2
15, 17 15, 17 tCK tCK ps tCK tCK ps tCK 15, 17 35
TBD TBD TBD TBD
TBD TBD TBD TBD
TBD
TBD
tDSH
TBD TBD
0.2
tDQSQ
TBD TBD
tRPRE
TBD
TBD
0.9
1.1
NOTE: * AC specification is based on MICRON components. Other DRAM manufactures specification may be different.
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W3HG64M72EER-AD7
ADVANCED
AC TIMING PARAMETERS (Continued)
0C TCASE < +85C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V AC CHARACTERISTICS PARAMETER DQS read preamble Data Strobe DQS write preamble setup time DQS write preamble DQS write postamble Write command to first DQS latching transition Address and control input pulse width for each input Address and control input setup time Address and control input hold time Address and control input setup time Address and control input hold time CAS# to CAS# command delay Active to Active (same bank) command Active bank a to Active b bank command Active to Read or Write delay Four Bank Activate period Active to precharge command Internal Read to precharge command delay Write recovery time Auto precharge wirte recovery and precharge time Interval Write to Read command delay Precharge command period Precharge All command period Load Mode command cycle time CKE low to CK,CK# uncertainty SYMBOL tRPST tWPRES tWPRE tWPST tDQSS tIPW tISa tIHa tISb tIHb tCCD tRC tRRD tRCD tFAW tRAS tRTP tWR tDAL tWTR tRP tRPA tMRD tDELAY MIN
TBD TBD TBD TBD TBD
806 MAX
TBD TBD TBD TBD TBD
665 MIN 0.4 0 0.35 0.4 WL0.25 0.6 400 400 200 275 2 55 7.5 15 37.5 40 7.5 15 tWR+tRP 10 15 tRP+tCK 2 tIS+tCK+tIH 70,000 0.6 MAX 0.6 MIN 0.4 0 0.25 0.4 WL0.25 0.6 500 500 250 375 2 55 7.5 15 37.5 40 7.5 15
534 MAX 0.6 MIN 0.4 0 0.25 0.6 0.4 WL0.25 0.6 600 600 350 475 2 55 7.5 15 37.5 70,000 40 7.5 15
403 MAX 0.6 UNIT tCK ps tCK 0.6 tCK tCK tCK ps ps ps ps tCK ns ns ns ns 70,000 ns ns ns ns ns ns ns tCK tIS+tCK+tIH ns 28 30 20, 33 23, 27 27 22 27 31 31 33 27 6, 21 6, 21 6, 21 6, 21 11 Notes 35 12, 13, 36
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Command and Address
TBD TBD TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD TBD TBD
tWR+tRP 7.5 15 tRP+tCK 2 tIS+tCK+tIH
tWR+tRP 10 15 tRP+tCK 2
TBD TBD TBD TBD
TBD TBD TBD TBD
TBD
TBD
NOTE: * AC specification is based on MICRON components. Other DRAM manufactures specification may be different.
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W3HG64M72EER-AD7
ADVANCED
AC TIMING PARAMETERS (Continued)
0C TCASE < +85C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V AC CHARACTERISTICS PARAMETER Refresh to Active or Refresh to Refresh command interval Self Refresh Average periodic refresh interval Exit self refresh to non-read command Exit self refresh to read command Exit self refresh timing reference ODT turn-on delay ODT turn-on ODT turn-off delay ODT turn-off ODT ODT turn-on (power-down mode) ODT turn-off (power-down mode) ODT to power-down entry latency ODT power-down exit latency Exit active power-down to READ command, MR[bit12=0] Power-Down Exit active power-down to READ command, MR[bit12=1] Exit precharge power-down to any non-READ command. CKE minimum high/low time SYMBOL tRFC tREFI tXSNR tXSRD tISXR tAOND tAON tAOFD tAOF MIN
TBD
806 MAX
TBD
665 MIN 105 200 tRFC
(MIN)+10
534 MAX 70,000 7.8 tRFC
(MIN)+10
403 MAX 70,000 7.8 tRFC
(MIN)+10
MIN 105
MIN 105
MAX 70,000 7.8
UNIT ns s ns tCK ps
Notes 14 14
TBD
TBD
TBD
TBD
TBD
TBD
200 tIS 2 tAC(MIN) 2.5 tAC(MIN)
tAC(MIN)
200 tIS 2 tAC(MAX) +700 2.5 tAC(MAX) +600
2x tCK + tAC (MAX) + 1,000 2x tCK + tAC (MAX) + 1,000
200 tIS 2 tAC(MAX) +1,000 2.5 tAC(MAX) +600
2x tCK + tAC (MAX) + 1,000 2x tCK + tAC (MAX) + 1,000
TBD TBD
TBD TBD
6, 29
2 tAC(MIN) 2.5 tAC(MIN)
tAC(MIN) +2,000 tAC(MIN) +2,000
2 tAC(MIN) 2.5 tAC(MIN)
tAC(MIN) +2,000 tAC(MIN) +2,000
2 tAC(MAX) +1,000 2.5 tAC(MAX) +600
2x tCK + tAC (MAX) + 1,000 2x tCK + tAC (MAX) + 1,000
tCK ps tCK ps 26 25
TBD
TBD
TBD
TBD
TBD
TBD
tAONPD
TBD
TBD
+2,000 tAC(MIN)
ps
tAOFPD tANPD tAXPD tXARD tXARDS tXP tCKE
TBD
TBD
+2,000
tCK tCK tCK tCK tCK tCK tCK 34
TBD TBD TBD
TBD TBD TBD
3 8 2 7-AL 2 3
3 8 2 6-AL 2 3
3 8 2 6-AL 2 3
TBD
TBD
TBD TBD
TBD TBD
NOTE: * AC specification is based on MICRON components. Other DRAM manufactures specification may be different.
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Notes
1. 2. All voltages referenced to VSS Tests for AC timing, ICC, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. Outputs measured with equivalent load: 13.
VTT = VCCQ/2 25 Output (VOUT) Reference Point
W3HG64M72EER-AD7
ADVANCED
High-Z and that any signal transition within the input switching region must follow valid input requirements. That is if DQS transitions high (above VIH DC (MIN) then it must not transition low (below VIH (DC) prior to tDQSH (MIN). 12. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turn around. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. The refresh period is 64ms. This equates to an average refresh rate of 7.8125s. However, a REFRESH command must be asserted at least once every 70.3s or tRFC (MAX). To ensure all rows of all banks are properly refreshed, 8192 REFRESH commands must be issued every 64ms. Each half-byte lane has a corresponding DQS. CK and CK# input slew rate must be 1V/ns ( 2V/ns if measured differentially). The data valid window is derived by achieving other specifications - tHP. (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived. MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. This value can be greater than the minimum specification limits for tCL and tCH. For example, tCL and tCH are = 50 percent of the period, less the half period jitter [tJIT(HP)] of the clock source, and less the half period jitter due to cross talk [tJIT(cross talk)] into the clock traces. tHP (MIN) is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs. READs and WRITEs with auto precharge are allowed to be issued before tRAS (MIN) is satisfied since tRAS lockout feature is supported in DDR2 SDRAM devices. VIL/VIH DDR2 overshoot/undershoot. REFER to the 512Mb DDR2 SDRAM data sheet for more detail. tDAL = (nWR) + (tRP/tCK): For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the application clock period; nWR refers to the tWR parameter stored in the MR[11,10,9]. Example: For 534 at tCK= 3.75 ns with tWR programmed to four clocks. tDAL = 4 + (15 ns/3.75ns) clock = 4 + (4) clocks = 8 clocks. The minimum READ to internal PRECHARGE time. This parameter is only applicable when tRTP/2*tCK) > 1. If tRTP/2*tCK) 1, then equation AL + BL/2 applies. Notwithstanding, tRAS (MIN) has to be satisfied as well. The DDR2 SDRAM device will automatically delay the internal PRECHARGE command until tRAS (MIN) has been satisfied. Operating frequency is only allowed to change during self refresh mode, precharge power-down mode, and system reset condition. ODT turn-on time tAON (MIN) is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn-on time tAON (MAX) is when the ODT resistance is fully on. Both are measured from tAOND.
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AC timing and ICC tests may use a VIL to VIH swing of up to 1.0V in the test environment parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1.0V/ns for signals in the range between VIL (AC) and VIH (AC). Slew rates less than 1.0V/ns require the timing parameters to be derated as specified. The AC and DC input level specifications are as defined in the SSTL_18 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). Command/Address minimum input slew rate is at 1.0V/ns. Command/Address input timing must be derated if the slew rate is not 1.0V/ns. This is easily accommodated using tISb and the Setup and Hold Time Derating Values table. tIS timing (tISb) is referenced from VIH (AC) for a rising signal and VIL (AC) for a falling signal. tIH timming (tIHb) is referenced from VIH (AC) for a rising signal and VIL (DC) for a falling signal. The timing table also lists the tISb and tIHb values for a 1.0V/ns slew rate; these are the "base" values. Data minimum input slew rate is at 1.0V/ns. Data input timing must be derated if the slew rate is not 1.0V/ns. This is easily accommodated if the timing is referenced from the logic trip points. tDS timing (tDSb) is referenced from VIH (AC) for a rising signal and VIL (AC) for a falling signal. tIH timing (tIHb) is referenced from VIH (DC) for a risng signal and VIL (DC) for a falling signal. The timing table lists the tDSb and tDHb values for a 1.0V/ns slew rate. If the DQS/DQS# differential strobe feature is not enabled, timing is no longer referenced to the crosspoint of DQS/DQS#. Data timing is now referenced to VREF, provided the DQS slew rate is not less than 1.0V/ns. If the DQS slew rate is less than 1.0V/ns, then data timing is now referenced to VIH (AC) for a rising DQS and VIL (DC) for a falling DQS. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (when the device output is no longer driving (tHZ) or begins driving (tLZ). This maximum value is derived from the referenced test load. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) tLZ will prevail over a tDQSCK (MIN) + tRPRE (MAX) condition. The intent of the Don't Care state after completion of the postamble is the DQS-driven signal should either be high, low or
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26. ODT turn-off time tAOF (MIN) is when the device starts to turn off ODT resistance. ODT turn off time tAOF (MAX) is when the bus is in high impedance. Both are measured from tAOFD. This parameter has a two clock minimum requirement at any tCK. tDELAY is calculated from tIS + tCK + tIH so that CKE registration LOW is guaranteed prior to CK, CK# being removed in a system RESET condition. tISXR is equal to tIS and is used for CKE setup time during self refresh exit. No more than 4 bank ACTIVE commands may be issued in a given tFAW (MIN) period. tRRRD (MIN) restriction still applies. The tFAW (MIN) parameter applies to all 8 bank DDR2 devices, regardless of the number of banks already open or closed. tRPA timing applies when the PRECHARGE(ALL) command is issued, regardless of the number of banks already open or closed. If a single-bank PRECHARGE command is issued, tRP timing applies. tRPA (MIN) applies to all 8-bank DDR2 devices. 35. 34. 32. 33.
W3HG64M72EER-AD7
ADVANCED
Value is minimum pulse width, not the number of clock registrations. Applicable to Read cycles only. Write cycles generally require additional time due to Write recovery time (tWR) during arto precharge. tCKE (MIN) of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2* tCK + tIH. This parameter is not referenced to a specific voltage level, but specified when the device output is no longer driving (tRPST) or beginning to drive (tRPRE). When DQS is used single-ended, the minimum limit is reduced by 100ps.
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W3HG64M72EER-AD7
ADVANCED
ORDERING INFORMATION FOR AD7
Part Number W3HG64M72EER806AD7XG** W3HG64M72EER665AD7xG** W3HG64M72EER534AD7xG W3HG64M72EER403AD7xG Speed/Data Rate 400MHz/800Mb/s 333MHz/667Mb/s 266MHz/533Mb/s 200MHz/400Mb/s CAS Latency 6 5 4 3 tRCD 6 5 4 3 tRP 6 5 4 3 Height* 18.29mm (0.72") 18.29mm (0.72") 18.29mm (0.72") 18.29mm (0.72")
**Contact factory for availability. NOTES: * RoHS product. ("G" = RoHS Compliant) * Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x" in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
PACKAGE DIMENSIONS FOR VLP AD7
FRONT VIEW
82.127 (3.233) 81.873 (3.223) 3.80 (0.150) MAX
1.00 (0.039) R X2 1.80 (0.071) D X2 6.0 (0.236) TYP 1.0 (0.039) TYP 2.0 (0.079) TYP 0.50 (0.02) R
PIN 1 PIN 122
18.45 (0.726) 18.15 (0.715) 10.0 (0.394) TYP 1.10 (0.043) 0.90 (0.035)
42.9 (1.689) TYP 78.0 (3.071) TYP
3.60 (0.142) FULL R
BACK VIEW
1.30 (0.051) Detail A
3.80 0.10 (0.150 0.004) 1.00 0.05 (0.039 0.002)
2.55 (0.100)
0.25 (0.010) MAX
3.3 (0.130) TYP 3.6 (0.142) TYP
PIN 244 PIN 123
0.60 (0.024)
0.450.03 (0.018 0.001) Detail B
33.6 (1.323) TYP 3.2 (0.126) TYP
Detail A
38.4 (1.512) TYP
Detail B
Tolerances: + /- 0.13 (0.005) unless otherwise specified.
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
December 2005 Rev. 1 12 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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PART NUMBERING GUIDE
W3HG64M72EER-AD7
ADVANCED
W 3 H G 64M 72 E E R xxx AD7 x G
WEDC MEMORY (SDRAM) DDR 2 GOLD DEPTH BUS WIDTH COMPONENT WIDTH (x8) 1.8V REGISTERED SPEED (Mb/s) VLP PACKAGE 244 PIN (0.72) COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = RoHS COMPLIANT
December 2005 Rev. 1
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White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Document Title
W3HG64M72EER-AD7
ADVANCED
512MB - 64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM
Revision History Rev #
Rev 0 Rev 1
History
Created 1.1 Updated ICC and AC specs
Release Date
September 2005 December 2005
Status
Advanced Advanced
December 2005 Rev. 1
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White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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