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MITSUBISHI ELECTRONICS AMERICA, INC.
PRELIMINARY
M30240
M30240 Group Specification
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Features...............................................................1-3 Applications......................................................... 1-3 Pin Configuration ................................................ 1-4 Block Diagram..................................................... 1-5 Performance outline............................................ 1-6 Pin Description.................................................... 1-8 Overview ........................................................... 1-10
Operation of Functional Blocks . . . . . . . . . 1-11
Central Processing Unit (CPU) ......................... 1-11 Processor Mode................................................ 1-14 Memory ............................................................. 1-15 SFR MAP .......................................................... 1-16 Reset................................................................. 1-22 Software Reset ................................................. 1-23 Clock-Generating Circuit................................... 1-23 Clock Control .................................................... 1-24 Stop Mode......................................................... 1-26 Wait Mode......................................................... 1-26 Status Transition Of the Internal Clock ......... 1-26 Power Control ................................................... 1-27 Protection.......................................................... 1-28 Interrupts........................................................... 1-29 NMI Interrupt ..................................................... 1-35 Key-Input Interrupt ............................................ 1-36 Address Match Interrupt.................................... 1-38 Watchdog Timer................................................ 1-39 Frequency Synthesizer Circuit .......................... 1-41 Universal Serial Bus.......................................... 1-44 DMAC ............................................................... 1-63 Timers ............................................................... 1-68 Timer A ............................................................. 1-69 Timer B ............................................................. 1-80 UART0 through UART2 .................................... 1-83 A-D Converter ................................................. 1-106 CRC Calculation Circuit .................................. 1-116 Programmable I/O Ports ................................. 1-117
Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-124
Usage Precautions.......................................... 1-124
Specifications . . . . . . . . . . . . . . . . . . . . . . 1-128
Electrical ......................................................... 1-128 Timing ............................................................. 1-130 Timing Diagrams- Peripheral/interrupt ............ 1-133
Applications . . . . . . . . . . . . . . . . . . . . . . . 1-134
Frequency Synthesizer Interface and DC-DC Converter..................................... 1-134 Attach/Detach Function................................... 1-138 Low Pass Filter Network ................................. 1-139 USB Transceiver............................................. 1-140 Programming Notes ........................................ 1-141
MITSUBISHI ELECTRONICS AMERICA, INC.
1-2
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Features
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.0 Description
The M30240 group is a 16-bit microcomputer based on the M16C family core technology. They are single-chip USB peripheral microcontrollers based on the Universal Serial Bus (USB) Version 1.1 specification. They are packaged in an 80-pin, molded plastic QFP. These single-chip microcontrollers operate using sophisticated instructions featuring a high level of instruction efficiency, making them capable of executing instructions at high speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling office communications, industrial equipment, and other high-speed processing applications.
1.1 Features
* * * * CPU .................................................... 16-bit (including a hardware multiplier) Number of instructions ........................ 91 Shortest instruction execution time ..... 83ns f(XIN)=12MHz USB Features:..................................... Five endpoint pairs (IN/OUT) FIFO Sizes (endpoints 0-4):32,128, 32, 32, 32 Conforms to USB V1.1 Specification USB Transceiver ................................. Conforms to USB V1.1 Specification-Internal Vref Frequency Synthesizer........................ PLL for 48MHz clock Memory capacity (mask device):......... ROM (40K, 48K) / RAM (3.0 K) Memory capacity (OTP device):.......... PROM (128K) / RAM (5K) Supply Voltage .................................... 4.1 to 5.25V f(XIN)=12MHz) Interrupts............................................. 21 internal and 4 external interrupt sources, 4 software interrupt sources; 7 levels (including key input interrupt X 16) Multifunction timer ............................... 5 X 16-bit, w/integrated 20mA (peak) PWM outputs General purpose timer ........................ 3 X 16-bit, internal interrupt only UART................................................... 3 X 7/8/9 bits; Configurable for synchronous or asynchronous mode DMAC.................................................. 2 channels (trigger: 18 sources) A-D Converter ..................................... 10 bits X 8 channels CRC calculation circuit ........................ 1 circuit (industry standard polynomial) Watchdog timer ................................... 1 line (15 bit) Programmable I/O............................... 63 lines High current and LED Drivers ............. 5 high current and 8 LED drivers Clock-generating circuit....................... 1 built-in circuit including feedback resistor Package: ............................................. 80P6N (0.8 mm pitch)
* * * * * * * * * * * * * * * * *
1.2 Applications
USB peripherals, such as telephones, audio systems, scanners, and digital cameras.
1-3
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Pin Configuration 1.3 Pin Configuration
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.1 shows the pin configuration (top view).
P20/LED0
P21/LED1
P22/LED2
P23/LED3
P24/LED4
P25/LED5
P26/LED6
P27/LED7
P12/KI10
P13/KI11
P14/KI12
P15/KI13
P16/KI14
P17/KI15
P11/KI9
P04/KI4
P05/KI5
P06/KI6
P07/KI7
P10/KI8
Vcc
P30
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P03/KI3 65 P02/KI2 66 P01/KI1 67 P00/KI0 68 40 39 38 37 36 35 34 P32 P33 P34 P35 P36 P37/CLKout P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TxD0 P64/CTS1/RTS1/CLKS1 P65/CLK1 P66/RxD1 P67/TxD1 P70/TxD2/TA0OUT P71/RxD2/TA0IN
P107/AN7 69 P106/AN6 70 P105/AN5 71
P104/AN4 72 P103/AN3 73 P102/AN2 74 P101/AN1 75 P100/AN0 76 AVss 77 LPF 78 Vref 79 AVcc 80 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
M30240Mx/EC
P31 33 32 31 30 29 28 27 26 25
1
2
3 P85/NMI
4 P84/INT1
5 P83/ATTACH
6
7 BYTE
8 CNVss
9 D+
Vss
P73/CTS2/RTS2/TA1IN
Figure 1.1:
Pin Configuration (top view)
1-4
P72/CLK2/TA1OUT
P80/TA4OUT
P76/TA3OUT
P74/TA2OUT
P81/TA4IN
P77/TA3IN
P87/ADTRG
P75/TA2IN
EXTCAP
P82/INT0
RESET
P86/SOF
Xout
Xin
Vcc
Vss
D-
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Block Diagram 1.4 Block Diagram
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.2 is a block diagram of the M30240 group.
8
8
8
8
8
8
7
8
I/O ports
Port P0
Port P1
Port P2
Port P3
Port P6
Port P7 Port P8 0~84 Port P85
86, 8 7
Port P10
Internal peripheral functions
Timer
Memory
ROM RAM
Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) Timer TA3 (16 bits) Timer TA4 (16 bits) Timer TB0 (16 bits) Timer TB1 (16 bits) Timer TB2 (16 bits) Watchdog timer
(1 line)
System clock generator XIN-XOUT
A-D converter
10 bits X 8 channels
M16C series16-bit CPU core
Registers Program counter PC Vector table INTB Stack pointer ISP USP R0H R0L R0H R0L R1L R1H R2 R3 A0 A1 FB SB
USB function Frequency Synthesizer
UART/clock synchronous SI/O (8 bits X 3 channels) (Note 1) CRC arithmetic circuit (CCITT) (Polynomial : X 16+X12+X 5+1)
DMAC
(2 channels)
Multiplier
FLG
Note 1: One of serial I/O can be used for SIM interface.
Figure 1.2:
Block diagram of M30240 group
1-5
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Performance outline 1.5 Performance outline
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.1 is a performance outline of the M30240 group. Table 1.1: Performance outline of M30240 group Item
Number of basic instructions Shortest instruction execution time ROM Memory capacity RAM I/O port Input port Multifunction Timer General purpose Timer Serial I/O A-D converter DMAC CRC calculation circuit Watchdog timer Interrupt Clock-generating circuit Supply voltage (typical) Power consumption (typical) I/O withstand voltage I/O characteristics Average output current P0 to P3, P6,P7, P8 (except P85), P10 P85 TA0, TA1, TA2, TA3, TA4 TB0, TB1, TB2 UART0, UART1, UART2 8 bits x 7, 7 bits x 1 1 bit x 1 16 bits x 5 16 bits x 3 (UART or clock synchronous) x 3 10 bits x 8 channels 2 channels (trigger:18 sources) CRC-CCITT 15 bits x 1 (with prescaler) 21 internal and 4 external sources, 4 software sources, 7 levels Built-in clock generation circuit (built-in feedback resistor, and external ceramic or quartz oscillator) 4.1 to 5.25V, (f(XIN)=12MHz, without software wait) 250 mwatt, Vcc=5.0V, 12MHz 5V 5 mA available on ports P0, P1, P3,P6, P71, P73, P75, P77, P81~P84, P86, P87, P10 10 mA available on ports P2, P70, P72, P74, P76, P80 0 to 70oC CMOS high performance silicon gate 80-pin plastic molded QFP (See Figure 3: ROM capacity field) 91 instructions 83ns (f(XIN) =12MHz)
Performance
Operating temperature Device configuration Package
1-6
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Performance outline
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi plans to release the following products in the M30240 group: (1) Support for mask ROM version and one-time PROM version (2) ROM capacity (3) Package
* 80P6N: Plastic molded QFP (mask ROM version and one-time PROM version)
Figure 1.3 shows the type number, memory size and package for the M30240 group.
Type No.
M 3 0 24 0 M 5 - X X X F P
Package type: FP : Package 80P6N
ROM No. Omitted for blank one-time PROM version,and EPROM version ROM capacity: 1: 8K bytes 2: 16K bytes 3: 24K bytes 4: 32K bytes 5: 40K bytes 6: 48K bytes 7: 8: 9: A: C: 56K bytes 64K bytes 80K bytes 96K bytes 128K bytes
Memory type: M : Mask ROM version E : EPROM or one-time PROM version S : External ROM version F : Flash memory version Part type: Specifies part variations with M30240 group M30240 Group M16C Family
Figure 1.3:
Type number, memory size, and package
Table 1.2 shows the Package Number, type, ROM and RAM Capacity for M30240 Group. Table 1.2: Type M30240M5 M30240M6 M30240ECFP M30240 Group
ROM Capacity 40K bytes 48K bytes 128K bytes RAM Capacity 3K bytes 3K bytes 5K bytes Package Type 80P6N 80P6N 80P6N Remarks Mask ROM Version Mask ROM Version One-time PROM version
1-7
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Pin Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.6 Pin Description
Table 1.3: Pin #
1 2 3 4,5
Figure Pin Description I/O
I/O I/O I I/O
Name
P87 P86 P85/(NMI) P84 ~ P83
Description
CMOS I/O port. This pin also functions as an external trigger for A-D conversion. CMOS I/O port. This pin also functions as the start of frame (SOF) pulse for the USB module. CMOS input port. This pin also functions as a non-maskable external interrupt. CMOS I/O port. These pins also functions as external interrupt 1 and are used to enable the stealth detach function for the USB transceiver. An external capacitor (Ext. Cap) pin. When the USB transceiver voltage converter is used, a 2.2 F and a 0.1 F capacitor should connect between this pin and Vss to ensure proper operation of the USB line driver. This option is enabled by setting bit 4 of the USB control register (000C16) to a "1". Connect this pin to Vss Connect this pin to Vss USB D+ voltage line interface, a series resistor of 33 is connected to this pin. USB D- voltage line interface, a series resistor of 33 is connected to this pin. A "L" on this input resets the microcomputer. See Xin Ground: Vss = 0V Input and output signals to and from the internal clock generation circuit. Connect a ceramic resonator or quartz crystal between Xin and Xout pins to set the oscillation frequency. If an external clock is used, connect the clock source to the Xin pin and leave the Xout pin open. Power: Vcc = 4.1~ 5.25V CMOS I/O port. This pin also functions as external interrupt 0. CMOS I/O port. Pins in this port also function as TimerA4 input and output as selected by software. CMOS I/O port. Pins in this port also function as timer pins. P77 and P76 can function as TimerA3 input and output as selected by software. P75 and P74 can function as TimerA2 input and output as selected by software. CMOS I/O port. Pins in this port also function as UART2 CTS, RTS, CLK, RXD, and TXD as selected by software. P73 and P72 can function as TimerA1 input and output as selected by software. P71 and P70 can function as TimerA0 input and output as selected by software. CMOS I/O port. Pins in this port also function as UART1 CTS, RTS, CLK, Serial Clock, RXD, and TXD as selected by software. TXD(OE~) and RTS(SUSPEND) in addition to D+ and D- can be used to run the device in USB bypass mode. CMOS I/O port. Pins in this port also function as UART0 CTS, RTS, CLK, RXD, and TXD as selected by software. CMOS I/O port. CMOS I/O port. These pins are capable of driving up to 20mA (peak) for LEDs.
6
EXTCAP
_
7 8 9 10 11 12 13
BYTE CNVss USB D+ USB D
-
I I I/O I/O I O I
RESET Xout Vss
14
Xin
I
15 16 17-18 19-22
Vcc P82 P81 ~ P80
I I/O I/O
P77 ~ P74
I/O
23-26
P73 ~ P70
I/O
27-30
P67 ~ P64 P63 ~ P60 P37 ~ P30 P27/LED7 ~ P20/LED0
I/O
31-34 35-42 43-50
I/O I/O I/O
1-8
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Pin Description
Table 1.3: Pin #
51 52 53 54-60 61-68 69-76 77 78 79 80
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure Pin Description I/O
I I/O I I/O I/O I/O I O I I Power: Vcc = 4.1~ 5.25V CMOS I/O port. This port can also function as the key-on wakeup interrupt KI15. Ground: Vss = 0V CMOS I/O port. This port can also function as the key-on wakeup interrupts (KI8 ~ KI14). CMOS I/O port. This port can also function as the key-on wakeup interrupts (KI0 ~ KI7). CMOS I/O port. These pins also function as Analog inputs 7-0 for A-D conversion This pin is a power supply input for the AD converter. (Connect to Vss) Loop filter for the frequency synthesizer. This pin is the reference voltage input for the A-D converter. This pin is a power supply input for the AD converter. (Connect to Vcc)
Name
Vcc P17/KI15 Vss P16/KI14 ~ P10/KI8 P07/KI7 ~ P00/KI0 P107 ~ P100 AVss LPF VREF AVcc
Description
1-9
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Overview 1.7 Overview
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The M30240 group is a single chip PC peripheral microcontroller based on the Universal Serial Bus (USB) Version 1.1 specification. This device provides interface between a USBequipped host computer and PC peripherals such as telephones, audio systems, and digital cameras. The M30240 block diagram is shown in Figure 1.4. The USB function control unit of the M30240 group can support all four data transfer types listed in the USB specification: Isochronous, Interrupt, Bulk, and Control. Each transfer type is used for controlling a different set of PC peripherals. Isochronous transfers provide guaranteed bus access, a constant data rate, and error tolerance for devices such as computer-telephone integration (CTI) and audio systems. Interrupt transfers are designed to support human input devices (HID) that communicate small amounts of data infrequently. Bulk transfers are necessary for devices such as digital cameras and scanners that communicate large amounts of data to the PC as bus bandwidth becomes free. Finally, control transfers are supported and are useful for bursty, host-initiated type communication where bus management is the primary concern.
1 - 12MHz
frequency 48 MHz synthesizer
UART x 3
RAM
M16C CPU Watchdog Timer A-D Converter DMAC x 2 CRC Circuit
Transceiver
LED Drivers (X 8)
Timers x 8
ROM
USB Function Control Unit
D+
D-
FIFOs (Normal MCU or DMA Transfer) I/O Ports (P0~P3, P6 ~ P8, P10)
Figure 1.4:
M30240 block diagram
1-10
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Central Processing Unit (CPU)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.0 Operation of Functional Blocks
The M30240 group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data, and the central processing unit (CPU) to execute arithmetic/logic operations. Also included are peripheral units such as USB, timers, serial I/O, DMAC, CRC calculation circuit, A-D converter, and I/O ports. The following explains each unit.
2.1 Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 1.5. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks.
b15
b8 b7
b0
R0(Note)
H
L
b15
b8 b7
b0
b19
b0
R1(Note)
H
L Data registers
PC
Program counter
b15
b0
b19
b0
R2(Note)
INTB
H
L
Interrupt table register
b0
b15
b0
b15
R3(Note)
USP
User stack pointer
b15
b0
b15
b0
A0(Note) Address registers
ISP
Interrupt stack pointer
b15
b0
b15
b0
A1(Note)
SB
Static base register
b15
b0
b15
b0
FB(Note)
Frame base registers
FLG
Flag register
IPL
U
I OBS Z DC
Note: These registers consist of two register banks.
Figure 1.5:
Central processing unit register
2.1.1 Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3) Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations.
1-11
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Central Processing Unit (CPU)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1, can be used as 32-bit data registers (R2R0/R3R1). 2.1.2 Address registers (A0 and A1) Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). 2.1.3 Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing. 2.1.4 Program counter (PC) Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed. 2.1.5 Interrupt table register (INTB) Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table. INTB can be used as separate registers of four high-order bits and 16 low-order bits. 2.1.6 Stack pointer (USP/ISP) Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG). 2.1.7 Static base register (SB) Static base register (SB) is configured with 16 bits, and is used for SB relative addressing. 2.1.8 Flag register (FLG) Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.6 shows the flag register (FLG). The following explains the function of each flag: 2.1.8.1 Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.1.8.2 Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt. When this flag is "1", a single-step interrupt is generated after instruction execution. This flag is cleared to "0" when the interrupt is acknowledged.
2.1.8.3 Bit 2: Zero flag (Z flag)
This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, cleared to "0".
2.1.8.4 Bit 3: Sign flag (S flag)
This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, cleared to "0".
2.1.8.5 Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is "0"; register bank 1 is selected when this flag is "1".
2.1.8.6 Bit 5: Overflow flag (O flag)
This flag is set to "1" when an arithmetic operation resulted in overflow; otherwise, cleared to "0".
1-12
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Central Processing Unit (CPU)
2.1.8.7 Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
An interrupt is disabled when this flag is "0", and is enabled when this flag is "1". This flag is cleared to "0" when the interrupt is acknowledged.
2.1.8.8 Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is "0"; user stack pointer (USP) is selected when this flag is "1". This flag is cleared to "0" when a hardware interrupt is acknowledged or an INT instruction of software interrupts 0 to 31 is executed.
2.1.8.9 Bits 8 to 11: Reserved area 2.1.8.10 Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled.
2.1.8.11 Bit 15: Reserved area The C, Z, S, and O flags are changed when instructions are executed. See the M16C software manual for details.
b15
b0
IPL
U
I
OBSZDC
Flag register (FLG)
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area
Figure 1.6:
Flag register (FLG)
1-13
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Processor Mode 2.2 Processor Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.7 shows the processor mode registers 0 and 1.
Processor mode register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
00
0
Symbol PM0
Address 000416
When reset 0016 (Note)
Bit symbol
Reserved bit
PM03
Bit name
Function
Must always be set to "0"
RW
Software reset bit
The device is reset when this bit is set to "1". The value of this bit is "0" when read.
Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate. Note : Set bit 1 of the protect register (address 000A 16) to "1" when writing new values to this register.
Processor mode register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Symbol PM1
Address 000516
When reset 00XXXXX02
Bit symbol
Reserved bit
Bit name
Function
Must always be set to "0"
RW
Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate.
PM17
Wait bit
0 : No wait state 1 : Wait state inserted
Note : Set bit 1 of the protect register (address 000A 16) to "1" when writing new values to this register.
Figure 1.7:
Processor mode registers 0 and 1
1-14
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Memory 2.3 Memory
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
0000016 0040016
SFR RAM
XXXXX16
unused
yyyyy 16
ROM
FFE0016
Special page vector table
FFFDC16 Undefined instruction
Overflow
Type M30240M5 M30240M6 M30240ECFP
Address xxxxx 16 01000 16 01000 16 01800 16
Address yyyyy 16 F6000 16 F4000 16 E0000 16
FFFFF16
BRK instruction Address match Single step Watchdog timer DBC NMI Reset
Figure 1.8:
Memory Map
Figure 1.8 is a memory map of the M30240 group. The address space extends the 1M bytes from address 0000016 to FFFFF16. Addresses above yyyyy16 are ROM. For example, in the M30240ECFP, there is 128K bytes of internal ROM from E000016 to FFFFF16. The special page vector table is mapped from FFE0016 to FFFDB16. If the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as two-byte instructions, reducing the number of program steps. The vector table for fixed interrupts such as the reset and NMI are mapped from FFFDC16 to FFFFF16. The starting addresses of the interrupt routines are stored here. The address of the vector table for software interrupts can be set as desired using the internal register (INTB). See Section 2.12 on interrupts for further details. Addresses below xxxxx16 are RAM. For example, in M30240ECFP, 5K bytes of internal RAM are mapped to the space from 0040016 to 017FF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated.The SFR area is mapped to 0000016 to 003FF16. This area accommodates control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers. Section 2.4 describes the SFR area for peripheral unit control registers. Any part of the SFR area that is unoccupied is reserved and cannot be used for other purposes.
1-15
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
SFR MAP 2.4 SFR MAP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The table below shows the peripheral control registers, their addresses, names, acronyms, and values after reset.
Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16
Register name
Acronym
Value after reset
Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 Address match interrupt enable register Protect register USB control register Watchdog timer start register Watchdog timer control register Address match interrupt register 0
PM0 PM1 CM0 CM1 AIER PRCR USBC WDTS WDC RMAD0
0016 00 4816 2016 00 000 0016 0
000????? 0016 0016 0000 0016 0016 0000
Address match interrupt register 1
RMAD1
Reserved USB attach / detach register
USBAD SAR0
0016
DMA0 source pointer
DMA0 destination pointer
DAR0
DMA0 transfer counter
TCR0
DMA0 control register
DM0CON
00000?00
DMA1 source pointer
SAR1
DMA1 destination pointer
DAR1
DMA1 transfer counter
TCR1
DMA1 control register
DM1CON
00000?00
1-16
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
SFR MAP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 030A16 030B16 030C16 030D16 030E16 030F16 031016 031116 031216 031316 031416 031516 031616 031716 031816 031916 031A16 031B16 031C16 031D16 031E16 031F16
Register name
Acronym
Value after reset
Suspend interrupt control register Resume interrupt control register USB SOF interrupt control register
SUSPIC RSMIC SOFIC
?000 ?000 00?000
Bus collision detection interrupt control register
DMA0 interrupt control register DMA1 interrupt control register Key input interrupt control register A-D conversion interrupt control register UART2 transmit interrupt control register UART2 receive interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register TIMER A0 interrupt control register TIMER A1 interrupt control register TIMER A2 interrupt control register TIMER A3 interrupt control register TIMER A4 interrupt control register TIMER B0 interrupt control register TIMER B1 interrupt control register Reset interrupt control register INT0 interrupt control register INT1 interrupt control register USB function interrupt control register --USB address register USB power management register USB interrupt status register 1 USB interrupt status register 2 USB interrupt enable register 1 USB interrupt enable register 2 USB frame number register low USB frame number register high USB ISO control register USB DMA0 source register USB DMA1 source register USB endpoint enable
BCNIC DM0IC DM1IC KUPIC ADIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC RSTIC INT0IC INT1IC USBFIC USBA USBPM USBIS1 USBIS2 USBIE1 USBIE2 USBSOFL USBSOFH USBISOC USBSAR0 USBSAR1 USBEPEN
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 00? 00? ? 0016 0016 0016 0016 FF16 3316 0016 0016 0016 0016 0016 FF16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
USB reserved USB EP 0 control/status register USB reserved USB EP 0 max packet size register USB reserved USB EP 0 OUT write count USB reserved USB reserved USB reserved USB EP 1 IN control/status register USB EP 1 OUT control/status register USB EP 1 IN max packet size register USB EP 1 OUT max packet size register USB EP 1 OUT write count USB reserved USB reserved
EP0CS EP0MP EP0WC
0016 0816 0016
EP1ICS EP1OCS EP1IMP EP1OMP EP1WC
0016 0016 0016 0016 0016
1-17
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
SFR MAP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address 032016 032116 032216 032316 032416 032516 032616 032716 032816 032916 032A16 032B16 032C16 032D16 032E16 032F16 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16
Register name
USB reserved USB EP 2 IN control/status register USB EP 2 OUT control/status register USB EP 2 IN max packet size register USB EP 2 OUT max packet size register USB EP 2 OUT write count USB reserved USB reserved USB reserved USB EP 3 IN control/status register USB EP 3 OUT control/status register USB EP 3 IN max packet size register USB EP 3 OUT max packet size register USB EP 3 OUT write count USB reserved USB reserved USB reserved USB EP 4 IN control/status register USB EP 4 OUT control/status register USB EP 4 IN max packet size register USB EP 4 OUT max packet size register USB EP 4 OUT write count USB reserved USB reserved USB EP 0 FIFO USB EP 1 FIFO USB EP 2 FIFO USB EP 3 FIFO USB EP 4 FIFO reserved reserved reserved
Acronym EP2ICS EP2OCS EP2IMP EP2OMP EP2WC
Value after reset 0016 0016 0016 0016 0016
EP3ICS EP3OCS EP3IMP EP3OMP EP3WC
0016 0016 0016 0016 0016 0016
EP4ICS EP4OCS EP4IMP EP4OMP EP4WC
0016 0016 0016 0016 0016
EP0 EP1 EP2 EP3 EP4
1-18
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
SFR MAP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16
Register name
Acronym
Value after reset
Reserved UART2 transmit / receive mode register UART2 bit rate generator UART2 transmit buffer register UART2 transmit /receive control register 0 UART2 transmit / receive control register 1 UART2 receive buffer register Count start flag Reserved One-shot start flag Trigger select register Up-down flag
U2MR U2BRG U2TB U2C0 U2C1 U2RB TABSR ONSF TRGSR UDF 00
0016
0816 0216
0016 00000 0016 0016
Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register
TA0 TA1 TA2 TA3 TA4 TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR 0016 0016 0016 0016 0016 00? 0000 00? 0000 00? 0000
UART0 transmit / receive mode register UART0 bit rate generator UART0 transmit buffer register UART0 transmit / receive control register 0 UART0 transmit / receive control register 1 UART0 receive buffer register UART1 transmit / receive mode register UART1 bit rate generator UART1 transmit buffer register UART1 transmit / receive control register 0 UART1 transmit / receive control register 1 UART1 receive buffer register
U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB
0016
0816 0216
0016
0816 0216
1-19
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
SFR MAP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16
Register name
UART transmit / receive control register 2
Acronym UCON
Value after reset 0000000
DMA0 cause select register DMA1 cause select register
DM0SL DM1SL
0016 0016
CRC data register CRC input register
CRCD CRCIN
A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
A-D control register 2 A-D control register 0 A-D control register 1
ADCON2 ADCON0 ADCON1
0 00000??? 0016
Frequency synthesizer clock control Frequency synthesizer control Frequency synthesizer multiplier control Frequency synthesizer prescaler control Frequency synthesizer divider Port P0 Port P1 Port P0 direction register Port P1 direction register Port P2 Port P3 Port P2 direction register Port P3 direction register
FSCCR FSC FSM FSP FSD P0 P1 PD0 PD1 P2 P3 PD2 PD3
0016 6016 FF16 FF16 FF16
0016 0016
0016 0016
Port P6 Port P7 Port P6 direction register Port P7 direction register
P6 P7 PD6 PD7
0016 0016
1-20
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
SFR MAP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16
Register name
Port P8 Port P8 direction register Port P10 Port P10 direction register
Acronym P8 PD8 P10 PD10
Value after reset
00
00000
0016
P2 drive capacity Timer A Output Drive Capacity Pull-up control register 0 Pull-up control register 1
P2DR TADR PUR0 PUR1
0016 0016 0016 0016
1-21
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Reset 2.5 Reset
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
There are two types of resets: hardware and software. In both cases, operation is the same after the reset. (See "Software Reset" for further details regarding software resets.) This section explains on hardware resets. When the supply voltage is within the range where operation is guaranteed, a reset is effected by holding the reset pin level "L" (0.2VCC max.) for at least 20 f(XIN) cycles. When the reset pin level is then returned to the "H" level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. Figure 1.9 shows an example of a reset circuit. Figure 1.10 shows the reset sequence. .
5V 4.0V VCC 0V 5V RESET 0.8V 0V
RESET
VCC
Example when V CC = 5V.
Figure 1.9:
Reset circuit
XIN At least 20 cycles are needed
RESET Internal clock F
Internal clock F 24 cycles
FFFFC16 Address FFFFE16
Content of reset vector
Figure 1.10: Reset sequence
1-22
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Software Reset
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When the RESET pin level = "L", all ports change to input mode (floating.) Table 1.4 shows the status of the other pins while the RESET pin level is "L". Table 1.4: Main clock-generating circuits Functions
Use of clock Usable oscillator Pins to connect oscillator Oscillation stop/restart function Oscillator status immediately after reset
Main clock-generating circuit
* CPU's operating clock source * Internal peripheral units' operating clock source Ceramic or crystal oscillator
Xin, Xout
Available Oscillating
2.6 Software Reset
Writing a "1" to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the microcomputer. A software reset has almost the same effect as a hardware reset with the following exceptions: * The contents of internal RAM are preserved * All USB, DC-DC converter, and PLL SFR values are preserved. (See Section 2.4)
2.7 Clock-Generating Circuit
The clock-generating circuit contains one oscillator circuit that supplies the operating clock sources to the CPU and internal peripheral units.Example of oscillator circuit Figure 1.11 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Circuit constants in Figure 1.11 vary with each oscillator used. Use circuit constant values recommended by the oscillator manufacturer.
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
XIN
XOUT (Note) Rd
XIN
XOUT Open
Externally derived clock CIN COUT Vcc Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable.
Figure 1.11: Examples of clock source
1-23
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Clock Control 2.8 Clock Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.12 shows the block diagram of the clock-generating circuit.
XIN XOUT fusb (48MHz) Frequency Synthesizer Circuit fsyn fAD f1SIO2 f1 FSCCR0=1 FSCCR0=0 CM10 "1" Write signal RESET Software reset NMI Interrupt request level judgment output WAIT instruction CM02 SQ b R a c d Internal clock Divider f8 f32 f8SIO2 f32SIO2
Main clock
SQ R
b a
1/2 1/2 1/2 1/2 1/2
c
CM06=0 CM17,CM16=11 CM06=1 CM06=0 CM17,CM16=10
d
CM06=0 CM17,CM16=01 CM06=0 CM17,CM16=00 CM0i : Bit i at address 000616 CM1i : Bit i at address 000716 FSCCRi: Bit i at address 03DB16
Details of divider
Figure 1.12: Clock-generating circuit The following paragraphs describe the clocks generated by the clock-generating circuit. 2.8.1 Main clock The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to the internal clock . The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the clock reduces the power dissipation. After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the f(Xout) pin can be reduced using the f(Xin)-f(Xout) drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the f(Xout) pin reduces the power dissipation. This bit defaults to "1" when shifting to stop mode and after a reset. 2.8.2 Internal clock The internal clock is the clock that drives the CPU, and is either the main clock or is derived by dividing the main clock by 2, 4, 8, or 16. The internal clock is derived by dividing the main clock by 8 after a reset. When shifting to stop mode, the main clock division select bit (bit 6 at 000616) is set to "1".
1-24
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Clock Control
2.8.3 Peripheral function clock 2.8.3.1 * f1, f8, f32
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 000616) to "1" and then executing a WAIT instruction. 2.8.3.2 * fAD This clock has the same frequency as the main clock and is used for A-D conversion. 2.8.4 Clock Output In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8 or f32 to be output from the P37/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address 000616) is set to "1", the output of f8 and f32 stops when a WAIT instruction is executed. Figure 1.13 shows the system clock control registers 0 and 1.
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CM0 Bit symbol
CM00 CM01 CM02
Address 000616 Bit name
Clock output function select bit
When reset 4816 Function
b1 b0
RW
WAIT peripheral function clock stop bit
0 0 : I/O port P3 7 0 1 : Invalid 1 0 : f8 output 1 1 : f32 output 0 : Do not stop f 1, f8, f32 in wait mode 1 : Stop f1, f8, f32 in wait mode
Reserved bit Reserved bit Reserved bit
CM06 Main clock division select bit 0 (Note 2)
Always set to "1" Always set to "0" Always set to "0"
0 : CM16 and CM17 valid 1 : Division by 8 mode
Reserved bit
Always set to "0"
Note 1: Set bit 0 of the protect register (address 000A 16) to "1" before writing to this register. Note 2: Changes to "1" when shifting to stop mode.
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
Symbol CM1 Bit symbol
CM10
Address 000716 Bit name
All clock stop control bit
When reset 2016 Function
0 : Clock on 1 : All clocks off (stop mode) Always set to "0" Always set to "0" Always set to "0" Always set to "0" 0 : LOW 1 : HIGH 0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode
b7 b6
RW
Reserved bit Reserved bit Reserved bit Reserved bit CM15 CM16 CM17 XIN-XOUT drive capacity select bit (Note 2) Main clock division select bit 1 (Note 3)
Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register. Note 2: Changes to "1" when shifting to stop mode. Note 3: Can be selected when bit 6 of system clock control register 0 (address 000616) is "0". If "1", division mode if fixed at 8.
Figure 1.13: System clock control registers 0 and 1 1-25
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Stop Mode 2.9 Stop Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Writing "1" to the all-clock stop control bit (bit 0 at address 0007 16) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains above 2V. Because the oscillation of internal clock , f1 to f32, and fAD stops in stop mode, peripheral functions such as the A-D converter and watchdog timer do not function. However, timer A operates, provided that the event counter mode is set to an external pulse, and UARTi (i = 0 to 2) functions provided an external clock is selected. Table 1.5 shows the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or interrupt. If an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. The I flag must also be set prior to stopping for an interrupt to cancel it. After coming out of stop mode, it is recommended that five "NOP" instructions be executed to clear the instruction queue. When shifting to stop mode, the main clock division select bit 0 (bit 6 at 000616) is set to "1". Table 1.5: Pin
Port CLKOUT
Port status during stop mode Single-chip mode
Retains status before stop mode Retains status before stop mode
2.10 Wait Mode
When a WAIT instruction is executed, the internal clock stops and the microcomputer enters the wait mode. In this mode, oscillation continues but the internal clock and watchdog timer stop. Writing "1" to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. Table 1.6 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the microcomputer restarts using as internal clock the clock that had been selected when the WAIT instruction was executed Table 1.6: Pin
Port CLKout
Port status during wait mode Single-chip mode
Retains status before stop mode Does not stop when the WAIT peripheral function clock stop bit is "0" When the WAIT peripheral function clock stop bit is "1", the status immediately prior to entering wait mode is maintained.
2.11 Status Transition Of the Internal Clock
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for internal clock . Table 1.7 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. After a reset, operation defaults to division by 8 mode. When shifting to stop mode, the main clock division select bit 0 (bit 6 at address 000616) is set to "1". The following shows the operational modes of internal clock 2.11.1 Division by 2 mode The main clock is divided by 2 to obtain the internal clock . 1-26
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Power Control
2.11.2 Division by 4 mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The main clock is divided by 4 to obtain the internal clock . 2.11.3 Division by 8 mode The main clock is divided by 8 to obtain the internal clock . Note that oscillation of the main clock must have stabilized before transferring from this mode to another mode. 2.11.4 Division by 16 mode The main clock is divided by 16 to obtain the internal clock . 2.11.5 No-division mode The main clock is used as internal clock. Table 1.7: CM17
0 1 Invalid 1 0
Operating modes dictated by settings of system clock control registers 0 and 1 CM16
1 0 Invalid 1 0
CM06
0 0 1 0 0
Operating mode of internal clock
Division by 2 mode Division by 4 mode Division by 8 mode Division by 16 mode No-division mode
2.12 Power Control
The following is a description of the three available power control modes: 2.12.0.1 Normal Operation Mode
* High-speed mode Divide-by-1 frequency of the main clock become the internal clock . The CPU operates with the internal clock selected. Each peripheral function operates according to its assigned clock. * Medium-speed mode Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the internal clock . The CPU operates according to the internal clock selected. Each peripheral function operates according to its assigned clock.
2.12.0.2 Wait mode
The CPU operation is stopped. The oscillators do not stop.
2.12.0.3 Stop Mode
All oscillators stop. The CPU and all built-in peripheral functions stop. Of the three modes listed, this mode is the most effective in decreasing power consumption.
1-27
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Protection
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.13 Protection
The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 1.14 shows the protect register. The values in the processor mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0 (address 000616), system clock control register 1 (address 000716) and frequency synthesizer registers can only be changed when the respective bit in the protect register is set to "1". The system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return to "0" after a value has been written to an address. The program must therefore be written to return these bits to "0".
Protect register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PRCR Bit symbol
PRC0
Address 000A16 Bit name
When reset XXXXX0002 Function
0 : Write-inhibited 1 : Write-enabled
RW
Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) and frequency
synthesizer registers (addresses
03DB16 to 03DF16) PRC1 Enables writing to processor mode 0 : Write-inhibited registers 0 and 1 (addresses 0004 16 1 : Write-enabled and 000516) Must always be set to "0"
Reserved bit
Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate.
Figure 1.14: Protect register
1-28
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Interrupts 2.14 Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.8 and Table 1.9 show the interrupt sources and vector table addresses. When an interrupt is received, the program is executed from the address shown by the respective interrupt vector. The vector table addresses for the interrupts in Table 7 are fixed (interrupt vector addresses). These interrupts are not affected by the interrupt enable flag (I flag) (non-maskable interrupts). The vector table addresses for the interrupts in Table 8 are variable, being determined as relative to the fixed address in the interrupt table register (INTB). These interrupts can be enabled or disabled using the interrupt enable flag (I flag) (maskable interrupts). Sixty four vectors can be set in the interrupt table register (INTB). Any of software interrupts 0 to 63 can be assigned to each vector. By using the INT instruction to specify a software interrupt number, the program can be executed starting at the address indicated by the respective vector. The BRK instruction interrupt has interrupt vectors in both the fixed vector address and variable vector address. When the contents of FFFE416 through FFFE716 are all "FF16), the program is executed from the address shown in the BRK instruction interrupt vector in the variable vector address. Specify the starting address of the interrupt program in the interrupt vector. Figure 1.15 shows the format for specifying the address.
Table 1.8:
Interrupt vectors (fixed interrupt vector addresses) Vector table addresses
Address(L) to Address(H) FFFDC16 to FFFDF16 FFFE016 to FFFE316 FFFE416 to FFFE716 FFFE816 to FFFEB16 FFFEC16 to FFFEF16 FFFF016 to FFF316 FFFF416 to FFFF716 FFFF816 to FFFFB16 FFFFC16 to FFFFF16 Do not use External interrupt by NMI pin
Interrupt source
Undefined instruction Overflow BRK instruction Address Match Single Step (Note) Watchdog timer DBC (Note) NMI Reset
Remarks
Interrupt on UND instruction Interrupt on INTO instruction If the vector is filled with FF16, program execution starts from the address shown by the vector in the variable vector table There is an address-matching interrupt enable bit Do not use
Note: Interrupts used for debugging purposes only
MSB LSB Low address Mid address 0000 0000 High address 0000
Vector address + 0 Vector address + 1 Vector address + 2 Vector address + 3
Figure 1.15: Format for specifying interrupt vector addresses 1-29
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.9:
Interrupt vectors (variable interrupt vector addresses)
Vector table addresses
Address(L) to Address(H)
Software interrupt number
Software interrupt number 0 Software interrupt number 4 Software interrupt number 6 Software interrupt number 7 Software interrupt number 10 Software interrupt number 11 Software interrupt number 12 Software interrupt number 13 Software interrupt number 14 Software interrupt number 15 Software interrupt number 16 Software interrupt number 17 Software interrupt number 18 Software interrupt number 19 Software interrupt number 20 Software interrupt number 21 Software interrupt number 22 Software interrupt number 23 Software interrupt number 24 Software interrupt number 25 Software interrupt number 26 Software interrupt number 27 Software interrupt number 28 Software interrupt number 29 Software interrupt number 30 Software interrupt number 31 Software interrupt number 32 to Software interrupt number 63
Interrupt source
BRK instruction USB Suspend USB Resume USB Start of Frame Bus collision detection DMA0 DMA1 Key input interrupt A-D UART2 transmit UART2 receive UART0 transmit UART0 receive UART1 transmit UART1 receive Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 USB Reset INT0 INT1 USB Function Software interrupt
Remarks
Cannot be masked by I flag
+0 to +3 (Note 1) +16 to +19 +24 to +27 +28 to +31 +40 to +43 +44 to +47 +48 to +51 +52 to +55 +56 to +59 +60 to +63 +64 to +67 +68 to +71 +72 to +75 +76 to +79 +80 to +83 +84 to +87 +88 to +91 +92 to +95 +96 to +99 +100 to +103 +104 to +107 +108 to +111 +112 to +115 +116 to +119 +120 to +123 +124 to +127 +252 to +255
Cannot be masked by I flag
Note 1:Address relative to address in interrupt table base address register (INTB)
1-30
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Interrupts
2.14.1 Interrupt control registers
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Peripheral I/O interrupts have their own interrupt control registers. Table 1.10 shows the addresses of the interrupt control registers. Figure 1.16 shows the interrupt control registers. The interrupt request bit is set by hardware to "0" when an interrupt request is received. The interrupt request bit can also be set by software to "0". (Do not set to "1".) INT0 and INT1 are triggered by the edges of external inputs. The edge polarity is selected using the polarity select bit. (Other interrupts are described elsewhere.) An interrupt must first be enabled before it can be used to cancel stop mode. Table 1.10: Addresses in interrupt control register
Symbol name SUSPIC RSMIC SOFIC BCNIC DM0IC DM1IC KUPIC ADIC S2TIC S2RIC S0TIC S0RIC S1TIC Address 004416 004616 004716 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 Interrupt control register UART1 receive Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 USB Reset INT0 INT1 USB Function Symbol name S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC RSTIC INT0IC INT1IC USBFIC Address 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16
Interrupt control register USB Suspend Interrupt USB Resume interrupt USB Start Of Frame Bus collision detection DMA0 DMA1 Key input interrupt A-D UART2 transmit UART2 receive UART0 transmit UART0 receive UART1 transmit
1-31
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol SUSPIC RSMIC BCNIC DMiIC(i=0, 1) KUPIC ADIC SiTIC(i=0 to 2) SiRIC(i=0 to 2) TAiIC(i=0 to 4) TBiIC(i=0 to 2) RSTIC USBFIC
Address 0044 16 004616 004A16 004B16, 004C16 004D16 004E16 005116, 0053 16, 004F 16 005216, 0054 16, 0050 16 005516 to 0059 16 005A16 to 005B 16 005C16 005F16
When reset XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2
Bit symbol
ILVL0
Bit name
Interrupt priority level select bit
b2 b1 b0
Function
000: 001: 010: 011: 100: 101: 110: 111: Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7
R
W
ILVL1
ILVL2
IR
Interrupt request bit
0 : Interrupt not requested 1 : Interrupt requested
(Note)
Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate.
Note: This bit can only be reset (= 0), but cannot be set ( = 1).
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbol INTiIC ( i= 0, 1) SOFIC
Address 005D16, 005E16 004716
When reset XX00X000 2 XX00X000 2
Bit symbol
ILVL0
Bit name
Interrupt priority level select bit
b2 b1 b0
Function
0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Always set to "0"
R
W
ILVL1
ILVL2
IR
Interrupt request bit
(Note 1)
POL
Polarity select bit
(Note 2)
Reserved bit
Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate.
Note 1: This bit can only be reset (=0), but cannot be set (=1). Note 2: For SOFIC (address 0047 1 6), a "0" should always be written.
Figure 1.16: Interrupt control registers
1-32
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Interrupts
2.14.2 Interrupt priority
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The order of priority when two or more interrupts are generated simultaneously is determined by both hardware and software. The interrupt priority levels determined by hardware are reset > NMI > DBC > watchdog timer > peripheral I/O interrupts > single-step > address matching interrupt. The interrupt priority levels determined by software are set in the interrupt control registers. Figure 1.17 shows the circuit that judges the interrupt hardware priority level. When two or more interrupts are generated simultaneously, the interrupt with the higher software priority is selected. However, if the interrupts have the same software priority level, the interrupt is selected according to the hardware priority set in the circuit. The selected interrupt is accepted only when the priority level is higher than the processor interrupt priority level (IPL) in the flag register (FLG) and the interrupt enable flag (I flag) is "1". Note that the reset, NMI, DBC, watchdog timer, single-step, address-match, BRK instruction, overflow, and undefined instruction interrupts are accepted regardless of the interrupt enable flag (I flag).
1-33
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Priority level of each interrupt INT1 USB Reset Timer B0 Timer A3 Timer A1 USB Resume USB Suspend USB Function INT0 Timer B1 Timer A4 Timer A2 USB SOF UART1 reception UART0 reception UART2 reception A-D conversion DMA1 Bus collision detection Timer A0 UART1 transmission UART0 transmission UART2 transmission Key input interrupt DMA0
Processor interrupt priority level (IPL)
Level 0 (initial value)
High
Priority of peripheral I/O interrupts (if priority levels are same)
Low
Interrupt enable flag (I flag) Address match Watchdog timer DBC NMI Reset
Interrupt request accepted
Figure 1.17: Interrupt resolution circuit 1-34
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
NMI Interrupt
2.14.3 Flag changes
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When an interrupt request is received, the stack pointer select flag (U flag) changes to "0" and the flag register (FLG) and program counter (PC) are saved to the stack area indicated by the interrupt stack pointer (ISP). Thereafter, the interrupt enable flag (I flag) and debug flag (D flag) change to "0" and the processor interrupt priority level (IPL) at the flag register (FLG) is replaced by the priority level of the received interrupt. However, when interrupt requests are received for software interrupts 32 to 63, the flag register (FLG) and program counter (PC) are saved to the stack shown by the stack pointer select flag (U flag) at the time the interrupt was received. The stack pointer select flag (U flag) does not change. The value of the processor interrupt priority level (IPL) in the flag register (FLG) differs in the case of reset, NMI, DBC, watchdog timer, single-step, address-match, BRK instruction, overflow, and undefined instruction interrupts. Table 1.11 shows how the IPL changes when interrupt requests are received. Table 1.11: Change of IPL state when interrupt request are accepted Change of IPL
Level 0 ("0002), is set Level 7 ("1112), is set Does not change Level 7 ("1112), is set Does not change Does not change Does not change
Interrupt
Reset NMI DBC Watchdog timer Single step Address match Software interrupt
2.13 NMI Interrupt
An NMI interrupt is generated when the input to the P85/NMI pin changes from "H" to "L". The NMI interrupt is a non-maskable external interrupt. The pin level can be checked in the Port P85 register (bit 5 at address 03F016). This pin cannot be used as a normal port input. 2.13.1 Notes: (1) (2) When not intending to use the NMI function, be sure to connect the NMI pin to VCC. Because the NMI interrupt is non-maskable, it cannot be disabled. When the NMI pin input is "L", do not set the microcomputer in stop mode or wait mode. The NMI interrupt is triggered by the falling edge, so the "L" level does not need to be maintained longer than necessary.
1-35
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Key-Input Interrupt 2.14 Key-Input Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
If the direction register of any of pin of Port0 or Port1 is set for input and a falling edge is input to that port, a key-input interrupt is generated. A key-input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. Figure 1.18 shows the block diagram of the keyinput interrupt.
Port P0i pull-up select bit Pull-up transistor
i=0~7; j=0~7
Port P0i direction register
Key input interrupt control register
(address 004D16)
P0i/KIj Pull-up transistor
i=0~7; j=8~15
KIO0
Port PXi pull-up select bit Port P1i direction register
Interrupt control circuit
Key input interrupt request
P1i/KIj
KIO1 5
Figure 1.18: Block diagram of key input interrupt 2.14.1 Enabling/disabling the key-input interrupt The key-input interrupt can be enabled and disabled using the key-input interrupt register (004D16). The key-input interrupt is affected by the interrupt priority level (IPL) and the interrupt enable flag (I flag). 2.14.2 Occurrence timing of the key-input interrupt With key-input interrupt acceptance enabled, ports P0 and P1, which are set to input, become keyinput interrupt pins (KI0 through KI15). A key-input interrupt occurs when a falling edge is input to a key-input interrupt pin. At this moment, the level of other key-input interrupt pins must be "H". No interrupt occurs when the level of any other key-input interrupt pins is "L". 2.14.3 How to determine a key-input interrupt A key-input interrupt occurs when a falling edge is input to one of 16 pins, but each pin has the same vector address.Therefore, read the input level of ports P0 and P1 in the key-input interrupt routine to determine the interrupted pin.
1-36
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Key-Input Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.14.4 Registers related to the key-input interrupt Figure 1.19 shows the memory map of key-input interrupt-related registers
Key-input interrupt control register (KUPIC)
04D16
Port 0 (P0) Port 1 (P1)
3E016 3E116
Port 0 direction register
3E216
Port 1 direction register
3E316
Pull-up control register 0
3FC16
Pull-up control register 1
3FD16
Figure 1.19: Memory Map of key input interrupt related registers
1-37
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Address Match Interrupt 2.15 Address Match Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). Figure 1.20 shows the address match interrupt-related registers.
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol AIER Bit symbol
Address 000916 Bit name Address match interrupt 0 enable bit Address match interrupt 1 enable bit
When reset XXXXXX002 Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled RW
AIER0 AIER1
Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate.
Address match interrupt register i (i = 0, 1)
(b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0
Symbol RMAD0 RMAD1
Address 001216 to 001016 001616 to 001416
When reset X0000016 X0000016
Function Address setting register for address match interrupt
Values that can be set R W 0000016 to FFFFF16
Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate.
Figure 1.20: Address match interrupt-related registers
1-38
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Watchdog Timer 2.16 Watchdog Timer
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is 39a 15-bit counter that decrements using the clock derived by dividing the internal clock using the prescaler. A watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. Bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or 128). Table 1.12 shows the periodic table for the watchdog timer. Table 1.12: CM06 Watchdog timer periodic table (f(XIN)=10MHz) CM17 CM16 Internal clock
10MHz 1 0 0 0 1 5MHz 1 0 0 1 0 2.5MHz 1 0 0 1 1 0.625MHz 1 0 1 Invalid Invalid 1.25MHz 1 Approx. 3.35s Approx. 6.71s Approx. 419.2ms Approx. 1.68s Approx. 838.8ms Approx. 838.8ms Approx. 209.7ms Approx. 419.2ms Approx. 104.9ms
WDC7
0 Approx. 52.4ms
Period
0
0
0
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by writing to the watchdog timer start register (address 000E16). Figure 1.21 shows the block diagram of the watchdog timer. Figure 1.22 shows the watchdog timerrelated registers.
1-39
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Watchdog Timer
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1/16 Internal clock 1/128
WDC7 = 0
Watchdog timer
WDC7 = 1
Write to the watchdog timer start register (address 000E16) Set to 7FFF16 RESET Watchdog timer interrupt request
Figure 1.21: Block diagram of watchdog timer
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol WDC Bit symbol
Address 000F16 Bit name
When reset 000XXXXX2 Function RW
High-order bit of watchdog timer Reserved bit Reserved bit
WDC7
Must always be set to 0 Must always be set to 0 Prescaler select bit 0 : Divided by 16 1 : Divided by 128
Watchdog timer start register
b7 b0
Symbol WDTS
Address 000E16
When reset Indeterminate RW
Function The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to 7FFF16 regardless of whatever value is written.
Figure 1.22: Watchdog timer control and start registers
1-40
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Frequency Synthesizer Circuit 2.17 Frequency Synthesizer Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The Frequency Synthesizer Circuit generates a 48MHz clock needed by the USB block and a clock fSYN that are both a multiple of the external input reference clock f(Xin). A block diagram of the circuit is shown in Figure 1.23.
EN USBC5
fUSB
f(Xin)
Prescaler
fPIN
Frequency Multiplier
fVCO
Frequency Divider
fSYN
FSCCR0
8 Bit
8 Bit
LS 8 Bit
FSP
03DE
FSM
03DD
FSC
03DC
FSD
03DF
FSCCR
03DB
Data Bus
Figure 1.23: Frequency Synthesizer Circuit The frequency synthesizer consists of a prescaler, frequency multiplier macro, a frequency divider macro, and five registers, namely FSP, FSM, FSC, FSD, and FSCCR. Clock f(Xin) is prescaled down using FSP to generate fPIN. fPIN is multiplied using FSM to generate an fVCO clock which is then divided using FSD to produce the clock fSYN. The fVCO clock is optimized for 48 MHz operation and is buffered and sent out of the frequency synthesizer block as signal fUSB. This signal is used by the USB block. 2.17.1 Prescaler Clock fPIN is a divided down version of clock f(Xin) (see Figure 1.24). The relationship between fPIN and the clock input to the prescaler f(Xin) is as follows: * fPIN = f(Xin) / 2(n+1) where n is a decimal number between 0 and 254. Setting FSP to 255 disables the prescaler and fPIN = f(Xin). * Note: f(Xin) frequency below 1 MHz is not recommended.
MSB 7
Bit 7
Bit 6
Bit 52
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LSB 0
Address: 03DE16 Access: R/W Reset: FF16
fPIN 12 MHz 1 MHz 2 MHz 3 MHz 6 MHz
FSP Dec(n) Hex(n) 255 FF 5 05 2 02 1 01 0 00
f(Xin)/2(n+1) = fPIN
f(Xin) 12.00 MHz 12.00 MHz 12.00 MHz 12.00 MHz 12.00 MHz
Figure 1.24: Frequency Synthesizer Prescaler Register (FSP)
1-41
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Frequency Synthesizer Circuit
2.17.2 Multiplier
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock fVCO is a multiplied up version of clock fPIN (See Figure 1.25). The relationship between fVCO and the clock input to the multiplier (fPIN) from the prescaler is as follows: * fVCO = fPIN x 2(n+1) where n is the decimal equivalent of the value loaded in FSM. Setting FSM to 255 disables the multiplier and fVCO = fPIN.
Note 1: n must be chosen such that fVCO equals 48 MHz. Note 2: Minimum fPIN is 1 MHz.
MSB 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
fPIN 1 MHz 2 MHz 4 MHz 6 MHz 12 MHz
FSM Dec(n) 33 11 5 3 1
Address: 03DD16 LSB Access: R/W 0 Reset: FF16
Hex(n) 4A 0B 05 03 01
fVCO 48.00 MHz 48.00 MHz 48.00 MHz 48.00 MHz 48.00 MHz
fPIN x 2(n+1) = fVCO
Figure 1.25: Frequency Synthesizer Multiply Register (FSM) 2.17.3 Divider Clock fSYN is a divided down version of clock fVCO (See Figure 1.26). The relationship between fSYN and the clock input to the divider (fVCO) from the multiplier is as follows: * fSYN = fVCO / 2(m+1) where m is the decimal equivalent of the value loaded in FSD. Setting FSD to 255 disables the divider and fSYN = fVCO.
MSB 7 LSB Address: 03DF16 0 Access: R/W Reset: FF16
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FSD Dec(m) 48.00 MHz 1 48.00 MHz 127 fVCO
Hex(m) 01 7F
fSYN 12.00 MHz 187.50 KHz
fVCO/2(m+1) = fSYN
Figure 1.26: Frequency Synthesizer Divide Register (FSD)
1-42
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Frequency Synthesizer Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The FSC0 bit in the FSC Control Register enables the frequency synthesizer block. When disabled (FSC0 = "0"), fVCO is held at either a high or low state. When the frequency synthesizer control bit is active (FSC0 = "1"), a lock status (LS = "1") indicates that fSYN and fVCO are the correct frequency. The LS and FSCO control bits in the FSC Control register are shown in Figure 1.27. When using the frequency synthesizer, a low-pass filter must be connected to the LPF pin. Once the frequency synthesizer is enabled, a delay of 2-5ms is recommended before the output of the frequency synthesizer is used. This is done to allow the output to stabilize. It is also recommended that none of the registers be modified once the frequency synthesizer is enabled as it will cause the output to be temporarily (2-5ms) unstable. The MCU clock source is selected via the Frequency Synthesizer Clock Control register (FSCCR). See Figure 1.28. Note: None of the registers must be written to once the frequency synthesizer is enabled and used as the system clock source (FSCCR register, address 03DB16, bit `0' set to `1') because it will cause the output of the PLL to freeze. Switch system back to f(XIN) and disable before modifying PLL registers.
Frequency Synthesizer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol FSC Bit symbol
FSE VCO0 VCO Gain Control VCO1 Reserved bit
Address 03DC16 Bit name
Frequency Synthesizer Enable 0 : Disable 1 : Enabled Bit 2 0 0 1 1 Bit 1 0: 1: 0: 1:
When reset 6016 Function RW
Lowest Gain (Note 1) Low Gain High Gain Highest Gain
Must always be set to "0" Bit 6 0 0 1 1 Bit 5 0: 1: 0: 1: Disabled Low Current Intermediate Current (Note 1) High Current
CHG0 LPF Current Control CHG1 LS Frequency Synthesizer Lock Status
0: 1:
Unlocked Locked
Note 1: Recommended
Figure 1.27: Frequency Synthesizer Control Register (FSC)
Frequency Synthesizer Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00
00000
Symbol FSCCR Bit symbol
FSCCR0 Reserved
Address 03DB16 Bit name Clock source selection
When reset 0016 Function
0 : Xin 1 : fsyn Must always be set to "0"
RW
Figure 1.28: Frequency Synthesizer Clock Control Register (FSCCR)
1-43
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Universal Serial Bus 2.18 Universal Serial Bus
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The Universal Serial Bus (USB) has the following features: * Complete USB Specification (version 1.1) Compatibility * Error-handling capabilities * FIFOs: * Endpoint * Endpoint * Endpoint * Endpoint * Endpoint 0: 1: 2: 3: 4: IN/OUT 32-byte IN 128-byte OUT IN 32-byte OUT IN 32-byte OUT IN 32-byte OUT
128-byte 32-byte 32-byte 32-byte
* Nine endpoints - control endpoint (Endpoint 0 - bi-directional) plus four IN and four OUT endpoints * Complete device configuration * Support of all device commands * Supports of full-speed functions * Support of all USB transfer types: * Isochronous * Bulk * Control * Interrupt * Suspend/Resume operation * On-chip USB transceiver with voltage converter * Start-of-frame interrupt and output pin 2.18.1 USB Function Control Unit (USB FCU) The implementation of the USB by this device is accomplished chiefly through the device's USB Function Control Unit (See Figure 1.29). The Function Control Unit's overall purpose is to handle the USB packet protocol layer. The Function Control Unit notifies the MCU that a valid token has been received. When this occurs, the data portion of the token is routed to the appropriate FIFO. The MCU transfers the data to, or from, the host by interacting with that endpoint's FIFO and CSR register. The USB Function Control Unit is composed of five sections: * Serial Interface Engine (SIE) * Generic Function Interface (GFI) * Serial Engine Interface Unit (SIU) * Microcontroller Interface (MCI) * USB Transceiver 2.18.1.1 Serial Interface Engine
The SIE interfaces to the USB serial data and handles deserialization/serialization of data, NRZI encoding decoding, clock extraction, CRC generation and checking, bit stuffing, and other items pertaining to the USB protocol such as handling inter-packet time-outs and packet ID (PID) decoding.
1-44
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Universal Serial Bus
2.18.1.2 Generic Function Interface
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The GFI handles all USB standard requests from the host through the control endpoint (endpoint zero), handles Bulk, Isochronous and Interrupt transfers through endpoints 1-4. The GFI handles read pointer reversal for re-transmission the current data set; write pointer reversal for reception of the last data set again and data toggle synchronization.
2.18.1.3 Serial Engine Interface Unit
The SIU block decodes the Address and Endpoint fields from the USB host.
2.18.1.4 Microcontroller Interface
The MCI block handles the Microcontroller interface and performs address decoding and synchronization of control signals.
2.18.1.5 USB Transceiver
The USB transceiver, designed to interface with the physical layer of the USB, is compliant with the USB Specification (version 1.1) for full-speed devices. It consists of two 6-ohm drivers, a receiver, and Schmitt triggers for single-ended receive signals. The transceiver also includes a voltage converter. The voltage converter can supply 3.0 - 3.6V to the transmitter when the rest of the chip (CPU, USB FCU) operates at 4.15 - 5.25V. To enable the voltage converter, set bit 4 of the USB Control Register (USBC) to a "1". To disable the voltage converter, set bit 4 of the USBC to a "0". Refer to Section 5.4 "USB Transceiver" for more detailed information.
SIU D+ CPU MCI SIE Transceiver
D-
GFI
FIFOs
Figure 1.29: USB Function Control Unit Block Diagram 2.18.2 USB Interrupts
There are five USB interrupts in this device: * USB Function interrupt * USB Reset interrupt * USB Suspend interrupt * USB Resume interrupt * USB Start-of-Frame (SOF) interrupt. The first four interrupts are used to control the data flow and USB power. The SOF interrupt is used to monitor the transfer of isochronous (ISO) data. Each of the five USB interrupts is enabled by setting the corresponding bit in the Interrupt Control Register of the Interrupt Control Unit. Because the USB Function Interrupt has multiple interrupt sources, another level of enabling is within the USB Interrupt Registers 1 & 2.
1-45
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Universal Serial Bus
2.18.2.1 USB Function Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The USB Function Interrupt can be triggered by 10 sources; many of these may be cause by several different events. Interrupt status flags associated with each source are contained in USBIS1 and USBIS2. Endpoints 1-4 have two interrupt status flags associated with it to control data transfer or to report a STALL/ UNDER_RUN/OVER RUN condition. The USB Endpoint x Out Interrupt Status Flag is set when * USB FCU successfully receives a packet of data OR * USB FCU sets the FORCE_STALL bit or OVER_RUN bit of the Endpoint x OUT CSR. The USB Endpoint x In Interrupt Status is set when * USB FCU successfully sends a packet of data OR * USB FCU sets the UNDER_RUN bit of the Endpoint x IN CSR. The USB Endpoint 0 (control endpoint) has one interrupt status bit associated with it to control data transfer or report a STALL condition. The USB Endpoint 0 Interrupt Status Flag is set when * USB FCU successfully receives/sends a packet of data * Sets the SETUP_END bit or the FORCE_STALL bit, OR clears the DATA_END bit in the Endpoint 0 IN CSR. The Overrun/Underrun Interrupt Status Flag is set when (applicable to endpoints used for isochronous data transfer) * Overrun condition occurs in a endpoint (CPU is too slow to unload the data from the FIFO), OR * Underrun condition occurs in an endpoint (CPU is too slow to load the data to the FIFO). Each endpoint interrupt and overrun/underrun interrupt is enabled by setting the corresponding bit in the USB Interrupt Enable Register 1 and 2.
2.18.2.2 USB Reset Interrupt
The USB Reset Interrupt Status Flag is set when the USB FCU sees a SE0 present on D+/D- for at least 2.5s. When this bit is set, all USB internal registers except INTST13 (bit5 of USBIS2) are reset to their default values. INTST13, the USB reset Interrupt Status Flag, is set to a "1" when the USB Reset is detected. When the CPU recognizes a USB Reset Interrupt, it needs to re initialize the USB FCU so that the USB operation can behave properly. It must also clear INTST13 by writing a "1" to this bit to allow a USB Reset Interrupt request to occur the next time a USB Reset is detected. Register RSTIC contains the USB Reset Interrupt's request bit and its interrupt priority select bits which are used to enable the interrupt and set its software priority level.
2.18.2.3 USB Suspend and Resume Interrupts
The USB Suspend Interrupt is set when the USB FCU does not detect any bus activity on D+/D- (in J-state) for at least 3ms. The USB Suspend Signaling Interrupt Status Flag (INTST15, bit 7 of USBIS2) is set to a "1" when the USB Suspend is detected. The CPU must clear INTST15 by writing a "1" to this bit to allow a USB Suspend Interrupt request to occur the next time a USB Suspend is detected. The USB Resume Signaling Interrupt Status Flag is set when a USB FCU is in the suspend state and detects non-idle signaling on the D+/D-. Register SUSPIC contains the USB Suspend Interrupt's request bit and its interrupt priority select bits which are used to enable the interrupt and set its software priority level. The USB Resume Interrupt request is set when the USB FCU is in the suspend state and detects non-idle signaling on D+/D-. The USB Signaling Interrupt Status Flag (INTST14, bit 6 of USBIS2) is set to a "1" when the USB Resume is detected. The CPU must clear INTST14 by writing a "1" to this bit to allow a USB Resume Interrupt request to occur the next time a USB Resume is detected. Register RSMIC contains the USB Resume Interrupt's request bit and its interrupt priority select bits, which are used to enable the interrupt an set its software priority level.
1-46
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Universal Serial Bus
2.18.2.4 USB SOF Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The USB SOF (Start-Of-Frame) Interrupt is used to control the transfer of isochronous data. The USB FCU generates a USB SOF Interrupt request when a start-of-frame packet is received. Register SOFIC contains the USB SOF Interrupt's request bit and its interrupt priority select bits, which are used to enable the interrupt and set its software priority level.
2.18.3 USB Endpoint FIFOs
The USB FCU has an IN (transmit) FIFO and an OUT (receive) FIFO for each endpoint. Each endpoint (except endpoint 0) can be configured to support either single packet mode (in which only a single data packet is allowed to reside in the endpoint's FIFO) or dual packet mode (in which up to two data packets are allowed to reside in the endpoint's FIFO). Dual packet mode provides support for back-to-back transmission or backto-back reception. The mode is automatically determined by the MAXP value. When MAXP > 1/2 of the endpoint's FIFO size, single packet mode is set. When MAXP <= 1/2 of the endpoint's FIFO size, dual packet mode is set. In the event of a bad transmission/reception, the USB FCU handles all the FIFO read/write pointer reversal and data set management tasks required. Throughout this specification, the terms "IN FIFO" and "OUT FIFO" usually refer to the FIFOs associated with a specific endpoint.
2.18.3.1 IN (Transmit) FIFOs
The CPU/DMA writes data to the endpoint's IN FIFO location specified by the FIFO write pointer, which automatically increments by "1" after a write. The CPU/DMA should only write data to the IN FIFO when the IN_PKT_RDY bit of the associated IN CSR is a "0". * Endpoint 0 IN FIFO Operation: The CPU writes a "1" to the IN_PKT_RDY bit of Endpoint 0 CSR after it finishes writing a packet of data to the IN FIFO. The USB FCU clears the IN_PKT_RDY bit after the packet has been successfully transmitted to the host (i.e., ACK is received from the host) or the SETUP_END bit of the IN CSR is set to a "1". * Endpoint 1-4 IN FIFO Operation when AUTO_SET (bit 7 of Endpoint x IN CSR) = "0" (disabled): MAXP > 1/2 of the IN FIFO size: The CPU writes a "1" to the IN_PKT_RDY bit of the associated IN CSR after the CPU/DMAC finishes writing a packet of data to the IN FIFO. The USB FCU clears the IN_PKT_RDY bit after the packet has been successfully transmitted to the host (which is assumed for isochronous transfers and is concluded when an ACK is received from the host for non-isochronous transfers). MAXP <= 1/2 of the IN FIFO size: The CPU writes a "1" to the IN_PKT_RDY bit of the associated IN CSR after the CPU/DMAC finishes writing a packet of data to the IN FIFO. The USB FCU clears the IN_PKT_RDY bit as soon as the IN FIFO is ready to accept another data packet. (The FIFO can hold up to two data packets at the same time in this configuration for back-to-back transmission.) * Endpoint 1-4 IN FIFO Operation when AUTO_SET (bit 7 of Endpoint x IN CSR) = "1" (enabled): MAXP > 1/2 of the IN FIFO size: When the number of bytes of data equal to the MAXP (maximum packet size) has been written to the IN FIFO by the CPU/DMAC, the USB FCU sets the IN_PKT_RDY bit of the associated IN CSR to a "1" automatically. The USB FCU clears the IN_PKT_RDY bit after the packet has been successfully transmitted to the host (which is assumed for isochronous transfers and is concluded when an ACK is received from the host for non-isochronous transfers). MAXP <= 1/2 of the IN FIFO size: When the number of bytes of data equal to the MAXP (maximum packet size) has been written to the IN FIFO by the CPU/DMAC, the USB FCU sets the IN_PKT_RDY bit to a "1" automatically. The USB FCU clears the IN_PKT_RDY bit as soon as the IN FIFO is ready to accept another data packet. (The FIFO can hold up to two data packets at the same time in this configuration for back-to-back transmission.) A software or a hardware flush causes the USB FCU to act as if a packet has been successfully transmitted out to the host. When there is one packet in the IN FIFO, a flush causes the IN FIFO to be empty. When there are two packets in the IN FIFO, a flush causes the older packet to be flushed out from the IN FIFO. A flush also updates the IN FIFO status bits IN_PKT_RDY and TX_NOT_EMPTY of the associated IN CSR.
1-47
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Universal Serial Bus
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The status of endpoint 1-4 IN FIFOs for both of the above cases can be obtained from the IN CSR of the corresponding IN FIFO as shown in Table 1.13 .
Table 1.13:
TA FIFO Status TX_NOT_EMPTY
0 1 0 1 No data packet in IN FIFO One data packet in IN FIFO if MAXP <= 1/2 of the FIFO size./ Invalid when MAXP>1/2 of the FIFO size Invalid Two data packets in IN FIFO when MAXP <=1/2 of the FIFO size One data packet in IN FIFO when MAXP > 1/2 of the FIFO size
IN_PKT_RDY
0 0 1 1
IN FIFO Status
2.18.3.2 Out (Receive) FIFOs
The USB FCU writes data to the endpoint's OUT FIFO location specified by the FIFO write pointer, which automatically increments by one after a write. When the USB FCU has successfully received a data packet, it sets the OUT_PKT_RDY bit of the corresponding OUT CSR to a "1". The CPU/DMAC should only read data from the OUT FIFO when the OUT_PKT_RDY bit of the OUT CSR is a "1". * Endpoint 0 OUT FIFO Operation: The USB FCU sets the OUT_PKT_RDY bit to a "1" after it has successfully received a packet of data from the host. The CPU sets bit SERVICED_OUT_PKT_RDY to a "1" to clear the OUT_PKT_RDY bit after the packet of data has been unloaded from the OUT FIFO by the CPU. * Endpoint 1-4 OUT FIFO Operation when AUTO_CLR (bit 7 of Endpoint x OUT CSR) = "0" (disabled): MAXP > 1/2 of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit of the associated IN CSR to a "1" after it has successfully received a packet of data from the host. The CPU writes a "0" to the OUT_PKT_RDY bit after the packet of data has been unloaded from the OUT FIFO by the CPU/DMAC. MAXP <= 1/2 of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit of the associated IN CSR to a "1" after it has successfully received a packet of data from the host. The CPU writes a "0" to the OUT_PKT_RDY bit after the packet of data has been unloaded from the OUT FIFO by the CPU/DMAC. If another packet is in the OUT FIFO, the OUT_PKT_RDY bit will be set to a "1" again almost immediately (such that it may appear that the OUT_PKT_RDY bit remains a "1"). In this configuration, the FIFO can store up to two data packets at the same time for back-to-back reception. * Endpoint 1-4 OUT FIFO Operation when AUTO_CLR (bit 7 of Endpoint x OUT CSR) = "1" (enabled): MAXP > 1/2 of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit of the associated IN CSR to a "1" after it has successfully received a packet of data from the host. The USB FCU clears the OUT_PKT_RDY bit to a "0" automatically when the number of bytes of data equal to the MAXP (maximum packet size) has been unloaded from the OUT FIFO by the CPU/DMAC. MAXP <= 1/2 of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit of the associated IN CSR to a "1" after it has successfully received a packet of data from the host. The USB FCU clears the OUT_PKT_RDY bit to a "0" automatically when the number of bytes of data equal to the MAXP (maximum packet size) has been unloaded from the OUT FIFO by the CPU/DMAC. If another packet is in the OUT FIFO, the OUT_PKT_RDY bit will be set to a "1" again almost immediately (such that it may appear that the OUT_PKT_RDY bit remains a "1"). In this configuration, the FIFO can store up to two data packets at the same time for back-to-back reception. A software flush causes the USB FCU to act as if a packet has been unloaded from the OUT FIFO. If there is one packet in the OUT FIFO, a flush will cause the OUT FIFO to be empty. If there are two packets in the OUT FIFO, a flush will cause the older packet to be flushed out from the OUT FIFO.
1-48
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Universal Serial Bus
2.18.3.3 Interrupt Endpoints:
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Any endpoint can be used for interrupt transfers. For normal interrupt transfers, the interrupt transactions behave the same as bulk transactions, i.e., no special setting is required. The IN endpoints may also be used to communicate rate feedback information for certain types of isochronous functions. This is done by setting the INTPT bit in the IN CSR register of the corresponding endpoint. The following outlines the operation sequence for an IN endpoint used to communicate rate feedback information: 1. Set MAXP > 1/2 of the endpoint's FIFO size; 2. Set INTPT bit of the IN CSR; 3. Flush the old data in the FIFO; 4. Load interrupt status information and set IN_PKT_RDY bit in the IN CSR; 5. Repeat steps 3 & 4 for all subsequent interrupt status updates.
2.18.4 USB Special Function Registers The MCU controls USB operation through the use of special function registers (SFR). This section describes each USB related SFR. Some USB special function registers have a mix of read/write, read only, and write only register bits. Additionally, the bits may be configured to allow the user to write only a "0" or a "1" to individual bits. * When accessing these registers, writing a "0" to a register that can only be set to a "1" by the CPU has no effect on that register bit. * Writing a "1" to a register that can only be set to a "0" by the CPU has not effect on that register bit. Each figure and description of the special function registers details this operation. All USB Special Function Registers, with the exception of USB Attach/Detach (001F16) and USB control (000C16) must use byte access. Work access is prohibited for USB internal registers (030016 033C16). The contents of all USB Special Functions Registers, including USB Attach/Detach and USB Control, are preserved on a software reset. 2.18.4.1 USB Attach/Detach Register
The USB Attach / Detach Register is shown in Figure 1.30. The register is used to attach and detach the USB function from a USB host without physically disconnecting the USB cable. This functionality is enabled by setting P83_SECOND to a "1". Doing this forces P83 to operate as a pull-up for D+ (through an external 1.5k ohm resistor). The port driver is tri-stated and a "1" is always read from the port bit in this mode. When the ATTACH/DETACH bit is a "1" (and P83_SECOND is a "1"), P83 is driven with the voltage on EXTCAP, causing D+ to be pulled up and the host to detect an attach. When the ATTACH/DETACH bit is a "0" (and P83_SECOND is a "1"), P83 is tri-stated, causing D+ to be pulled down (through the cable and 15k ohm resistor on the host/hub side) and a detach to be registered by the host. A 1.5k ohm pull-up resistor must be connected externally from P83 to D+ when this functionality is used. When it is not used, the 1.5k ohm resistor should be placed between EXTCAP and D+.
USB Attach/Detach Register
b7 b6 b5 b4 b3 b2 b1 b0
000000
Symbol USBAD Bit symbol P83_2nd Attach/ Detach Reserved Bit name Port 83-Second
Address 001F16
When reset 0016 Function RW
0 : Normal mode for Port 8_3 1 : Forces Port 8_3 to operate as pull up for D+. 0 : Tri-states, P8_3 causing the host to detect a detach 1 : Drives P8_3 with voltage on EXTCAP, causing the host to detect an attach Must always be set to "0"
Attach/Detach
Figure 1.30: USB Attach/Detach Register 1-49
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Universal Serial Bus
2.18.4.2 USB Control Register
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The USB Control Register, shown in Figure 1.31, is used to control the USB FCU. This register is not reset by a USB reset signaling. After the USB is enabled (USBC7 set to "1"), a minimum delay of 250ns (three 12 MHz clock periods) is needed before performing any other USB register read/write operations.
USB Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00
0
Symbol USBC
Address 000C16 Bit name
When reset 0016 Function Must always be set to "0" RW
Bit symbol
Reserved
USBC3 USBC4
USBC5
Tranceiver voltage converter High/Low current mode selection USB tranceiver voltage converter enable bit USB clock enable bit USB SOF port select bit USB enable bit
USBC6 USBC7
Note Note Note Note 1: 2: 3: 4:
0: 1: 0: 1: 0: 1: 0: 1: 0: 1:
High current mode (Note 1) Low current mode (Note 2) Disabled Enabled Disabled Enabled Disabled (Note 3) Enabled Disabled (Note 4) Enabled
For USB normal operation For USB suspend operation P86 is used as GPIO pin All USB internal registers are held at their default values.
Figure 1.31: USB Control Register 2.18.4.3 USB Function Address Register
The USB Function Address Register, shown in Figure 1.32, maintains the 7-bit USB address assigned by the host. The USB FCU uses this register value to decode USB token packet addresses. At reset, when the device is not yet configured, the value is 0016. For the procedures on how to update this register, refer to Application Notes USB Consecutive Set Address.
Function Address Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol USBA Bit symbol
FUNAD0-6 Reserved
Address 030016 Bit name
Function Address
When reset 0016 Function
7-bit programmable Function Address
Must always be set to "0"
RW
Figure 1.32: USB Function Address Register
1-50
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Universal Serial Bus
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.18.4.4 The USB Power Management Register
The USB Power Management Register, shown in Figure 1.33, is used for power management in the USB FCU. * SUSPEND Detection Flag: When the USB FCU does not detect any bus activity on D+/D- for at least 3ms (and D+/D- are in the J-state), it sets the Suspend Detection Flag and generates an interrupt. This bit is cleared when signaling from the host is detected on D+/D- (which sets the Resume Detection Flag and generates an interrupt), or the Remote Wake-up Bit is set and then cleared by the CPU. If the USB clock was disabled during the suspend state, the SUSPEND Detection Flag is not cleared until after the USB clock is re-enabled. * RESUME Detection Flag: When the USB FCU is in the suspend state and detects activity on D+/D- from the host, it sets the Resume Detection Flag and generates an interrupt. The CPU writes a "1" to INTST14 (bit 6 of USB Interrupt Status Register 2) to clear this flag. * WAKEUP Control Bit: The CPU writes a "1" to the WAKEUP Control Bit for remote wake-up. While this bit is set and the USB FCU is in suspend mode, resume signaling is sent to the host. The CPU must keep this bit set for a minimum of 10ms and a maximum of 15ms before writing a "0" to this bit.
USB Power Management Register
b7 b6 b5 b4 b3 b2 b1 b0
00000
Symbol USBPM Bit symbol
SUSPEND RESUME WAKEUP
Reserved
Address 030116 Bit name Function
When reset 0016 RW
Note 1
USB Suspend Detection Flag USB Resume Detection Flag USB Remote Wakeup Bit
0 : No USB suspend signal detected 1 : USB suspend signal detected 0 : No USB resume signal detected 1 : USB resume signal detected 0 : End remote resume signaling 1 : Remote resume signaling (Note 2)
Must always be set to "0"
Note 1
Note 1: Write "0" only or Read Note 2: If SUSPEND = "1"
Figure 1.33: USB Power Management Register
1-51
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Universal Serial Bus
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.18.4.5 USB Interrupt Status Registers 1 and 2
USB Interrupt Status Registers 1 and 2, shown in Figure 1.34 and Figure 1.35, are used to indicate the condition that caused a USB function interrupt and USB Reset, Suspend and Resume Interrupts to the CPU. A "1" indicates the corresponding condition caused an interrupt. The USB Interrupt Status Register bits can be cleared by writing a "1" to the corresponding bit. INTST0 is set to a "1" by the USB FCU when (in Endpoint 0 CSR): *A packet of data is successfully received (EP0CSR0 - OUT_PKT_RDY is set by the USB FCU) *A packet of data is successfully sent (EP0CSR - IN_PKT_RDY is cleared by the USB FCU) *EP0CSR3 (DATA_END) bit is cleared by the USB FCU *EP0CSR4 (FORCE_STALL) bit is set by the USB FCU *EP0CSR5 (SETUP_END) bit is set by the USB FCU INTST2, INTST4, INTST6 or INTST8 is set to a "1" by the USB FCU when (in Endpoint x IN CSR): *A packet of data is successfully sent (INXCSR0 - IN_PKT_RDY is cleared by the USB FCU) *INXCSR1 (UNDER_RUN) bit is set by the USB FCU INTST3, INTST5, INTST7 or INTST9 is set to a "1" by the USB FCU when (in Endpoint xOUT CSR): *A packet of data is successfully received (OUTXCSR0 - OUT_PKT_RDY is set by the USB FCU) *OUTXCSR1 (OVER_RUN) bit is set by the USB FCU *OUTXCSR4 (FORCE_STALL) bit is set by the USB FCU INTST12 is set to a "1" by the USB FCU when an overrun or underrun condition occurs in any of the endpoints. INTST13 is set to a "1" by the USB FCU when a USB reset signaling from the host is received. All internal register bits except this bit are reset to their default values when the USB reset is received. INTST14 is set to a "1" by the USB FCU when the USB FCU is in the suspend state and non-idle signaling is received from D+/D-. INTST15 is set to a "1" by the USB FCU when D+/D- are in the idle state for more than 3ms.
USB Interrupt Status Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol USBIS1 Bit symbol
INTST0
Reserved
Address 030216 Bit name Function
When reset 0016 RW
USB Endpoint 0 Interrupt Status Flag
0 : No interrupt request issued 1 : Interrupt request issued
Must always be set to "0"
INTST2 INTST3 INTST4 INTST5 INTST6 INTST7
USB Endpoint 1 IN Interrupt Status Flag USB Endpoint 1 OUT Interrupt Status Flag USB Endpoint 2 IN Interrupt Status Flag USB Endpoint 2 OUT Interrupt Status Flag USB Endpoint 3 IN Interrupt Status Flag USB Endpoint 3 OUT Interrupt Status Flag
0 : No interrupt request issued 1 : Interrupt request issued 0 1 0 1 0 1 0 1 0 1 : : : : : : : : : : No interrupt request issued Interrupt request issued No interrupt request issued Interrupt request issued No interrupt request issued Interrupt request issued No interrupt request issued Interrupt request issued No interrupt request issued Interrupt request issued
Figure 1.34: USB Interrupt Status Register 1
1-52
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Universal Serial Bus
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
USB Interrupt Status Register 2
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol USBIS2 Bit symbol
INTST8 INTST9
Reserved
Address 030316 Bit name Function
When reset 0016 RW
USB Endpoint 4 IN Interrupt Status Flag USB Endpoint 4 OUT Interrupt Status Flag
0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued
Must always be set to "0"
INTST12 INTST13 INTST14 INTST15
USB Overrun/Underrun Interrupt Status Flag USB Reset Interrupt Status Flag USB Resume Signaling Interrupt Status Flag USB Suspend Signaling Interrupt Status Flag
0 1 0 1 0 1
: : : : : :
No interrupt request issued Interrupt request issued No interrupt request issued Interrupt request issued No interrupt request issued Interrupt request issued
0 : No interrupt request issued 1 : Interrupt request issued
Figure 1.35: USB Interrupt Status Register 2 2.18.4.6 Clearing of the USB Interrupt Status Registers
The USB Interrupt Status Register 1 and 2 are used to indicate pending interrupts for a given source. The USB FCU sets the interrupt status bits. The CPU writes a "1" to each status bit to clear it. Because the USB Function Interrupt has multiple sources that can generate an interrupt, it is recommended that the user first read the two status registers and store them in variables then write back the same value for clearing all the existing interrupts that were pending when the status registers were read. This procedure prevents any interrupt that occurs after the status registers are read from being cleared by the `write-back' operation. The CPU must read, then write both status registers, writing to status register 1 first and status register 2 second to guarantee proper operation. The upper three bits of the value written back to USBIS2 should always be "000" to prevent any of the USB Reset, Suspend and Resume Status Flags from being cleared. The USB Reset, Suspend and Resume Status Flags are contained in USBIS2 along with the USB Endpoint 4 In/Out Interrupt Status Flags and the USB Overrun/Underrun Interrupts Status Flag. Because the flags are not all sources for the same interrupt, use caution when clearing one or more of the flags to avoid inadvertently clearing other flags. The Reset, Suspend and Resume Status Flags should be cleared individually by writing a byte value with at "1" only at the position corresponding to the flag to be cleared. The USB Endpoint 4 In/ Out Interrupt status Flags and the USB Overrun/Underrun Interrupt Status Flag should be cleared as described in the preceding paragraph because they are sourced for the USB Function Interrupt. "Read-modify-write' instructions, such as "BCLR' and `BSET', should not be used to clear any of the interrupt status bits in USBIS1 or USBIS2. Using these instructions could cause pending interrupts to be cleared without the firmware's knowledge.
2.18.4.7 The USB Function Interrupt Enable Registers 1 and 2
The USB Function Interrupt Enable Registers 1 and 2, shown in Figure 1.36 and Figure 1.37, are used to enable the corresponding interrupt status conditions that can generate a USB Function Interrupt. When the bit to a corresponding interrupt condition is "0", that condition does not generate a USB function interrupt. When the bit is a "1", that condition can generate a USB function interrupt. At reset, all USB function interrupt status conditions are enabled.
1-53
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Universal Serial Bus
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
USB Interrupt Enable Register 1
b7 b6 b5 b4 b3 b2 b1 b0
1
Symbol USBIE1 Bit symbol
INTEN0
Reserved
Address 030416 Bit name Function
0 : Interrupt disabled 1 : Interrupt enabled
Must always be set to "1"
When reset FF16 RW
USB Endpoint 0 Interrupt Enable Bit
INTEN2 INTEN3 INTEN4 INTEN5 INTEN6 INTEN7
USB Endpoint 1 IN Interrupt Enable Bit USB Endpoint 1 OUT Interrupt Enable Bit USB Endpoint 2 IN Interrupt Enable Bit USB Endpoint 2 OUT Interrupt Enable Bit USB Endpoint 3 IN Interrupt Enable Bit USB Endpoint 3 OUT Interrupt Enable Bit
0 : Interrupt disabled 1 : Interrupt enabled 0 1 0 1 0 1 0 1 : : : : : : : : Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt disabled enabled disabled enabled disabled enabled disabled enabled
0 : Interrupt disabled 1 : Interrupt enabled
Figure 1.36: USB Interrupt Enable Register 1
USB Interrupt Enable Register 2
b7 b6 b5 b4 b3 b2 b1 b0
001
0
0
Symbol USBIE2 Bit symbol
INTEN8 INTEN9
Address 030516 Bit name Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
Must always be set to "0"
When reset 3316 RW
USB Endpoint 4 IN Interrupt Enable Bit USB Endpoint 4 OUT Interrupt Enable Bit
Reserved
INTEN12
Reserved Reserved
USB Overrun/Underrun Interrupt Enable Bit
0 : Interrupt disabled 1 : Interrupt enabled
Must always be set to "1" Must always be set to "0"
Figure 1.37: USB Interrupt Enable Register 2
1-54
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Universal Serial Bus
2.18.4.8 USB Frame Number Registers
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The USB Frame Number Low Register, shown in Figure 1.38, contains the lower 8 bits of the 11-bit frame number received from the host. The USB Frame Number High Register, shown in Figure 1.39 contains the upper 3 bits of the 11-bit frame number received from the host.
USB Frame Number Low Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol USBSOFL Bit symbol
FN0 to FN7
Address 030616 Bit name
When reset 0016 Function RW
Lower 8 bits of the 11-bit frame number issued with a SOF token
X
Figure 1.38: USB Frame Number Low Register
USB Frame Number High Register
b7 b6 b5 b4 b3 b2 b1 b0
0000
0
Symbol USBSOFH Bit symbol
FN8 FN9 FN10
Address 030716 Bit name
When reset 0016 Function RW
Upper 3 bits of the 11-bit frame number issued with a SOF token Must always be set to "0"
X
Reserved
X
Figure 1.39: USB Frame Number High Register 2.18.4.9 USB ISO Control Register
The USB ISO Control Register, shown in Figure 1.40, contains two global bits, ISO_UPD and AUTO_FL for controlling endpoints 1-4 isochronous data transfer. When ISO_UPD = "0", a data packet in an endpoint's IN FIFO is always `ready to transmit' upon receiving the next IN_TOKEN from the host (with matched address and endpoint number) if the endpoint's IN_PKT_RDY is set. When ISO_UPD = "1" and the ISO/TOGGLE_INIT bit of the corresponding endpoint's IN CSR is set, the internal `ready to transmit' signal to the transmit control logic is not activated when the endpoint's IN_PKT_RDY is set. Instead, it is activated when the next SOF is received, this way, the data loaded in frame n is transmitted out in frame n+1. The ISO_UPD bit is a global bit for endpoints 1-4 and works with isochronous pipes only. When AUTO_FL = "1", ISO_UPD = "1", a particular IN endpoint's ISO/TOGGLE_INIT bit is set, and the IN endpoint's IN_PKT_RDY = "1", the USB FCU detects a SOF packet and the USB FCU automatically flushes the oldest packet from the IN FIFO. In this case, IN_PKT_RDY = "1", indicates that two data packets are in the IN FIFO. Because double buffering is a requirement for ISO transfer, MAXP must be set to less than or equal to 1/2 of the FIFO size.
USB ISO Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00000
0
Symbol USBISOC Bit symbol
Reserved
Address 030816 Bit name
0: 1: 0: 1:
When reset 0016 Function RW
Must always be set to "0"
AUTO_FL ISO_UPD
AUTO_FLUSH Bit ISO_UPDATE Bit
Hardware auto FIFO flush diabled Hardware auto FIFO flush enabled ISO_UPDATE disabled ISO_UPDATE enabled
Figure 1.40:
USB ISO Control Register
1-55
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Universal Serial Bus
2.18.4.10 USB DMAx Request Registers
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The USB DMAx Request Registers, shown in Figure 1.41 and Figure 1.42, are used to select which USB Endpoint x FIFO read/write requests are selected as the DMAC channel 0 or channel 1 request source. The USB DMA0 (DMA1) Request Register should have only one bit set at any given time. When multiple bits are set, no request is selected.
USB DMA0 Request Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol USBSAR0 Bit symbol
DMA0R0 DMA0R1 DMA0R2 DMA0R3 DMA0R4 DMA0R5 DMA0R6 DMA0R7 Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint
Address 030916 Bit name
1 IN FIFO write request selection bit 2 IN FIFO write request selection bit 3 IN FIFO write request selection bit 4 IN FIFO write request selection bit 1 OUT FIFO read request selection bit 2 OUT FIFO read request selection bit 3 OUT FIFO read request selection bit 4 OUT FIFO read request selection bit
When reset 0016 Function
0 : Not selected 1 : Selected
RW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 1.41:
USB DMA0 Request Register
USB DMA1 Request Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol USBSAR1 Bit symbol
DMA1R0 DMA1R1 DMA1R2 DMA1R3 DMA1R4 DMA1R5 DMA1R6 DMA1R7 Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint
Address 030A16 Bit name
1 IN FIFO write request selection bit 2 IN FIFO write request selection bit 3 IN FIFO write request selection bit 4 IN FIFO write request selection bit 1 OUT FIFO read request selection bit 2 OUT FIFO read request selection bit 3 OUT FIFO read request selection bit 4 OUT FIFO read request selection bit
When reset 0016 Function
0 : Not selected 1 : Selected
RW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 1.42:
USB DMA1 Request Register
2.18.4.11 USB Endpoint Enable Register
The USB Endpoint Enable Register, shown in Figure 1.43, is used to enable/disable an individual endpoint. Endpoint 0 is always enabled and cannot be disabled by firmware. All endpoints are enabled after reset.
USB Endpoint Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol USBEPEN Bit symbol
EP1_OUT EP1_IN EP2_OUT EP2_IN EP3_OUT EP3_IN EP4_OUT EP4_IN
Address 030B16 Bit name
Endpoint 1OUT FIFO Enable bit Endpoint 1 IN FIFO Enable bit Endpoint 2OUT FIFO Enable bit Endpoint 2 IN FIFO Enable bit Endpoint 3 OUT FIFO Enable bit Endpoint 3 IN FIFO Enable bit Endpoint 4 OUT FIFO Enable bit Endpoint 4 IN FIFO Enable bit
When reset FF16 Function
0 : Disabled 1 : Enabled
RW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 1.43:
USB Endpoint Enable Register
1-56
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Universal Serial Bus
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.18.4.12 Endpoint 0 CSR (Control and Status Register)
The Endpoint 0 CSR (Control and Status Register), shown in Figure 1.44 contains the control and status information of Endpoint 0. *EP0CSR0 (OUT_PKT_RDY): The USB FCU sets this bit to a "1" after it receives a valid SETUP/OUT token from the host. The CPU clears this bit after unloading the packet from the FIFO by writing a "1" to EP0CSR6. The CPU should not clear the OUT_PKT_RDY bit before it finishes decoding the host request. When EP0CSR2 (SEND_STALL) needs to be set (because the CPU decodes an invalid or unsupported request) a "1" should be written to EP0CSR6 and EP0CSR2 at the same time using the same instruction. * EP0CSR1 (IN_PKT_RDY): The CPU writes a "1" to this bit after it finishes writing a packet of data to the endpoint 0 FIFO. The USB FCU clears this bit after the packet is successfully transmitted to the host, or the EP0CSR5 (SETUP_END) bit is set. * EP0CSR2 (SEND_STALL): The CPU writes a "1" to this bit when it decodes an invalid or unsupported standard device request from the host. When the OUT-PKT_RDY bit is a "1" at the time the CPU wants to set the SEND_STALL bit to a "1", the CPU must also set SERVICED_OUT_PKT_RDY to a "1" to clear the OUT-PKT_RDY at the same time as setting the SEND_STALL bit. The USB FCU returns a STALL handshake for all subsequent IN/OUT transactions (during control transfer data or status stages) while this bit is set. The CPU writes a "0" to clear it after it receives a new SETUP packet. It is up to the firmware to decide what SETUP packet should lead the clearing of the SEND_STALL bit. * EP0CSR3 (DATA_END): The CPU writes a "1" to this bit when it writes (IN data phase) or reads (OUT data phase) the last packet of data to or from the FIFO. The CPU sets this bit at the same time as it sets the last IN_PKT_RDY bit or sets the last SERVICED_OUT_PKT_RDY bit.This bit indicates to the USB FCU that the specific amount of data in the setup phase is transferred. The USB FCU advances to the status phase once this bit is set. When the status phase completes, the USB FCU clears this bit. When this bit is set to a "1", and the host requests or sends more data, the USB FCU returns a STALL handshake and terminates the current control transfer. * EP0CSR4 (FORCE_STALL): The USB FCU sets this bit to a "1" to report an error status when one of the following occur: * Host sends an IN token in the absence of a SETUP stage * Host sends a bad data toggle in the STATUS stage, (i.e. DATA0 is used) * Host sends a bad data toggle in the SETUP stage, (i.e. DATA1 is used) * Host request more data than specified in the SETUP state, (i.e. IN token comes after DATA_END bit is set) * Host sends more data than specified in the SETUP state, (i.e. OUT token comes after DATA_END bit is set) * Host sends larger data packet than MAXP size All of the conditions stated (except bad data toggle in the SETUP stage) cause the device to send a STALL handshake for the current IN/OUT transaction. For the bad data toggle in the SETUP state, the device sends ACK for the SETUP stage and then sends STALL for the next IN/OUT transaction. A STALL handshake caused by the above listed conditions lasts for one transaction and terminates the ongoing control transfer. Any packet after the STALL handshake will be seen as the beginning of a new control transfer. The CPU writes a "0" to clear the FORCE_STALL status bit. * EP0CSR5 (SETUP_END): The USB FCU sets this bit to a "1" if a control transfer has ended before the specific length of data is transferred during the data phase (status phase starts before DATA_END bit is set) or a control transfer has ended before a new SETUP has arrived and before successfully completing the status phase. The CPU clears this bit by writing a "1" to IN0CSR7. Once the CPU detects the SETUP_END bit as set, it should stop accessing the FIFO to service the previous setup transaction. If the SETUP_END is caused by the reception of the SETUP packet prior to the end of the current control transfer, the OUT_PKT_RDY bit is set once the reception of the SETUP packet has completed (without errors). After the OUT_PKT_RDY bit is set, the new SETUP packet
1-57
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Universal Serial Bus
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
data will be in the FIFO. For this case, because the SETUP_END bit is set near the beginning of the packet when the SETUP PID is encountered and the OUT_PKT_RDY bit is set at the end of the packet, the value read from EP0IN_CSR in the USB functional interrupt routine may only show that the SETUP_END bit as "1" instead of both the SETUP_END and OUT_PKT_RDY bits. * EP0CSR6 and EP0CSR7: These bits are used to clear EP0CSR0 and EP0CSR5 respectively. Writing a "1" to these bits clears the corresponding register bit.
USB Endpoint 0 Control and Status Register (Note 5)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol EP0CS Bit symbol
EP0CSR0 EP0CSR1 EPOCSR2 EPOCSR3 EP0CSR4 EPOCSR5
Address 031116 Bit name
OUT_PKT_RDY Flag IN_PKT_RDY Bit SEND_STALL Bit DATA_END Bit FORCE_STALL Flag SETUP_END Flag 0 1 0 1 0 1 0 1 0 1 0 1 : : : : : : : : : : : :
When reset 0016 Function
Not ready Ready Not ready Ready No action Stall Endpoint 0 by CPU No action Last packet transferred from/to FIFO No action Stall Endpoint 0 by USB FCU No action Control transfer ended before specific length of data transferred during data phase No change Clear the OUT_PKT_RDY bit (EPOCSR0) No change Clear the STUP-END bit (EP0CSR5)
RW
00
Note 1
00
Note 2
00 00 00 00
Note 1
Note 2 Note 3
EP0CSR6 EPOCSR7 Note Note Note Note Note
SERVICED_OUT_PKY_RDY Bit SERVICED_SETUP_END Bit
0: 1: 0: 1:
00
Note 4
00
Note 4
1: Read only 2: Write "1" only or Read 3: Write "0" only or Read 4: Write only - Read "0" 5: Refer to Section 5.5 "Programming Notes" for this register
Figure 1.44: USB Endpoint 0 CSR 2.18.4.13 USB Endpoint 0 MAXP Register
The USB Endpoint 0 MAXP Register, shown in Figure 1.45, indicates the maximum packet size (MAXP) of Endpoint 0 IN/OUT packet. The default value for Endpoint 0 MAXP is 8 bytes.
USB Endpoint 0 MAXP Register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol EP0MP Bit symbol
EP0MXP0 to EP0MXP5
Address 031316 Bit name
Maximum packet size (MAXP) of Endpoint 0 IN/OUT packet
When reset 0816 Function RW
Reserved
Must always be set to "0"
Figure 1.45: USB Endpoint 0 MAXP
1-58
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Universal Serial Bus
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.18.4.14 USB Endpoint 0 OUT WRT CNT Register
The USB Endpoint 0 OUT WRT CNT Register, shown in Figure 1.46, contains the number of bytes of the current data set in the OUT FIFO. The USB FCU sets the value in the Write Count Register after having successfully received a packet of data from the host. The CPU reads the register to determine the number of bytes to be read from the FIFO.
USB Endpoint 0 OUT Write Count Register
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Symbol EP0WC Bit symbol
W_CNT0 to W_CNT4
Address 031516 Bit name
Receive byte count
When reset 0016 Function RW
X
Must always be set to "0"
Reserved
X
Figure 1.46: USB Endpoint 0 OUT WRT CNT 2.18.4.15 USB Endpoint x IN CSR (Control & Status Register)
The USB Endpoint x IN CSR (Control and Status Register), shown in Figure 1.47, contains control and status information of the respective IN endpoint 1-4. * INxCSR0 (IN_PKT_RDY) and INxCSR5 (TX_FIFO_NOT_EMPTY): These two bits are for IN FIFO status when in read operation (see "IN (Transmit) FIFO" operation for details). The CPU writes a "1" to the INxCSR0 bit to inform the USB FCU that a packet of data is written to the FIFO. The USB FCU updates the pointers up on this bit set. The USB FCU also updates the pointers upon a packet of data successfully sent to the host. When the pointer updates are completed, the IN FIFO status is shown on INxCSR0 and INxCSR5 bits for the CPU to read. The CPU must allow at least one wait state between writing and reading these bits for proper FIFO status. * INxCSR1 (UNDER_RUN): This bit is used in ISO mode only to indicate to the CPU that a FIFO underrun has occurred. The USB FCU sets this bit to a "1" at the beginning of an IN token if no data packet is in the FIFO. Setting this bit causes the INST12 bit of the Interrupt Status Register 2 to set. The CPU writes a "0" to clear this bit. * INxCSR2 (SEND_STALL): The CPU writes a "1" to this bit when the endpoint is stalled (transmitter halt). The USB FCU returns a STALL handshake while this bit is set. The CPU writes a "0" to clear this bit. * INxCSR3 (ISO/TOGGLE_INIT): When the endpoint is used for isochronous data transfer, the CPU sets this bit to a "1" for the entire duration of the isochronous transfer. With the ISO bit set to a "1", the device uses DATA0 as the pid for all packets sent back to the host. When the endpoint is required to initialize the data toggle, this set/reset of the TOGGLE_INIT bit method assumes that there is no activity IN transaction to the respective endpoint on the bus at the time the initialization process is ongoing. Set/reset of the TOGGLE_INIT bit is performed only when an endpoint experiences a configuration event. * INxCSR4 (INTPT): The CPU writes a "1" to this bit to initialize this endpoint as a status change endpoint for IN transactions. This bit is set only when the corresponding endpoint is to be used to communicate rate feedback information (see Chapter. IN (Transmit) FIFOs for details). * INxCSR5 (TX_FIFO_NOT_EMPTY): The USB FCU sets this bit to a "1" when there is at least one data packet in the IN FIFO. This bit, in conjunction with IN_PKT_RDY bit, provides the transmit IN FIFO status information (see "IN (Transmit) FIFO" for details). * INxCSR6 (FLUSH):
1-59
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Universal Serial Bus
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The CPU writes a "1" to this bit to flush the IN FIFO. When there is one packet in the IN FIFO, a flush causes the IN FIFO to be empty. When there are two packets in the IN FIFO, a flush causes the older packet to be flushed out from the IN FIFO. Setting the INXCSR6 (FLUSH) bit during transmission could produce unpredictable results. *INxCSR7 (AUTO_SET): When the CPU sets this bit to a "1", the IN_PKT_RDY bit is set automatically by the USB FCU after the number of bytes of data equal to the maximum packet size (MAXP) is written into the IN FIFO (see "IN (Transmit) FIFO" operation for details).
USB Endpoint x IN Control and Status Register (Note 5)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol EPiICS (i= 1-4) Bit symbol
INxCSR0 INxCSR1 INxCSR2 INxCSR3 INxCSR4 INxCSR5 INxCSR6 INxCSR7 Note Note Note Note Note
Address 031916, 032116, 032916, 033116 Bit name
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 : : : : : : : : : : : : : : : :
When reset 0016 Function RW
00
Note 1
IN_PKT_RDY Bit UNDER_RUN Flag SEND_STALL Bit ISO Bit INTPT TX_NOT_EPT Flag FLUSH Bit AUTO_SET Bit
Not ready Ready No FIFO underrun FIFO underrun has occured No action Stall IN Endpoint x by CPU Select non-isochronous transfer Select isochronous transfer Select non-rate feedback interrupt transfer Select rate feedback interrupt transfer Transmit FIFO is empty Transmit FIFO is not empty No action Flush the FIFO AUTO-SET disabled AUTO-SET enabled
00
Note 2
00 00 00 00
Note 3
00
Note 4
00
1: Write "1" only or read 2: Write "0" only or read 3: Read only 4: Write only - Read "0" 5: Refer to section 5.5 "Programming Notes" for this register
Figure 1.47: USB Endpoint x IN CSR 2.18.4.16 USB Endpoint x OUT Control and Status Register
The USB Endpoint x OUT CSR (Control and Status Register), shown in Figure 1.48 contains control and status information of the respective OUT endpoint 1-4. * OUTxCSR0 (OUT_PKT_RDY): The OUTxCSR0 bit for the OUT FIFO status (see "OUT (Receive) FIFOs" for details). The USB FCU sets this bit to a "1" and updates the FIFO pointers after a data packet has been successfully received from the host. The CPU writes a "0" to this bit to inform the USB FCU that a data packet has been unloaded. The USB FCU updates the FIFO pointers when this occurs. The CPU must allow at least one clock cycle between writing and reading bit OUTxCSR0. * OUTXxCSR1 (OVER_RUN): This bit is used in ISO mode only to indicate to the CPU that a FIFO overrun has occurred. The USB FCU sets this bit to a "1" at the beginning of an OUT token when two data packets are already present in the FIFO. Setting this bit causes the INST12 bit of the Interrupt Status Register 2 to set. The CPU writes a "0" to clear OUTXCSR1. * OUTxCSR2 (SEND_STALL): The CPU writes a "1" to this bit when the endpoint is stalled. The USB FCU returns a STALL handshake while this bit is set. The CPU writes a "0" to clear this bit. * OUTxCSR3 (ISO/TOGGLE_INIT): When the endpoint is used for isochronous data transfer, the CPU sets this bit to a "1" for the entire duration of the isochronous transfer. With the ISO/TOGGLE_INIT bit set to a "1", the device accepts either DATA0 or DATA1 for the PID sent by the host.
1-60
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Universal Serial Bus
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When endpoint is required to initialize the data toggle sequence bit (i.e. reset to DATA0 for the next data packet), the CPU sets this bit to a "1" and then resets it to a "0" to initialize the respective endpoint's data toggle. Successful initialization of the data toggle sequence bit can only be guaranteed if no active OUT transaction to the respective endpoint is ongoing when the initialization process is taking place. Set/reset of the ISO/ TOGGLE_INIT bit should only be performed when an endpoint experiences a configuration event. * OUTxCSR4 (FORCE_STALL): The USB FCU sets this bit to a "1" when the host sends out a larger data packet than the MAXP size. The USB FCU returns a STALL handshake while this bit is set. The CPU writes a "0" to clear this bit. * OUTxCSR5 (DATA_ERR): The USB FCU sets this bit to a "1" to indicate that a CRC error or a bit stuffing error was received in an ISO packet. The CPU writes a "0" to clear this bit. * OUTxCSR6 (FLUSH): The CPU writes a "1" to this to flush the OUT FIFO. When there is one packet in the OUT FIFO, a flush causes the OUT FIFO to be empty. When there are two packets in the OUT FIFO, a flush causes the older packet to be flushed out from the OUT FIFO. Setting the OUTXCSR6 (FLUSH) bit during reception could produce unpredictable results. * OUTxCSR7 (AUTO_CLR): When the CPU sets this bit to a "1", the OUT_PKT_RDY bit is cleared automatically by the USB FCU after the number of bytes of data equal to the maximum packet size (MAXP) is unloaded from the OUT FIFO (see "OUT (Receive) FIFO" for details).
USB Endpoint x OUT Control and Status Register (Note 3)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol EPiOCS (i = 1-4) Bit symbol
Address 031A16, 032216, 032A16, 033216 Bit name
0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1:
When reset 0016 Function RW
00
Note 1
OUTxCSR0 OUT_PKT_RDY Flag OUTxCSR1 OVER_RUN Flag OUTxCSR2 SEND_STALL Bit OUTxCSR3 ISO Bit OUTxCSR4 FORCE-STALL Flag OUTxCSR5 DATA-ERR Flag OUTxCSR6 FLUSH Bit OUTxCSR7 AUTO_CLR Bit
Not ready Ready No FIFO overrun FIFO overrun occured No action Stall OUT Endpoint x by CPU Select non-isochronous transfer Select isochronous transfer No action Stall Endpoint X by the USB FCU No error CRC or bit stuffing error received in ISO packet No action Flush the FIFO AUTO-CLR disabled AUTO-CLR enabled
00
Note 1
00 00 00
Note 1
00
Note 1
00
Note 2
00
Note 1: Write "0" only or read Note 2: Write only - Read "0" Note 3: Refer to section 5.5 "Programming Notes" for this register
Figure 1.48: USB Endpoint x OUT CSR 2.18.4.17 USB Endpoint x IN MAXP Register
The USB Endpoint x IN MAXP Register, shown in Figure 1.49, indicates the maximum packet size (MAXP) of an Endpoint x IN packet. The default values for Endpoints 1-4 are 0 bytes. The setting of this register also affects the configuration of single/dual packet operation. When MAXP > 1/2 of the FIFO size, single packet mode is set. When MAXP <= 1/2 of the FIFO size, dual packet mode is set.
USB Endpoint x IN MAXP Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol EPiIMP (i = 1-4) Bit symbol
IMAXP0 to IMAXP7
Address When reset 0016 031B16, 032316, 032B16, 033316 Bit name Function
For endpoints that support smaller FIFO size, unused bits are not implemented, (always write "0" to those bits).
RW
Maximum packet size (MAXP) of Endpoint x IN packet.
Figure 1.49: USB Endpoint x IN MAXP 1-61
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Universal Serial Bus
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.18.4.18 USB Endpoint x OUT MAXP Register
The USB Endpoint x OUT MAXP Register, shown in Figure 1.50, indicates the maximum packet size (MAXP) of an Endpoint x OUT packet. The default values for endpoints 1-4 are 0 bytes. The setting of this register also affects the configuration of single/dual packet operation. When MAXP > 1/2 of the FIFO size, single packet is set. When MAXP <= 1/2 of the FIFO size, dual packet mode is set.
USB Endpoint x OUT MAXP Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol EPiOMP (i = 1-4) Bit symbol
OMAXP0 to OMAXP7
Address When reset 0016 031C16, 032416, 032C16, 033416 Bit name Function
For endpoints that support smaller FIFO size, unused bits are not implemented, (always write "0" to those bits).
RW
Maximum packet size (MAXP) of Endpoint x OUT packet.
Figure 1.50: USB Endpoint x OUT MAXP 2.18.4.19 USB Endpoint x OUT WRT CNT Register
The USB Endpoint x OUT WRT CNT Register, shown in Figure 1.51, contains the number of bytes of the current data set in the OUT FIFO. The USB FCU sets the value in the Write Count Register after having successfully received a packet of data from the host. The CPU reads the register to determine the number of bytes to be read from the FIFO.
USB Endpoint x OUT Write Count Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol EPiWC (i = 1-4) Bit symbol
W_CNT0 to W_CNT7
Address When reset 0016 031D16, 032516, 032D16, 033516 Bit name Function RW
Receive Byte Count
X
Figure 1.51: USB Endpoint x OUT WRT CNT 2.18.4.20 USB Endpoint x FIFO Register
The USB Endpoint x FIFO Register, shown in Figure 1.52 is the USB IN (transmit) and OUT (receive) FIFO data register. The CPU writes data to this register for the corresponding Endpoint IN FIFO and reads data from this register for the corresponding Endpoint OUT FIFO.
USB Endpoint x FIFO Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol EPi (i = 0-4) Bit symbol
DATA_0 to DATA_7
Address 033816, 033916, 033A16, 033B16, 033C16 Bit name
Endpoint x IN/OUT FIFO register
When reset Indeterminate RW
Function
X
Figure 1.52: USB Endpoint x FIFO Register
1-62
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
DMAC 2.19 DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU.Table 1.14 shows the DMAC specifications. Figure 1.53 shows the block diagram of the DMAC. Figure 1.54, Figure 1.55 and Figure 1.56 show the registers used by the DMAC. Table 1.14: DMAC specifications Item
Number of channels 2 (cycle steal method) *From any SFR, RAM, or ROM address to a fixed address *From a fixed address to any SFR or RAM address *From a fixed address to a fixed address (Note that DMA-related registers [002016 to 003F16] cannot be accessed) 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers) Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 by DMA1) Timer A0 to timer A4 Timer B0 to timer B1 UART0 transmission and reception UART1 transmission and reception UART2 transmission and reception A-D conversion complete USB function Software triggers DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously 8 bits or 16 bits forward/fixed (forward direction cannot be specified for both source and destination simultaneously) Single transfer mode The DMA enable bit is cleared and transfer ends when an underflow occurs in the transfer counter. Repeat transfer mode When an underflow occurs in the transfer counter, the value in the transfer counter reload register is loaded into the transfer counter and the DMA transfer is repeated When an underflow occurs in the transfer counter Single transfer mode Transfer starts when the DMA is requested after "1" is written to the DMA enable bit Repeat transfer mode Transfer starts when the DMA is requested after "1" is written to the DMA enable bit or after an underflow occurs in the transfer counter When "0" is written to the DMA enable bit When, in single transfer mode, an underflow occurs in the transfer counter When DMA transfer starts, the value of whichever of the source or destination pointer that is set up as the forward pointer is loaded into the forward address pointer. The value in the transfer counter reload register is loaded into the transfer counter. Registers specified for forward direction transfer are always write-enabled. Registers specified for fixed address transfer are write-enabled when the DMA enable bit is "0". Can be read at any time. However, when the DMA enable bit is "1", reading the register sets up as the forward register is the same as reading the value of the forward address pointer.
Specification
Transfer memory space
Maximum number of bytes transferred
DMA request sources
Channel priority Transfer unit Transfer address direction
Transfer modes
DMA interrupt request generation timing
DMA startup
DMA shutdown Forward address pointer and reload timing for transfer counter
Writing to register
Reading the register
1-63
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address bus
DMA0 source pointer SAR0(20) (addresses 0022 16 to 002016) DMA0 destination pointer DAR0 (20)
(addresses 002616 to 002416)
DMA0 forward address pointer (20)
DMA0 transfer counter reload register TCR0 (16)
DMA1 source pointer SAR1 (20) (addresses 0032 16 to 003016) DMA1 destination pointer DAR1 (20)
(addresses 003616 to 003416)
(addresses 0029 16, 002816) DMA0 transfer counter TCR0 (16)
DMA1 transfer counter reload register TCR1 (16)
DMA1 forward address pointer (20)
(addresses 0039 16, 003816) DMA1 transfer counter TCR1 (16)
DMA latch high-order bits DMA latch low-order bits
Data bus low-order bits Data bus high-order bits Note: Pointer is incremented by a DMA request.
Figure 1.53: Block diagram of DMAC
DMAi request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DMiSL (i=0,1)
Address 03B816,03BA16
When reset 0016
Bit symbol
Bit name DMA request cause select bit
b3 b2 b1 b0
Function
0 0 0 0 : Falling edge of INT0 / INT1 pin (Note1) 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3 0 1 1 0 : Timer A4 0 1 1 1 : Timer B0 1 0 0 0 : Timer B1 1 0 0 1 : USB0/USB1 (Note 3) 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 transmit / UART1 receive (Note 2)
R
W
DSEL0
DSEL1
DSEL2
DSEL3
Nothing is assigned. These bits can neither be set nor reset. When read, the value of these bits is "0".
DSR
Software DMA request bit
If software trigger is selected, a DMA request is generated by setting this bit to "1" (When read, the value of this bit is always "0")
Note 1: Address 03B8 16 is for INT0, 03BA 16 is for INT1. Note 2: Address 03B8 16 is for UART1 transmit, 03BA 16 is for UART1 receive. Note 3: Address 03B8 16 is for USB0, 03BA 16 is for USB1.
Figure 1.54: DMAC register (1)
1-64
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAi control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DMiCON(i=0,1)
Address 002C16, 003C16
When reset 00000X002
Bit symbol DMBIT DMASL DMAS DMAE DSD DAD
Bit name Transfer unit bit select bit Repeat transfer mode select bit DMA request bit (Note 1) DMA enable bit Source address direction select bit (Note 3) 0 : 16 bits 1 : 8 bits
Function
R
W
0 : Single transfer 1 : Repeat transfer 0 : DMA not requested 1 : DMA requested 0 : Disabled 1 : Enabled 0 : Fixed 1 : Forward
(Note 2)
Destination address 0 : Fixed direction select bit (Note 3) 1 : Forward
Nothing is assigned. These bits can neither be set nor reset. When read, the value of these bits is "0".
Note 1: DMA request can be cleared by resetting the bit. Note 2: This bit can only be set to "0". Note 3: Source address direction select bit and destination address direction select bit cannot be set to "1" simultaneously.
Figure 1.55: DMAC register (2)
DMAi source pointer (i = 0, 1)
(b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0
Symbol SAR0 SAR1
Address 002216 to 002016 003216 to 003016 Transfer count specification
When reset Indeterminate Indeterminate
Function Source pointer Stores the source address
RW
0000016 to FFFFF16
Nothing is assigned. These bits can neither be set nor reset. When read, the value of these bits is "0".
DMAi destination pointer (i = 0, 1)
(b23) b7 (b19) b3 (b16) (b15) b0 b7 (b8) b0 b7 b0
Symbol DAR0 DAR1
Address 002616 to 002416 003616 to 003416 Transfer count specification
When reset Indeterminate Indeterminate
Function Destination pointer Stores the destination address
RW
0000016 to FFFFF16
Nothing is assigned. These bits can neither be set nor reset. When read, the value of these bits is "0".
DMAi transfer counter (i = 0, 1)
(b15) b7 (b8) b0 b7 b0
Symbol TCR0 TCR1
Address 002916, 002816 003916, 003816
When reset Indeterminate Indeterminate RW
Function Transfer counter Set a value one less than the transfer count
Transfer count specification 000016 to FFFF16
Figure 1.56: DMAC register (3) 1-65
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
DMAC
2.19.1 Transfer cycle
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle in which the data is written to memory or to the SFR area (destination write). The number of read and write bus cycles depends on the source and destination addresses and the software waits are inserted. 2.19.1.1 Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there is one more source read cycle and destination write cycle than when the source and destination both start at even addresses.
2.19.2 DMAC transfer cycles Any combination of even or odd transfer read and write addresses is possible. Table 1.15 show the number of DMAC transfer cycles. Table 1.16 shows the corresponding coefficient values. Figure 1.57 shows an example of the transfer cycle for a source read. The number of DMAC transfer cycles can be calculated as follows:
Number of transfer cycles per transfer unit = Number of read cycles x j + Number of write cycles x k
Table 1.15:
Number of DMAC transfer cycles Single-chip mode Access address
Even Odd Even Odd
Transfer unit
Number of read cycles
1 1 1 2
Number of write cycles
1 1 1 2
8-bit transfers (DMBIT="1") 16-bit transfers (DMBIT="0")
Table 1.16:
Coefficients j,k Internal memory
Internal ROM/ RAM No wait
1
Internal ROM/ RAM with wait
2
SFR area
2
1-66
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) 8-bit transfers 16-bit transfers from even address and the source address is even.
CLKout Address bus
CPU use Source Destination Dummy cycle CPU use
Data bus
CPU use
Source
Destination
Dummy cycle
CPU use
(2) 16-bit transfers and the source address is odd Transferring 16-bit data on an 8-bit data bus (In this case, there are two destination write cycles).
CLKout Address bus
CPU use Source Source + 1 Destination Dummy cycle CPU use
Data bus
CPU use
Source
Source + 1 Destination
Dummy cycle
CPU use
(3) One wait is inserted into the source read under the conditions in (1)
CLKout Address bus RD signal WR signal Data bus
CPU use Source Destination Dummy cycle CPU use CPU use Source Destination Dummy cycle CPU use
(4) One wait is inserted into the source read under the conditions in (2) (When 16-bit data is transferred on an 8-bit data bus, there are two destination write cycles).
CLKout Address bus RD signal WR signal Data bus
CPU use Source Source + 1 Destination Dummy cycle CPU use CPU use Source Source + 1 Destination Dummy cycle CPU use
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 1.57: Example of the transfer cycle for a source read 1-67
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Timers 2.20 Timers
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
There are eight 16-bit timers. These timers can be classified by function into timers A (five) and timers B (three). All these timers function independently. Figure 1.58 shows the block diagram of Timers A and B.
XIN 1/8 f1 f8 f32 1/4
f1 f8 f32
* Timer mode * One-shot mode * PWM mode
TA0IN
Noise filter
Timer A0
* Event counter mode * Timer mode * One-shot mode * PWM mode
Timer A0 interrupt
TA1IN
Noise filter
Timer A1
* Event counter mode * Timer mode * One-shot mode * PWM mode
Timer A1 interrupt
TA2IN
Noise filter
Timer A2
* Event counter mode * Timer mode * One-shot mode * PWM mode
Timer A2 interrupt
TA3IN
Noise filter
Timer A3
* Event counter mode * Timer mode * One-shot mode * PWM mode
Timer A3 interrupt
TA4IN
Noise filter
Timer A4
* Event counter mode * Timer mode
Timer A4 interrupt
Timer B0 Timer B0 interrupt
* Timer mode
Timer B1 Timer B1 interrupt
* Timer mode
Timer B2 Timer B2 interrupt
Figure 1.58: Timer A and Timer B block diagram
1-68
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Timer A 2.21 Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.59, Figure 1.60,Figure 1.61, and Figure 1.62 show the timer A-related registers. Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. Timer A has the four operation modes listed as follows: * Timer mode: The timer counts an internal count source. * Event counter mode: The timer counts pulses from an external source or a timer over flow. * One-shot timer mode: The timer stops counting when the count reaches "000016". * Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Data bus high-order bits
Clock source selection
f1 f8 f32
* Timer * One shot * PWM * Timer (gate function) * Event counter
Data bus low-order bits Low-order 8 bits Reload register (16) High-order 8 bits
Polarity selection
TAiIN (i = 0 to 4)
Counter (16) Clock selection
Up count/down count Always down count except in event counter mode
Count start flag
(Address 038016) Down count External trigger
TB2 overflow TAj overflow
(j = i - 1. Note, however, that j = 4 when i = 0)
Up/down flag
(Address 038416)
TAi Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Addresses 038716 038616 038916 038816 038B16 038A16 038D16 038C16 038F16 038E16 TAj Timer A4 Timer A0 Timer A1 Timer A2 Timer A3 TAk Timer A1 Timer A2 Timer A3 Timer A4 Timer A0
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
TAiOUT
(i = 0 to 4)
Pulse output
Toggle flip-flop
Figure 1.59: Block diagram of Timer A
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1
Address When reset 039616 to 039A16 0016 Bit name
b1 b0
Function 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode
RW
Operation mode select bit
Function varies with each operation mode
Count source select bit Function varies with each operation mode
Figure 1.60: Timer A related Registers (1) 1-69
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai register (Note)
(b15) b7 (b8) b0 b7 b0
Symbol TA0 TA1 TA2 TA3 TA4
Address 038716,038616 038916,038816 038B16,038A16 038D16,038C16 038F16,038E16
When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate
Function Timer mode Counts an internal count source Event counter mode Counts pulses from an external source or timer overflow One-shot timer mode Counts a one shot width Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator
Values that can be set
RW
000016 to FFFF16 000016 to FFFF16
000016 to FFFF16
000016 to FFFE16 0016 to FE16 (Both high-order and low-order addresses)
Note: Read and write data in 16-bit units.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR
Address 038016
When reset 0016
Bit symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S
Bit name Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag
Function 0 : Stops counting 1 : Starts counting
RW
Up/down flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UDF
Address 038416
When reset 0016
Bit symbol TA0UD TA1UD TA2UD TA3UD TA4UD TA2P TA3P TA4P
Bit name Timer A0 up/down flag Timer A1 up/down flag Timer A2 up/down flag Timer A3 up/down flag Timer A4 up/down flag Timer A2 two-phase pulse signal processing select bit Timer A3 two-phase pulse signal processing select bit Timer A4 two-phase pulse signal processing select bit
Function 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled When not using the two-phase pulse signal processing function, set the select bit to "0"
RW
Figure 1.61: Timer A-related registers (2)
1-70
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
One-shot start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ONSF
Address 038216
When reset 00X000002
Bit symbol
TA0OS TA1OS TA2OS TA3OS TA4OS
Bit name Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag
Function 1 : Timer start When read, the value is 0
RW
Nothing is assigned. This bit can neither be set nor reset. When read, its content is indeterminate. TA0TGL TA0TGH
Timer A0 event/trigger select bit
b7 b6
0 0 : Input on TA0IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA4 overflow is selected 1 1 : TA1 overflow is selected
Note: Set the corresponding port direction register to 0 .
Trigger select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRGSR
Address 038316
When reset 0016
Bit symbol
TA1TGL
Bit name Timer A1 event/trigger select bit
Function
b1 b0
RW
TA1TGH TA2TGL
0 0 : Input on TA1IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected
b3 b2
Timer A2 event/trigger select bit
TA2TGH TA3TGL TA3TGH
0 0 : Input on TA2IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected
b5 b4
Timer A3 event/trigger select bit
0 0 : Input on TA3IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected
b7 b6
TA4TGL TA4TGH
Timer A4 event/trigger select bit
0 0 : Input on TA4IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to 0 .
Figure 1.62: Timer A-related registers (3)
1-71
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Timer A
2.21.1 Timer mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In this mode, the timer counts an internally generated count source. See Table 1.17 below. Figure 1.63 shows the timer Ai mode register in timer mode. Table 1.17: Item
Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer f1, f8, f32 * Down count * When the timer underflows, it loads the reload register contents before continuing counting 1/(n+1) n: Set value Count start flag is set (= 1) Count start flag is reset (= 0) When the timer underflows Programmable I/O port or gate input Programmable I/O port or pulse output Count value can be read out by reading timer Ai register * When counting is stopped and a value is written to timer Ai register, it is written to both reload register and counter * When counting is in progress and a value is written to timer Ai register, it is written only to reload register (to be transferred to counter at the next reload time) * Gate function Counting can be started and stopped by TAiIN pin's input signal * Pulse output function Each time the timer underflows, the TAiOUT pin's polarity is reversed
Specifications of timer mode Specification
Select function
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 MR0
Address When reset 0016 039616 to 039A16 Bit name Function
b1 b0
RW
Operation mode select bit Pulse output function select bit
0 0 : Timer mode 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin)
b4 b3
MR1
Gate function select bit
0 X (Note 2): Gate function not available
(TAiIN pin is a normal port pin)
MR2
1 0 : Timer counts only when TA iIN pin is held "L" (Note 3) 1 1 : Timer counts only when TA iIN pin is held "H" (Note 3) 0 (Must always be fixed to "0" in timer mode) Count source select bit
b7 b6
MR3 TCK0 TCK1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : Reserved
Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: The bit can be "0" or "1". Note 3: Set the corresponding port direction register to "0".
Figure 1.63: Timer Ai mode register in timer mode 1-72
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Timer A
2.21.2 Event counter mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In this mode, the timer counts an external signal or an internal timer's overflow. Timers A0 and A1 can count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase external signal. Table 1.18 lists the timer specifications when counting a single-phase external signal. Figure 1.64 shows Timer Ai mode register in event counter mode, single-phase signal. Table 1.18: Item
Count source
Timer specification in event counter mode (when not processing two-phase pulse signal) Specification
*External signals input to TAiIN pin (effective edge can be selected by software *TB2 overflow, TAj overflow *Up count or down count can be selected by external signal or software *When the timer overflows or underflows, it loads from the reload register contents before continuing counting. (However, this does not apply when the free-run function is selected.) 1/ (FFFF16 - n+1) for up count 1/ (n + 1) for down count n: set value Count start flag is set (=1) Count start flag is reset (=0) Timer overflows or underflows Programmable I/O port or count source input Programmable I/O port, pulse output, or up/down count select input Count value can be read out by reading timer Ai register *When counting is stopped and a value is written to timer Ai register, it is written to both reload register and counter *When counting is in progress and a value is written to timer Ai register, it is written to only reload register *Free-run count function When the timer overflows or underflows, the reload register content is not reloaded. *Pulse output function Each time the timer overflows, the TAiOUT pin`s polarity is reversed
Count operation
Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer
Write to timer
Select function
1-73
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
01
Symbol TAiMR(i = 0, 1) Bit symbol TMOD0 TMOD1 MR0
Address 039616, 039716
When reset 0016 Function RW RW
Bit name Operation mode select bit Pulse output function select bit
b1 b0
0 1 : Event counter mode (Note 1) 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 2) (TAiOUT pin is a pulse output pin) 0 : Counts external signal's falling edge 1 : Counts external signal's rising edge 0 : Up/down flag's content 1 : TAiOUT pin's input signal (Note 4)
MR1 MR2 MR3 TCK0 TCK1
Count polarity select bit (Note 3) Up/down switching cause select bit
0 (Must always be fixed to "0" in event counter mode) Count operation type select bit 0 : Reload type 1 : Free-run type (Note 5)
Invalid in event counter mode Can be "0" or "1"
Note 1: In event counter mode, the count source is selected by the event / trigger select bit (addresses 0382 16 and 038316). Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Valid only when counting an external signal. Note 4: When an "L" signal is input to the TAi OUT pin, the downcount is activated. When "H", the upcount is activated. Set the corresponding port direction register to "0". Note 5: This value can be indeterminate when the count starts.
Figure 1.64: Timer Ai mode register in event counter mode, single signal Table 1.19 shows the Timer specification in event counter mode when processing two-phase signal with timers A2, A3, and A4. Figure 1.65 shows Timer Ai mode register in event counter mode when processing two-phase signal.
1-74
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Timer A
Table 1.19:
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer specification in even counter mode (when processing two-phase pulse signal with timers A2, A3, and A4)
Item Count Source Count operation Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Writer to timer
Specification *Two-phase pulse signals input to TAiIN or TAiOUT pin *Up count or down count can be selected by two-phase pulse signal *When the timer overflows or underflows, the reload register content is loaded and the timer starts over again (Note 1) 1/ (FFFF16 - n + 1) for up count 1/ (n+1) for down count Count start flag is set (=1) Count start flag is reset (=0) Timer overflow or underflows Two-phase pulse input Two-phase pulse input Count value can be read out by reading timer A2, A3, or A4 register *When counting is stopped and a value is written to timer A2, A3, or A4 register, it is written to both the reload register and counter *When counting is in progress and a value is written to timer A2, A3, or A4 register, it is written to only reload register to be transferred to counter at the next reload time. *Normal processing operation The timer counts up rising edges or counts down falling edges on the TAiIN pin when input signal on the TAiOUT pin is "H" TAiOUT n: Set value
TAiIN
(i=2,3)
Up count Up count Up count Down count Down count Down count
Select function
*Multiply-by-4 processing operation If the phase relationship is such that the TAiIN pin goes "H" when the input signal on the TAiOUT pin is "H", the timer counts up rising and falling edges on the TAiOUT and TAiIN pins. If the phase relationship is such that the TAiIN pin goes "L" when the input signal on the TAiOUT pin is "H", the timer counts down rising and falling edges on the TAiOUT and TAiIN pins.
TAiOUT
Count up all edges Count down all edges
TAiIN (i=3,4) Count up all edges Count down all edges
Note 1
This does not apply when the free-run function is selected.
1-75
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai mode register (When not using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
0
01
Symbol Address When reset 0016 TAiMR(i = 2 to 4) 039816 to 039A16
Bit symbol
TMOD0 TMOD1 MR0
Bit name
Operation mode select bit Pulse output function select bit
b1 b0
Function
0 1 : Event counter mode 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin) 0 : Counts external signal's falling edges 1 : Counts external signal's rising edges 0 : Up/down flag's content 1 : TAiOUT pin's input signal (Note 3)
RW
MR1 MR2 MR3 TCK0 TCK1
Count polarity select bit (Note 2) Up/down switching cause select bit
0 : (Must always be "0" in event counter mode) Count operation type select bit Two-phase pulse signal processing operation select bit (Note 4)(Note 5) 0 : Reload type 1 : Free-run type (Note 6) 0 : Normal processing operation 1 : Multiply-by-4 processing operation
Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: This bit is valid when only counting an external signal. Note 3: Set the corresponding port direction register to "0". Note 4: This bit is valid for the timer A3 mode register. For timer A2 and A4 mode registers, this bit can be "0 "or "1". Note 5: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 0384 16) is set to "1". Also, always be sure to set the event/trigger select bit (addresses 0382 16 and 038316) to "00". Note 6: This value can be indeterminate when the count starts.
Timer Ai mode register (When using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
010001
Symbol Address When reset 0016 TAiMR(i = 2 to 4) 039816 to 039A16
Bit symbol
TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1
Bit name
Operation mode select bit
b1 b0
Function
0 1 : Event counter mode
RW
0 (Must always be "0" when using two-phase pulse signal processing) 0 (Must always be "0" when using two-phase pulse signal processing) 1 (Must always be "1" when using two-phase pulse signal processing) 0 (Must always be "0" when using two-phase pulse signal processing) Count operation type select bit Two-phase pulse processing operation select bit (Note 1)(Note 2) 0 : Reload type 1 : Free-run type (Note 3) 0 : Normal processing operation 1 : Multiply-by-4 processing operation
Note 1: This bit is valid for timer A3 mode register. For timer A2 and A4 mode registers, this bit can be "0" or "1". Note 2: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 0384 16) is set to "1". Also, always be sure to set the event/trigger select bit (addresses 0382 16 and 038316) to "00". Note 3: This value can be indeterminate when the count starts.
Figure 1.65: Timer Ai mode register in event counter mode, two-phase signal 1-76
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Timer A
2.21.3 One-shot timer mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In this mode, the timer operates only once (See Table 1.20 ). When a trigger occurs, the timer starts up and continues operating for a given period. Figure 1.66 shows the timer Ai mode register in oneshot mode. Table 1.20: Item
Count source Count operation Divide ratio Count start condition f1, f8, f32 *The timer counts down *When the count reaches 000016, the timer stops counting after reloading a new count * If a trigger occurs when counting, the timer reloads a new count and restarts counting 1/n n: Set value
Timer specifications in one-shot timer mode Specification
* An external trigger is input * The selected timer overflows * The one-shot start flag is set (= 1) * A new count is reloaded after the count has reached 000016 * The count start flag is reset (= 0) The count reaches 000016 Programmable I/O port or trigger input Programmable I/O port or pulse output When timer Ai register is read, it indicates an indeterminate value *When counting is stopped and a value is written to timer Ai register, it is written to both reload register and counter *When counting is in progress and a value is written to timer Ai register, it is written to the reload register to be transferred to counter at next load time
Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer
Write to timer
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
10
Symbol Address When reset TAiMR(i = 0 to 4) 039616 to 039A16 0016 Bit symbol TMOD0 TMOD1 MR0 Pulse output function select bit Bit name Operation mode select bit
b1 b0
Function 1 0 : One-shot timer mode 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin)
0 : Falling edge of TAiIN pin's input signal (Note 3) 1 : Rising edge of TAiIN pin's input signal (Note 3)
RW
MR1 MR2
External trigger select bit (Note 2) Trigger select bit
0 : One-shot start flag is valid 1 : Selected by event/trigger select register
MR3 TCK0 TCK1
0 (Must always be "0" in one-shot timer mode) Count source select bit
b7 b6
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : invalid
Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: Valid only when the TA iIN pin is selected by the event/trigger select bit (addresses 038216 and 038316). If timer overflow is selected, this bit can be "1" or "0". Note 3: Set the corresponding port direction register to "0".
Figure 1.66: Timer Ai mode register in one-shot mode
1-77
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Timer A
2.21.4 Pulse-width modulation (PWM) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In this mode, the timer outputs pulses of a given width in succession (See Table 1.21 ). In this mode, the counter functions as either a 16-bit pulse-width modulator or an 8-bit pulse-width modulator. Figure 1.67 shows the timer Ai mode register in pulse-width modulation mode.Figure 1.68 shows the example of how a 16-bit pulse-width modulator operates. Figure 1.69 shows the example of how an 8-bit pulse width modulator operates. Table 1.21: Item
Count source Count operation f1, f8, f32 *The timer counts down (operating as an 8-bit or a 16-bit pulse-width modulator) *The timer reloads a new count at a rising edge of PWM pulse and continues counting * The timer is not affected by a trigger that occurs when counting *High level width n / fi *Cycle time (216-1) / fi n: Set value fixed n: values set to timer Ai register's high-order address m: values set to timer Ai register's low-order address
Timer specifications in pulse-width modulation mode Specification
16-bit PWM 8-bit PWM
Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer
*High level width n (m+1) /fi *Cycle time (28-1) (m+1) /fi *External trigger is input *The timer overflows *The count start flag is set (= 1) *The count start flag is reset (= 0) PWM pulse goes "L"
Programmable I/O port or trigger input Pulse output When timer Ai register is read, it indicates an indeterminate value *When counting is stopped and a value is written to timer Ai register, it is written to both reload register and the counter *When counting in progress and a value is written to timer A register, it is written to only reload register to be transferred to the counter at next reload timer.
Write to timer
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
111
Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 MR0 MR1
Address When reset 039616 to 039A16 0016 Bit name Function
b1 b0
RW
Operation mode select bit
1 1 : PWM mode
Must always be "1" in PWM mode) External trigger select bit (Note 1) 0 : Falling edge of TAi IN pin's input signal (Note 2) 1 : Rising edge of TAi IN pin's input signal (Note 2) 0 : Count strat flig is valid 1 : Selected by event /trigger select register
MR2 MR3 TCK0 TCK1
Trigger select bit
16/8 PWM mode select bit 0 : Functions as a 16-bit pulse width modulator 1 : Functions as an 8-bit pulse width modulator
b7 b6
Count source select bit
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : Reserved
Note 1: Valid only when the TAi IN pin is selected by the event/trigger select bit. (addresses 0382 16 and 038316). If timer overflow is selected, this bit can be "1", or "0". Note 2: Set the corresponding port direction register to "0".
Figure 1.67: Timer Ai mode register in pulse-width modulation mode 1-78
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Condition : Reload register = 000316, when external trigger (rising edge of TAiIN pin input signal) is selected
1 / fi X (2 16 - 1)
Count source
TAiIN pin input signal
"H" "L"
Trigger is not generated by this signal 1 / fi X n
PWM pulse output from TAiOUT pin Timer Ai interrupt request bit
"H" "L" "1" "0"
fi : Frequency of count source (f1, f8, f32) Cleared to "0" when interrupt request is accepted, or cleared by software
Note: n = 000016 to FFFE16.
Figure 1.68: Example of how a 16-bit pulse-width modulator operates
Condition : Reload register high-order 8 bits = 0216 Reload register low-order 8 bits = 0216 External trigger (falling edge of TAiIN pin input signal) is selected
1 / fi X (m + 1) X (2 - 1) Count source (Note1)
8
TAiIN pin input signal
"H" "L"
1 / fi X (m + 1)
"H" Underflow signal of 8-bit prescaler (Note2) "L"
1 / fi X (m + 1) X n PWM pulse output from TAiOUT pin Timer Ai interrupt request bit
"H" "L" "1" "0"
fi : Frequency of count source (f1, f8, f32)
Cleared to "0" when interrupt request is accepted, or cleared by software
Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 0016 to FE16; n = 0016 to FE16.
Figure 1.69: Example of how an 8-bit pulse-width modulator operates 1-79
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Timer B 2.22 Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.70 shows the block diagram of timer B. Figure 1.71 and Figure 1.72 show the timer B-related registers. Use the timer Bi mode register (i = 0 to 2) bits 0 and 1 to choose the desired mode. Timer B works in Timer mode only (i.e., the timer counts an in internal count source).
Data bus high-order bits Data bus low-order bits Low-order 8 bits High-order 8 bits
Clock source selection
f1 f8 f32
Reload register (16)
Counter (16) Count start flag (address 038016) Counter reset circuit
TBj overflow (j=i - 1. Note, however, j = 2 when i = 0)
TBi Timer B0 Timer B1 Timer B2
Address 039116 039016 039316 039216 039516 039416
TBj Timer B2 Timer B0 Timer B1
Figure 1.70: Block diagram of Timer B
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol TBiMR(i=0 to 2)
Address 039B16 to 039D16
When reset 00XX00002
Bit symbol TMOD0 TMOD1 MR0 MR1 MR2
Bit name
Operation mode select bit
b1 b0
Function
0 0 : Timer mode
R
W
Invalid in timer mode Can be "0" or "1" 0 (Fixed to "0" in timer mode ; i = 0)
Nothing is assiigned (i = 1, 2).
This bit can neither be set nor reset. When read, its content is indeterminate. (Note 2) (Note 1)
MR3
Invalid in timer mode. This bit can neither be set nor reset. When read in timer mode, its content is indeterminate. Count source select bit
b7 b6
TCK0 TCK1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : Reserved
Note 1: Timer B0. Note 2: Timer B1, Timer B2.
Figure 1.71: Timer B-related registers
1-80
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Bi register (Note)
(b15) b7 (b8) b0 b7 b0
Symbol TB0 TB1 TB2 TB3 TB4 TB5
Address 039116, 039016 039316, 039216 039516, 039416 035116, 035016 035316, 035216 035516, 035416
When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate
Values that can be set
Function
* Timer mode Counts the timer's period
RW
000016 to FFFF16
Note: Read and write data in 16-bit units.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR
Address 038016
When reset 0016
Bit symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S
Bit name
Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag
Function
0 : Stops counting 1 : Starts counting
RW
Figure 1.72: Timer B-related registers 2.22.1 Timer mode In this mode, the timer counts an internally generated count source. (See Table 1.22 ) Figure 1.73 shows the Timer Bi mode register in timer mode. Table 1.22: Item
Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request generation timing f1, f8, f32 *Counts down *When the timer underflows, it reloads the reload register contents before continuing counting 1/(n+1) n: Set value
Timer specifications in timer mode Specification
Count start flag is set (= 1) Count start flag is reset (= 0) The timer underflows (see Note)
Note: Timer B2 does not generate an interrupt; it is used only as a prescaler.
1-81
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol TBiMR(i=0 to 2)
Address 039B16 to 039D16
When reset 00XX00002
Bit symbol TMOD0 TMOD1 MR0 MR1 MR2
Bit name
b1 b0
Function
0 0 : Timer mode
R
W
Operation mode select bit Invalid in timer mode Can be "0" or "1"
0 (Fixed to "0" in timer mode ; i = 0)
Nothing is assiigned (i = 1, 2). In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate.
(Note 1) (Note 2)
MR3
Invalid in timer mode. In an attempt to write to this bit, write "0". The value, if read in timer mode, turns out to be indeterminate.
b7 b6
TCK0 Count source select bit TCK1 Note 1: Timer B0. Note 2: Timer B1, Timer B2.
0 0 1 1
0 1 0 1
: : : :
f1 f8 f32 Reserved
Figure 1.73: Timer Bi mode register in timer mode
1-82
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2 2.23 UART0 through UART2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O is configured as three channels: UART0, UART1, and UART2. UART0, UART1, and UART2 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 1.74 shows the block diagram of UART0, UART1, and UART2.
(UART0)
RxD0
UART reception
TxD0
1/16
Clock source selection
f1 f8 f32 Bit rate generator Internal (address 03A116)
Clock synchronous type
1/16
Reception control circuit
Receive clock
Transmit/ receive unit
1 / (n0+1)
External
UART transmission
Clock synchronous type
Transmission control circuit
Transmit clock
Clock synchronous type
1/2
(when internal clock is selected)
Clock synchronous type (when internal clock is selected)
CLK0
CLK polarity reversing circuit CTS/RTS disabled CTS/RTS selected
Clock synchronous type (when external clock is selected)
CTS0 / RTS0
VCC CTS/RTS disabled
RTS0
CTS0
(UART1)
RxD1
Clock source selection
f1 f8 f32 Bit rate generator Internal (address 03A916)
1/16
TxD1
UART reception Reception control circuit Receive clock Transmit/ receive unit
Clock synchronous type UART transmission
1/16
1 / (n1+1)
External
Clock synchronous type Clock synchronous type
1/2 (when internal clock is selected)
Transmission control circuit
Transmit clock
CLK1 CTS1 / RTS1 CLKS1
CLK polarity reversing circuit
Clock synchronous type (when internal clock is selected)
Clock synchronous type (when external clock is selected)
CTS/RTS disabled
RTS1
Clock output pin select switch VCC CTS/RTS disabled
CTS1
(UART2)
RxD2
RxD polarity reversing circuit
1/16
UART reception
Clock source selection f1 f8 f32 Internal Bit rate generator (address 037916)
Clock synchronous type UART transmission
1/16
Reception control circuit
Receive clock
TxD polarity reversing circuit Transmit/ receive unit
TxD2
1 / (n2+1)
External
Clock synchronous type Clock synchronous type
1/2
Transmission control circuit
Transmit clock
(when internal clock is selected)
CLK2
CLK polarity reversing circuit
Clock synchronous type (when internal clock is selected)
Clock synchronous type (when external clock is selected)
CTS/RTS selected
CTS/RTS disabled
CTS2 / RTS2
Vcc CTS/RTS disabled
RTS2
CTS2
n0 : Values set to UART0 bit rate generator (BRG0) n1 : Values set to UART1 bit rate generator (BRG1) n2 : Values set to UART2 bit rate generator (BRG2)
Figure 1.74: Block diagram of UARTi (i=0 to 2)
1-83
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.75 and Figure 1.76 show the block diagram of the transmit/receive unit.
Clock synchronous type UART (7 bits) UART (8 bits)
1SP
PAR disabled
Clock synchronous type
UART (7 bits)
UARTi receive register
RxDi
SP 2SP
SP
PAR
PAR enabled
UART
UART (9 bits)
Clock synchronous type UART (8 bits) UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UARTi receive buffer register Address 03A616 Address 03A716 Address 03AE16 Address 03AF16
MSB/LSB conversion circuit
Data bus high-order bits Data bus low-order bits
MSB/LSB conversion circuit
D8
D7
D6
D5
D4
D3
D2
D1
D0
UARTi transmit buffer register Address 03A216 Address 03A316 Address 03AA16 Address 03AB16
UART (8 bits) UART (9 bits)
UART (9 bits)
Clock synchronous type
2SP SP SP 1SP
PAR
PAR enabled
UART
TxDi
PAR disabled Clock synchronous type
UART (7 bits)
UART (7 bits) UART (8 bits) Clock synchronous type
UARTi transmit register
"0"
SP: Stop bit PAR: Parity bit
Figure 1.75: Block diagram of UARTi (i=0,1) transmit/receive circuit
No reverse
RxD2
RxD data reverse circuit
Reverse
Clock synchronous type
1SP SP 2SP SP
PAR
PAR disabled
Clock synchronous type
UART (7 bits) UART (8 bits)
UART(7 bits)
UART2 receive register
PAR enabled
UART
UART (9 bits)
Clock synchronous type
UART (8 bits) UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UART2 receive buffer register Address 037E16 Address 037F16
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D8
D7
D6
D5
D4
D3
D2
D1
D0
UART2 transmit buffer register Address 037A16 Address 037B16
UART (8 bits) UART (9 bits)
PAR enabled
UART (9 bits) UART
Clock synchronous type
2SP SP SP 1SP
PAR
PAR disabled
Clock synchronous type
"0"
UART (7 bits) UART (8 bits)
Clock synchronous type
UART(7 bits)
UART2 transmit register
Error signal output disable
No reverse
Error signal output circuit
Error signal output enable Reverse
TxD data reverse circuit
TxD2
SP: Stop bit PAR: Parity bit
Figure 1.76: Block diagram of UART2 transmit/receive circuit 1-84
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 03A016, 03A816 and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a UART. Although a few functions are different, UART0 and UART1 have almost the same functions. UART0 through UART2 are almost equal in their functions with minor exceptions.Table 1.23 shows the comparison of functions of UART0 through UART2, and Figure 1.77, Figure 1.78, Figure 1.79, Figure 1.80, and Figure 1.81 show the registers related to UARTi. Table 1.23: Comparison of functions of UART0 through UART2 Function
CLK polarity selection LSB first / MSB first selection Continuous receive mode selection Transfer clock output from multiple pins selection Serial data logic switch Sleep mode selection TxD, RxD I/O polarity switch TxD, RxD port output format Parity error signal output Bus collision detection Note 1: Note 2: Note 3: Note 4:
UART0
Possible (Note 1) Possible (Note 1) Possible (Note 1) Impossible Impossible Possible (Note 3) Impossible CMOS output Impossible Impossible
UART1
Possible (Note 1) Possible (Note 1) Possible (Note 1) Possible (Note 1) Impossible Possible (Note 3) Impossible CMOS output Impossible Impossible
UART2
Possible (Note 1) Possible (Note 2) Possible (Note 1) Impossible Possible (Note 4) Impossible Possible CMOS output Possible (Note 4) Possible
Only during clock synchronous serial I/O mode. Only during clock synchronous serial I/O mode and 8-bit UART mode. Only during UART mode. Used for SIM interface.
1-85
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit buffer register
(b15) b7 (b8) b0 b7 b0
Symbol U0TB U1TB U2TB
Address 03A316, 03A216 03AB16, 03AA16 037B16, 037A16
When reset Indeterminate Indeterminate Indeterminate Function RW
Transmit data Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate.
UARTi receive buffer register
(b15) b7 (b8) b0 b7 b0
Symbol U0RB U1RB U2RB
Address 03A716, 03A616 03AF16, 03AE16 037F16, 037E16
When reset Indeterminate Indeterminate Indeterminate
Bit symbol
Bit name
Function (During clock synchronous serial I/O mode) Receive data
Function (During UART mode) Receive data
RW
Nothing is assigned. These bits can neither be set nor reset. When read, the value of these bits is "0". OER FER PER SUM Overrun error flag (Note 1) 0 : No overrun error 1 : Overrun error found Framing error flag (Note 1) Invalid Parity error flag (Note 1) Error sum flag (Note 1) Invalid Invalid 0 : No overrun error 1 : Overrun error found 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found
Note 1: Bits 15 through 12 are set to "0" when the serial I/O mode select bit (bits 2 to 0 at addresses 03A0 16, 03A816 and 037816) are set to "0002" or the receive enable bit is set to "0". (Bit 15 is set to "0" when bits 14 to 12 all are set to "0".) Bits 14 and 13 are also set to "0" when the lower byte of the UARTi receive buffer register (addresses 03A6 16, 03AE16 and 037E16) is read out.
UARTi bit rate generator
b7 b0
Symbol U0BRG U1BRG U2BRG
Address 03A116 03A916 037916 Function
When reset Indeterminate Indeterminate Indeterminate Values that can be set 0016 to FF16 RW
Assuming that set value = n, BRGi divides the count source by n+1
Figure 1.77: Serial I/O-related registers (1)
1-86
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiMR(i=0,1)
Address 03A016, 03A816
When reset 0016
Bit symbol SMD0 SMD1 SMD2
Bit name
Function (During clock synchronous serial I/O mode) Must be fixed to 001
b2 b1 b0
Function (During UART mode)
b2 b1 b0
RW
Serial I/O mode select bit
0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited
1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited 0 : Internal clock 1 : External clock 0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected
CKDIR Internal/external clock select bit STPS PRY Stop bit length select bit Odd/even parity select bit
0 : Internal clock 1 : External clock Invalid Invalid
PRYE SLEP
Parity enable bit Sleep select bit
Invalid Must always be "0"
UART2 transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2MR
Address 037816
When reset 0016
Bit symbol SMD0 SMD1 SMD2
Bit name
Function (During clock synchronous serial I/O mode) Must be fixed to 001
b2 b1 b0
Function (During UART mode)
b2 b1 b0
RW
Serial I/O mode select bit
0 0 0 : Serial I/O invalid 0 1 1 : Inhibited 1 1 1 : Inhibited
1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 1 : Inhibited 1 1 1 : Inhibited 0 : Internal clock 1 : External clock 0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse Usually set to "0"
CKDIR Internal/external clock select bit STPS PRY Stop bit length select bit Odd/even parity select bit
0 : Internal clock 1 : External clock Invalid Invalid
PRYE IOPOL
Parity enable bit TxD, RxD I/O polarity reverse bit
Invalid 0 : No reverse 1 : Reverse Usually set to "0"
Figure 1.78: Serial I/O-related registers (2)
1-87
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiC0(i=0,1)
Address When reset 03A416, 03AC16 0816 Function (During clock synchronous serial I/O mode)
b1 b0 b1 b0
Bit symbol CLK0 CLK1 CRS
Bit name BRG count source select bit
Function (During UART mode) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Reserved
Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port)
RW
0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Reserved
Valid when bit 4 = "0"
0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2)
CTS/RTS function select bit Transmit register empty flag
TXEPT
0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port)
CRD
CTS/RTS disable bit
Nothing is assigned. This bit can neither be set nor reset. When read, the value of this bit is "0".
CKPOL CLK polarity select bit
0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge
Must always be "0"
UFORM Transfer format select bit 0 : LSB first 1 : MSB first
Must always be "0"
Note 1: Set the corresponding port direction register to "0". Note 2: The settings of the corresponding port register and port direction register are invalid.
UART2 transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2C0
Address 037C16
When reset 0816 Function (During clock synchronous serial I/O mode)
Bit symbol CLK0 CLK1 CRS
Bit name BRG count source select bit
Function (During UART mode)
b1 b0
RW
b1 b0
0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited
Valid when bit 4 = "0"
0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2)
0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited
Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port)
CTS/RTS function select bit Transmit register empty flag
TXEPT
0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port)
CRD
CTS/RTS disable bit
0 : TXDi pin is CMOS output 0: TXDi pin is CMOS output Nothing is assigned. 1: This bit can neither be set nor reset.TXDi pin read, the value of 1: TXDi pin "0". When is N-channel this bit is is N-channel open-drain output open-drain output
CKPOL
CLK polarity select bit
0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge
Must always be "0"
UFORM Transfer format select bit 0 : LSB first (Note 3) 1 : MSB first
0 : LSB first 1 : MSB first
Note 1: Set the corresponding port direction register to "0". Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
Figure 1.79: Serial I/O-related registers (3) 1-88
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiC1(i=0,1)
Address 03A516,03AD16
When reset 0216
Bit symbol TE TI
Bit name Transmit enable bit Transmit buffer empty flag
Function (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register
Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register
RW
RE RI
Receive enable bit Receive complete flag
Nothing is assigned. These bits can neither be set nor reset. When read, the value of these bits is "0".
UART2 transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2C1
Address 037D16
When reset 0216
Bit symbol TE TI
Bit name Transmit enable bit Transmit buffer empty flag
Function (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled 0 : No reverse 1 : Reverse Must be fixed to "0"
Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) Invalid
RW
RE RI
Receive enable bit Receive complete flag
U2IRS UART2 transmit interrupt cause select bit
U2RRM UART2 continuous receive mode enable bit
U2LCH Data logic select bit U2ERE Error signal output enable bit
0 : No reverse 1 : Reverse 0 : Output disabled 1 : Output enabled
Figure 1.80: Serial I/O-related registers (4) 1-89
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UCON
Address 03B016
When reset X00000002
Bit symbol U0IRS
Bit name UART0 transmit interrupt cause select bit UART1 transmit interrupt cause select bit
Function (During clock synchronous serial I/O mode)
0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed
(TXEPT = 1)
Function (During UART mode)
0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1)
RW
U1IRS
0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed
(TXEPT = 1)
U0RRM UART0 continuous receive mode enable bit
0 : Continuous receive mode disabled 1 : Continuous receive mode enable 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Valid when bit 5 = "1" 0 : Clock output to CLK1 1 : Clock output to CLKS1 0 : Normal mode
(CLK output is CLK1 only)
Invalid
U1RRM UART1 continuous receive mode enable bit
Invalid
CLKMD0 CLK/CLKS select bit 0
Invalid
CLKMD1 CLK/CLKS select bit 1 (Note)
Must always be "0"
1 : Transfer clock output from multiple pins function selected Reserved Must always be "0" Must always be "0"
Nothing is assigned. This bit can neither be set nor reset. When read, its content is indeterminate. Note: When using multiple pins to output the transfer clock, the following requirements must be met: * UART1 internal/external clock select bit (bit 3 at address 03A8 16) = "0".
Figure 1.81: Serial I/O-related registers (5)
1-90
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2
2.23.1 Clock synchronous serial I/O mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 1.24 and Table 1.25 list the specifications of the clock synchronous serial I/O mode. Figure 1.82 shows the UARTi transmit/receive mode register. Table 1.24: Specifications of clock synchronous serial I/O mode (1) Specification
* Transfer data length: 8 bits * When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = "0"): fi=2(n+1) (Note 1) fi = f1, f8, f32 * When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = "1"): Input from CLKi pin (Note 2) * CTS function/RTS function/CTS, RTS function chosen to be invalid * To start transmission, the following requirements must be met: _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = "1" _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = "0" _ When CTS function selected, CTS input level = "L" * Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "0": CLKi input level = "H" _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "1": CLKi input level = "L" * To start reception, the following requirements must be met: _ Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = "1" _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = "1" _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = "0" * Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "0": CLKi input level = "H" _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "1": CLKi input level = "L" * When transmitting _ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at address 037D16) = "0": Interrupts requested when data transfer from UARTi _ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at address 037D16) = "1": Interrupts requested when data transmission from * Overrun error (Note 3) This error occurs when the next data is ready before contents of UARTi receive buffer is read.
Item
Transfer data format
Transfer clock
Transmission/reception control
Transmission start condition
Reception start condition
Error detection
Note 1: "n" denotes the value 0016 to FF16 that is set to the UART bit rate generator. Note 2: Maximum 5 Mbps. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit is not set to "1".
1-91
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.25: Item
Specifications of clock synchronous serial I/O mode (2) Specification
* CLK polarity selection Whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected * LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected * Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register * Transfer clock output from multiple pins selection (UART1) UART1 transfer clock can be chosen by software to be output from one of the two pins set * Switching serial data logic (UART2) Whether to reverse data in writing to the transmission buffer register or reading the reception buffer register can be selected. * Switching serial data logic (UART2) This function is reversing TxD port output and RxD port input. All I/O data level is reversed.
Select function
UARTi transmit/receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
0
001
Symbol UiMR(i=0,1) Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE SLEP
Address 03A016, 03A816 Bit name
When reset 0016 Function
b2 b1 b0
RW
Serial I/O mode select bit
0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock 1 : External clock
Internal/external clock select bit
Invalid in clock synchronous serial I/O mode 0 (Must always be "0" in clock synchronous serial I/O mode)
UART2 transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
001
Symbol U2MR Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE IOPOL
Address 037816 Bit name
When reset 0016 Function
b2 b1 b0
RW
Serial I/O mode select bit
0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock 1 : External clock
Internal/external clock select bit
Invalid in clock synchronous serial I/O mode TxD, RxD I/O polarity reverse bit (Note) 0 : No reverse 1 : Reverse
Note: Usually set to "0".
Figure 1.82: UARTi transmit/receive mode register in clock synchronous serial I/O mode
1-92
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.26 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table shows the pin functions when the transfer clock output from multiple pins function is not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxD pin outputs a "H". The typical clock synchronous timing diagrams are shown in Figure 1.83. Table 1.26: Pin name
TxDi (P63, P67, P70) RxDi (P62, P66, P71)
Input/output pin functions in clock synchronous serial I/O mode Function
Serial data output Serial data input Transfer clock output
Method of selection
(Outputs dummy data when performing reception only) Port P62, P66, and P71 direction register (bits 2 and 6 at address 03EE16 bit 1 at address 03EF16)= "0" (Can be used as an input port when performing transmission only.) Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = "0" Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = "1" Port P61, P65, and P72 direction register (bits 1 and 5 at address 03EE16, bit 2 at address 03EF16) = "0" CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = "0" Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16, bit 3 at address 03EF16) = "0" CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = "1" CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "1"
CLKi (P61, P65, P72)
Transfer clock input
CTS input CTSi/RTSi (P60,P64,P73) RTS output Programmable I/O port
1-93
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Tc
Transfer clock
"1" "0" "1" "0" Transferred from UARTi transmit buffer register to UARTi transmit register "H" Data is set in UARTi transmit buffer register
Transmit enable bit (TE) Transmit buffer empty flag (Tl) CTSi
"L"
TCLK
Stopped pulsing because CTS = "H"
Stopped pulsing because transfer enable bit = "0"
CLKi
TxDi Transmit register empty flag (TXEPT) Transmit interrupt request bit (IR)
"1" "0" "1" "0"
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: * Internal clock is selected. * CTS function is selected. * CLK polarity select bit = "0". * Transmit interrupt cause select bit = "0". Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f 1, f8, f32) n: value set to BRGi
Example of receive timing (when external clock is selected)
Receive enable bit (RE) Transmit enable bit (TE) Transmit buffer empty flag (Tl) RTSi
"1" "0" "1" "0" "1" "0" "H" "L"
Dummy data is set in UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register
1 / fEXT
Receive data is taken in
CLKi
RxDi Receive complete "0" flag (Rl) Receive interrupt request bit (IR)
"1" "0" "1"
D0 D1 D2 D3 D4 D5 D6 D7
Transferred from UARTi receive register to UARTi receive buffer register
D0 D1 D2 D3 D4 D5
Read out from UARTi receive buffer register
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: * External clock is selected. * RTS function is selected. * CLK polarity select bit = "0". fEXT: frequency of external clock Meet the following conditions are met when the CLK input before data reception = "H" * Transmit enable bit "1" * Receive enable bit "1" * Dummy data write to UARTi transmit buffer register
Figure 1.83: Typical transmit/receive timings in clock synchronous serial I/O mode Polarity select function
1-94
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2
2.23.1.1 Polarity select function
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
As shown in Figure 1.84, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) allows selection of the polarity of the transfer clock.
* When CLK polarity select bit = "0"
CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Note 1: The CLK pin level when not transferring data is "H".
* When CLK polarity select bit = "1"
CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Note 2: The CLK pin level when not transferring data is "L".
Figure 1.84: Polarity of transfer clock 2.23.1.2 LSB first/MSB first select function
As shown in Figure 1.85, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16, 037C16) = "0", the transfer format is "LSB first"; when the bit = "1", the transfer format is "MSB first".
* When transfer format select bit = "0"
CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7
LSB first
D7
* When transfer format select bit = "1"
CLKi TXDi RXDi D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0
MSB first
D0
Note: This applies when the CLK polarity select bit = "0".
Figure 1.85: Transfer format 1-95
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.23.1.3 Transfer clock output from multiple pins function (UART1)
This function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). See Figure 1.86. The multiple pins function is valid only when the internal clock is selected for UART1. Note that when this function is selected, UART1 CTS/RTS function cannot be used.
Microcomputer
TXD1 (P67)
CLKS1 (P64) CLK1 (P65) IN CLK IN CLK
Note: This applies when the internal clock is selected and transmission is performed only in clock synchronous serial I/O mode. Figure 1.86: The transfer clock output from the multiple pins function usage 2.23.1.4 Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 037D16) is set to "1", the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again.
2.23.1.5 Serial data logic switch function (UART2)
When the data logic select bit (bit6 at address 037D16) = "1", and writing to transmit buffer register or reading from receive buffer register, data is reversed. Figure 1.87 shows the example of serial data logic switch timing.
*When LSB first
Transfer clock TxD2
"H" "L" "H"
(no reverse) "L"
D0
D1
D2
D3
D4
D5
D6
D7
TxD2
"H"
(reverse) "L"
D0
D1
D2
D3
D4
D5
D6
D7
Figure 1.87: Serial data logic switch timing
1-96
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.23.2 Clock asynchronous serial I/O (UART) mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Table 1.27 and Table 1.28 list the specifications of the UART mode. Figure 1.88 shows the UARTi transmit/receive mode register. Table 1.27: Specifications of UART Mode (1) Specification
* Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected * Start bit: 1 bit * Parity bit: Odd, even, or nothing as selected * Stop bit: 1 bit or 2 bits as selected * When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = "0"): fi/16(n+1) (Note 1) fi = f1, f8, f32 * When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816 ="1"): fEXT/16(n+1)(Note 1) (Note 2) * CTS function/RTS function/CTS, RTS function chosen to be invalid * To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = "1" - Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = "0" - When CTS function selected, CTS input level = "L" * To start reception, the following requirements must be met: - Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = "1" - Start bit detection * When transmitting - Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at address 037D16) = "0": Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed - Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at address 037D16) = "1": Interrupts requested when data transmission from UARTi transfer register is completed * When receiving - Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed * Overrun error (Note 3) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out * Framing error This error occurs when the number of stop bits set is not detected * Parity error This error occurs when if parity is enabled, the number of 1's in parity and character bits does not match the number of 1's set * Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Item
Transfer data format
Transfer clock
Transmission/reception control
Transmission start condition
Reception start condition
Interrupt request generation timing
Error detection
Note 1: `n' denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: fEXT is input from the CLKi pin. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit is not set to "1"
1-97
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.28: Item
Specifications of UART Mode (2) Specification
* Sleep mode selection (UART0, UART1) This mode is used to transfer data to and from one of multiple slave micro-computers *Serial data logic switch (UART2) This function is reversing logic value of transferring data. Start bit, parity bit and stop bit are not reversed. *TxD, RxD I/O polarity switch This function is reversing TxD port output and RxD port input. All I/O data level is reversed.
Select function
UARTi transmit / receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiMR(i=0,1)
Address 03A016, 03A816
When reset 0016
Bit symbol
SMD0 SMD1 SMD2 CKDIR STPS PRY
Bit name
Serial I/O mode select bit
b2 b1 b0
Function
1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 : Internal clock 1 : External clock 0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected
RW
Internal / external clock select bit Stop bit length select bit Odd / even parity select bit Parity enable bit Sleep select bit
PRYE SLEP
UART2 transmit / receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2MR
Address 037816
When reset 0016
Bit symbol
SMD0 SMD1 SMD2 CKDIR STPS PRY
Bit name
Serial I/O mode select bit
b2 b1 b0
Function
1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 : Internal clock 1 : External clock 0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse
RW
Internal / external clock select bit Stop bit length select bit Odd / even parity select bit Parity enable bit TxD, RxD I/O polarity reverse bit (Note)
PRYE IOPOL
Note: Usually set to "0".
Figure 1.88: UARTi transmit/receive mode register in UART mode
1-98
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.29 lists the functions of the input/output pins during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a "H". Table 1.29: Pin name
TxDi (P63, P67, P70) RxDi (P62, P66, P71)
Input/output pin functions in UART mode Function
Serial data output Serial data input Programmable I/O port Port P62, P66, and P71 direction register (bits 2 and 6 at address 03EE16 bit 1 at address 03EF16)= "0" (Can be used as an input port when performing transmission only.) Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = "0" Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = "1" Port P61, P65, and P72 direction register (bits 1 and 5 at address 03EE16, bit 2 at address 03EF16) = "0" CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = "0" Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16, bit 3 at address 03EF16) = "0" CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = "1" CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "1"
Method of selection
CLKi (P61, P65, P72)
Transfer clock input
CTS input CTSi/RTSi (P60,P64,P73) RTS output Programmable I/O port
Figure 1.89 and Figure 1.90 show the typical UART mode transmit and receive timing diagrams.
1-99
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
* Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTS is "H" when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTS changes to "L".
Tc
Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI)
"1" "0" "1" "0"
Data is set in UARTi transmit buffer register.
Transferred from UARTi transmit buffer register to UARTi transmit register
"H"
CTSi
"L"
Start bit TxDi
"1" Transmit register empty flag (TXEPT) "0" "1" "0"
Parity bit
P
Stop bit
SP
Stopped pulsing because transmit enable bit = "0"
ST D0 D1
ST D0 D1 D2 D3 D4 D5 D6 D7
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
Transmit interrupt request bit (IR)
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * CTS function is selected. * Transmit interrupt cause select bit = "1". Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi
* Example of receive timing when transfer data is 8 bits long (parity enabled, one stop bit)
Tc
Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI)
"1" "0" "1" "0"
Data is set in UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register Start bit TxDi
"1" Transmit register empty flag (TXEPT) "0" "1" "0"
Stop bit
Stop bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP ST D0 D1
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
Transmit interrupt request bit (IR)
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is disabled. * Two stop bits. * CTS function is disabled. * Transmit interrupt cause select bit = "0". Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi
Figure 1.89: Typical transmit timings in UART mode 1-100
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
BRGi count source Receive enable bit RxDi "1" "0" Start bit Sampled "L" Receive data taken in Transfer clock Receive complete flag RTSi Receive interrupt request bit Reception triggered when transfer clock "1" is generated by falling edge of start bit "0" "H" "L" "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software The above timing applies to the following settings : *Parity is disabled. *One stop bit. *RTS function is selected. Transferred from UARTi receive register to UARTi receive buffer register Stop bit
D0
D1
D7
Figure 1.90: Typical receive timing in UART mode 2.23.2.1 Sleep mode (UART0, UART1)
This mode is used to transfer data between specific microcomputers among multiple microcomputers connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 03A016, 03A816) is set to "1" during reception. In this mode, the unit performs receive operation when the MSB of the received data = "1" and does not perform receive operation when the MSB = "0".
2.23.2.2 Function for switching serial data logic (UART2)
When the data logic select bit (bit 6 of address 037D16) is assigned 1, data is inverted in writing to the transmission buffer register or reading the reception buffer register. Figure 1.91 shows the example of timing for switching serial data logic.
* When LSB first, parity enabled, one stop bit
Transfer clock TxD2
(no reverse)
"H" "L" "H" "L" "H" "L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
TxD2
(reverse)
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST : Start bit P : Even parity SP : Stop bit
Figure 1.91: Timing for switching serial data logic
1-101
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.23.2.3 TxD, RxD I/O polarity reverse function (UART2)
This function is to reverse TxD pin output and RxD pin input. The level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. Set this function to "0" (not to reverse) for usual use.
2.23.2.4 Bus collision detection function (UART2)
This function is to sample the output level of the TxD pin and the input level of the RxD pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.92 shows the example of detection timing of a buss collision (in UART mode).
Transfer clock
"H" "L"
TxD2
"H" "L"
ST
SP
RxD2 Bus collision detection interrupt request signal Bus collision detection interrupt request bit
"H" "L" "1" "0" "1" "0"
ST
SP
ST : Start bit SP : Stop bit
Figure 1.92: Detection timing of a bus collision (in UART mode)
1-102
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.23.3 Clock-asynchronous serial I/O mode (compliant with the SIM interface) The SIM interface is used for connecting the microcomputer with a memory card I/C or the like; adding some extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table 1.30 shows the specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface). Figure 1.93 shows the typical transmit/receive timing in UART mode. Table 1.30: Item Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface) Specification
* Transfer data 8-bit UART mode (bit 2 through bit 0 of address 037816 = "1012") * One stop bit (bit 4 of address 037816 = "0") * With the direct format chosen Set parity to "even" (bit 5 and bit 6 of address 037816 = "1" and "1" respectively) Set data logic to "direct" (bit 6 of address 037D16 = "0"). Set transfer format to LSB (bit 7 of address 037C16 = "0"). * With the inverse format chosen Set parity to "odd" (bit 5 and bit 6 of address 037816 = "0" and "1" respectively) Set data logic to "inverse" (bit 6 of address 037D16 = "1") Set transfer format to MSB (bit 7 of address 037C16 = "1") * With the internal clock chosen (bit 3 of address 037816 = "0"): fi / 16 (n + 1) (Note 1): fi=f1, f8, f32 * With an external clock chosen (bit 3 of address 037816 = "1"): fEXT / 16 (n+1) (Note 1) (Note 2) * Disable the CTS and RTS function (bit 4 of address 037C16 = "1") * The sleep mode select function is not available for UART2 * Set transmission interrupt factor to "transmission completed" (bit 4 of address 037D16 = "1") * To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 of address 037D16) = "1" - Transmit buffer empty flag (bit 1 of address 037D16) = "0" * To start reception, the following requirements must be met: - Reception enable bit (bit 2 of address 037D16) = "1" - Detection of a start bit * When transmitting When data transmission from the UART2 transfer register is completed (bit 4 of address 037D16 = "1") * When receiving When data transfer from the UART2 receive register to the UART2 receive buffer register is completed * Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 3) * Framing error (see the specifications of clock-asynchronous serial I/O) * Parity error (see the specifications of clock-asynchronous serial I/O) - On the reception side, an "L" level is output from the TxD2 pin by use of the parity error signal output function (bit 7 of address 037D16 = "1") when a parity error is detected - On the transmission side, a parity error is detected by the level of input to the RxD2 pin when a transmission interrupt occurs * The error sum flag (see the specifications of clock-asynchronous serial I/O)
Transfer data format
Transfer clock Transmission / reception control Other settings
Transmission start condition
Reception start condition
Error detection
Note 1: `n' denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: fEXT is input from the CLK2 pin. Note 3: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit is not set to "1".
1-103
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Tc
Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI)
"1" "0" "1" "0" Data is set in UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register Start bit Parity bit
P
Stop bit
SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
TxD2 RxD2
ST D0 D1 D2 D3 D4 D5 D6 D7
A "L" level returns from TxD2 due to the occurrence of a parity error.
Signal conductor level (Note 1)
"1" Transmit register empty flag (TXEPT) "0" "1" "0"
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5 D6 D7 The level is detected by the interrupt routine.
P
SP The level is detected by the interrupt routine.
Transmit interrupt request bit (IR)
Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = "1".
Cleared to "0" when interrupt request is accepted, or cleared by software Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi
Tc
Transfer clock Receive enable bit (RE)
"1" "0"
Start bit
Parity bit
P
Stop bit
SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
TxD2 RxD2
ST D0 D1 D2 D3 D4 D5 D6 D7
A "L" level returns from TxD2 due to the occurrence of a parity error.
Signal conductor level (Note 1) Receive complete flag (RI) Receive interrupt request bit (IR)
"1" "0" "1" "0"
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
Read to receive buffer
Read to receive buffer
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = "0". Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi
Note: Equal in waveform because TxD2 and RxD2 are connected.
Figure 1.93: Typical transmit/receive timing in UART mode (compliant with the SIM interface) 1-104
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
UART0 through UART2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.23.3.1 Function for outputting a parity error signal
With the error signal output enable bit (bit 7 of address 037D16) assigned "1", you can output an "L" level from the TxD2 pin when a parity error is detected. In step with this function, the generation timing of a transmission completion interrupt changes to the detection timing of a parity error signal. Figure 1.94 shows the output timing of the parity error signal.
* LSB first
Transfer clock RxD2 TxD2 Receive complete flag
"H" "L" "H" "L" "H" "L" "1" "0"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
Hi-Z
ST : Start bit P : Even Parity SP : Stop bit
Figure 1.94: Output timing of the parity error signal 2.23.3.2 Direct format/inverse format
Connecting the SIM card allows you to switch between direct format and inverse format. If you choose the direct format, D0 data is output from TxD2. If you choose the inverse format, D7 data is inverted and output from TxD2. Figure 1.95 shows the SIM interface format.
Transfer clcck TxD2 (direct) TxD2 (inverse) D0 D1 D2 D3 D4 D5 D6 D7 P
D7
D6
D5
D4
D3
D2
D1
D0
P P : Even parity
Figure 1.95: SIM interface format
Figure 1.96 shows the example of connecting the SIM interface with TxD2 and RxD2.
Microcomputer
SIM card TxD2 RxD2
Figure 1.96: Connecting the SIM interface 1-105
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
A-D Converter 2.24 A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P100 to P107 function as the analog signal input pins. The direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF. The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Table 1.31 shows the performance of the A-D converter. Figure 1.97 shows the block diagram of the AD converter, and Figure 1.98 and Figure 1.99 show the A-D converter-related registers. Table 1.31: Performance of A-D Converter Item
Method of A-D conversion Analog input voltage (Note) Operating clock fAD Resolution 0V to AVCC (VCC) VCC = 5V fAD/divide-by-2 or fAD/divide-by-4 or fAD, fAD=f(Xin)
Performance
Successive approximation (capacitive coupling amplifier)
8-bit or 10-bit (selectable) * Without sample and hold function 3LSB * With sample and hold function (8-bit resolution) 2LSB * With sample and hold function (10-bit resolution) 3LSB
Absolute precision
VCC = 5V
Operating modes Analog input pins
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 8pins (AN0 to AN7) *Software trigger A-D conversion starts when the A-D conversion start flag changes to "1" *External trigger (can be retriggered) A-D conversion starts when the A-D conversion start flag is "1" and the ADTRG/P87 input changes from "H" to "L" *Without sample and hold function 8-bit resolution: 49 AD cycles, 10-bit resolution: 59 AD cycles * With sample and hold function 8-bit resolution: 28 AD cycles, 10-bit resolution: 33 AD cycles
A-D conversion start condition
Conversion speed per pin
Note Does not depend on use of sample and hold function.
1-106
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CKS1=1
fAD
1/2 1/2
CKS0=1 CKS1=0
AD
A-D conversion rate selection
CKS0=0
VREF
VCUT=0
Resistor ladder
AVSS
VCUT=1
Successive conversion register A-D control register 1 (address 03D7 16)
A-D control register 0 (address 03D6 16)
Addresses
(03C116, 03C016) (03C316, 03C216) (03C516, 03C416) (03C716, 03C616) (03C916, 03C816) (03CB16, 03CA16) (03CD16, 03CC16) (03CF16, 03CE16)
A-D register 0(16) A-D register 1(16) A-D register 2(16) A-D register 3(16) A-D register 4(16) A-D register 5(16) A-D register 6(16) A-D register 7(16) VIN Comparator Vref Decoder
Data bus high-order Data bus low-order
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
CH2,CH1,CH0=000 CH2,CH1,CH0=001 CH2,CH1,CH0=010 CH2,CH1,CH0=011 CH2,CH1,CH0=100 CH2,CH1,CH0=101 CH2,CH1,CH0=110 CH2,CH1,CH0=111
Figure 1.97: Block diagram of A-D converter
1-107
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ADCON0 Bit symbol
CH0
Address 03D616 Bit name
When reset 00000XXX2 Function
b2 b1 b0
RW
Analog input pin select bit
CH1
CH2 MD0 MD1 TRG ADST CKS0 Trigger select bit A-D conversion start flag Frequency select bit 0 A-D operation mode select bit 0
0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected
b4 b3
(Note 2)
0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
(Note 2)
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
When reset 0016 Function
When single sweep and repeat sweep mode 0 are selected
b1 b0
RW
A-D sweep pin select bit
0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) SCAN1 When repeat sweep mode 1 is selected
b1 b0
0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) MD2 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 0 : Vref not connected 1 : Vref connected
BITS CKS1 VCUT
Reserved bit
Always set to "0"
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Figure 1.98: A-D converter-related registers (1)
1-108
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D control register 2 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
When reset
XXXXXXX02
000
Bit symbol
SMP Reserved bit
Bit name
A-D conversion method select bit
Function
0 : Without sample and hold 1 : With sample and hold Always set to "0"
RW
Nothing is assigned. These bits can neither be set nor reset. When read, their content is "0". Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D register i
(b15) b7 (b8) b0 b7
Symbol
ADi(i=0 to 7)
Address When reset 03C016 to 03CF16 Indeterminate
b0
Function
Eight low-order bits of A-D conversion result * During 10-bit mode Two high-order bits of A-D conversion result * During 8-bit mode When read, the content is indeterminate Nothing is assigned. These bits can neither be set nor reset. When read, their content is "0".
RW
(JA 03 UM60)
Figure 1.99: A-D converter-related registers (2)
1-109
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
A-D Converter
2.24.1 One-shot mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conversion.Table 1.32 shows the specifications of one-shot mode. Figure 1.100 shows the A-D control register in one-shot mode. Table 1.32: One-shot mode specification Item
Function Start condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter
Specification
The pin selected by the analog input pin select bit is used for one A-D conversion Writing "1" to A-D conversion start flag *End of A-D conversion (A-D conversion start flag changes to "0", except when external trigger is selected) *Writing "0" to A-D conversion start flag End of A-D conversion One of AN0 to AN7, as selected Read A-D register corresponding to selected pin
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol ADCON0 Bit symbol
CH0
Address 03D616 Bit name
When reset 00000XXX2 Function
b2 b1 b0
RW
Analog input pin select bit
CH1
CH2 MD0 MD1 TRG ADST CKS0 A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
: : : : : : : :
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
is selected is selected is selected is selected is selected is selected is selected is selected
(Note 2) (Note 2)
b4 b3
0 0 : One-shot mode 0 1 0 1 : : : : Software trigger ADTRG trigger A-D conversion disabled A-D conversion started
0: fAD/4 is selected 1: fAD/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
001
0
Symbol ADCON1 Bit symbol
SCAN0 SCAN1 MD2 BITS CKS1 VCUT
Address 03D716 Bit name
When reset 0016 Function
Invalid in one-shot mode
RW
A-D sweep pin select bit
A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit1 Vref connect bit
0 : Any mode other than repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected
Reserved bit
Always set to "0"
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Figure 1.100: A-D conversion register in one-shot mode 1-110
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
A-D Converter
2.24.2 Repeat mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion. Table 1.33 shows the specifications of repeat mode. Figure 1.101 shows the A-D control register in repeat mode. Table 1.33: Repeat sweep mode 0 specifications Item
Function Star condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter
Specification
The pin selected by the analog input pin select bit is used for repeated A-D conversion
Writing "1" to A-D conversion start flag Writing "0" to A-D conversion start flag None generated One of AN0 to AN7, as selected Read A-D register corresponding to selected pin
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
01
Symbol ADCON0 Bit symbol
CH0 CH1
Address 03D616 Bit name
When reset 00000XXX 2 Function
b2 b1 b0
RW
Analog input pin select bit
CH2 MD0 MD1 TRG ADST CKS0 A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0
0 0 0 : AN0 0 0 1 : AN1 0 1 0 : AN2 0 1 1 : AN3 1 0 0 : AN4 1 0 1 : AN5 1 1 0 : AN6 1 1 1 : AN7
b4 b3
is selected is selected is selected is selected is selected is selected is selected is selected
(Note 2) (Note 2)
0 1 : Repeat mode 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
001
0
Symbol ADCON1 Bit symbol
SCAN0 SCAN1 MD2 BITS CKS1 VCUT
Address 03D716 Bit name
A-D sweep pin select bit
When reset 0016 Function
Invalid in repeat mode RW
A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit
0 : Any mode other than repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected
Reserved bit
Always set to "0"
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Figure 1.101: A-D conversion register in repeat mode 1-111
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
A-D Converter
2.24.3 Single sweep mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D conversion. Table 1.34 shows the specifications of single sweep mode. Figure 1.102 shows the A-D control register in single sweep mode. Table 1.34: Item
Function Start condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter Writing "1" to A-D converter start flag *End of A-D conversion (A-D conversion start flag changes to "0", except when external trigger is selected) *Writing "0" to A-D conversion start flag End of A-D conversion AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Read A-D register corresponding to selected pin
Single sweep mode specification Specification
The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
10
Symbol ADCON0 Bit symbol
CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0
Address 03D616 Bit name
When reset 00000XXX2 Function
Invalid in single sweep mode
RW
Analog input pin select bit
A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0
b4 b3
1 0 : Single sweep mode
0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
00
1
0
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
A-D sweep pin select bit
When reset 0016 Function
When single sweep and repeat sweep mode 0 are selected
b1 b0
RW
SCAN1 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit
0 0 1 1
0 1 0 1
: : : :
AN0, AN1 (2 pins) AN0 to AN3 (4 pins) AN0 to AN5 (6 pins) AN0 to AN7 (8 pins)
MD2 BITS CKS1 VCUT
0 : Any mode other than repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected
Reserved bit
Always set to "0"
Note : If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Figure 1.102: A-D conversion register in single sweep mode 1-112
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
A-D Converter
2.24.4 Repeat sweep mode 0
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep A-D conversion. Table 1.35 shows the specifications of repeat sweep mode 0. Figure 1.103 shows the A-D control register in repeat sweep mode 0. Table 1.35: Repeat sweep mode 0 specifications Item
Function Start condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter
Specification
The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion Writing "1" to A-D conversion start flag Writing "0" to A-D conversion start flag None generated AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Read A-D register corresponding to selected pin (at any time)
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
11
Symbol ADCON0 Bit symbol
CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0
Address 03D616 Bit name
When reset 00000XXX2 Function
Invalid in repeat sweep mode 0
RW
Analog input pin select bit
A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0
b4 b3
1 1 : Repeat sweep mode 0
0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
001
0
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
A-D sweep pin select bit
When reset 0016 Function
When single sweep and repeat sweep mode 0 are selected
b1 b0
RW
SCAN1 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit
0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) 0 : Any mode other than repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected
MD2 BITS CKS1 VCUT
Reserved bit
Always set to "0"
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Figure 1.103: A-D conversion register in repeat sweep mode 0 1-113
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
A-D Converter
2.24.5 Repeat sweep mode 1
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using the A-D sweep pin select bit. Table 1.36 shows the specifications of repeat sweep mode 1. Figure 1.104 show the A-D control in repeat sweep mode 1. Table 1.36: Repeat sweep mode 1 specification Item
Function Start condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter
Specification
All pins perform repeat sweep A-D conversion, with emphasis on the pin or pins selected by the A-D sweep pin select bit Example: AN0 selected AN0 AN1 AN0 AN2 AN0 AN3, etc. Writing "1" to A-D conversion start flag Writing "0" to A-D conversion start flag None generated AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins) Read A-D register corresponding to selected pin (at any time)
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
11
Symbol ADCON0 Bit symbol
CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0
Address 03D616 Bit name
When reset 00000XXX2 Function
Invalid in repeat sweep mode 1
RW
Analog input pin select bit
A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0
b4 b3
1 1 : Repeat sweep mode 1
0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
001
1
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
A-D sweep pin select bit
When reset 0016 Function
When repeat sweep mode 1 is selected
b1 b0
RW
SCAN1 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit
0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) 1 : Repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected
MD2 BITS CKS1 VCUT
Reserved bit
Always set to "0 "
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Figure 1.104: A-D conversion register in repeat sweep mode 1 1-114
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
A-D Converter
2.24.6 Sample and hold
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to "1". When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 AD cycle is achieved with 8-bit resolution and 33 AD with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and hold is to be used.
1-115
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
CRC Calculation Circuit 2.25 CRC Calculation Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcomputer uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code. The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC code is set in a CRC data register each time one byte of data is transferred to a CRC input register after writing an initial value into the CRC data register. Generation of CRC code for one byte of data is completed in two machine cycles. Figure 1.105 shows the block diagram of the CRC circuit. Figure 1.106 shows the CRC-related registers.
Data bus high-order bits Data bus low-order bits
Eight low-order bits CRC data register (16)
Eight high-order bits
(Addresses 03BD16, 03BC16) CRC code generating circuit x16 + x12 + x5 + 1
CRC input register (8)
(Address 03BE16)
Figure 1.105:
Block diagram of CRC circuit
CRC data register
(b15) b7 (b8) b0 b7 b0
Symbol CRCD
Address 03BD16, 03BC16
When reset Indeterminate Values that can be set
000016 to FFFF16
Function
CRC calculation result output register
RW
CRC input register
b7 b0
Symbo CRCIN Function
Data input register
Address 03BE16
When reset Indeterminate Values that can be set
0016 to FF16
RW
Figure 1.106: CRC-related registers
1-116
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Programmable I/O Ports 2.26 Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
There are 63 programmable I/O ports: P0 to P3, P6 to P8 (excluding P85), and P10. Each port can be set independently for input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P85 is an input-only port and has no built-in pull-up resistance. Figure 1.107, Figure 1.108 and Figure 1.109 show the programmable I/O ports. Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices. To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. When the pins are used as the outputs for the built-in peripheral devices, they function as outputs regardless of the contents of the direction registers. Unused I/O pins can be terminated as shown in Figure 1.114 and Table 1.37 . 2.26.1 Direction registers Figure 1.110 shows the direction registers. These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin. Note: There is no direction register bit for P85. 2.26.2 Port registers Figure 1.111 shows the port registers. These registers are used to write and read data for input and output to and from an external device. A port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit in port registers corresponds one for one to each I/O pin. 2.26.3 Pull-up control registers Figure 1.112 shows the pull-up control registers.The pull-up control register can be set to apply a pullup resistance to each block of 4 ports. When ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. 2.26.4 High drive capacity registers Figure 1.113 shows the Port 2 and PWM drive capacity register. Port 2 can be configured to drive an LED by increasing the drive strength of the corresponding bit's N-channel transistor. Each Timer output (TA0OUT~TA4OUT) can be configured for high-drive capability by increasing the drive strength of the corresponding bits.
1-117
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pull-up selection Direction register
P30 to P36
Data bus
Port latch
Pull-up selection Direction register
P20 to P27
Data bus
Port latch
Drive capacity control register
Pull-up selection Direction register "1" P70, P72, P74, P76, P80 Data bus output Port latch
Input to respective peripheral functions Drive capacity control register
Pull-up selection Direction register P00 to P07 P10 to P17 P62, P66, P71, P73,P75, P77, P81, P82, P84, P87
Data bus
Port latch
Input to respective peripheral functions
Figure 1.107: Programmable I/O ports (1) 1-118
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pull-up selection Direction register "1" P37 P63, P67 P86 Data bus Port latch output
Pull-up selection P60, P61, P64, P65 Data bus Direction register "1" Port latch output
Input to respective peripheral functions
P85
Data bus NMI interrupt input
Pull-up selection P100 to P107 Direction register
Data bus
Port latch
Analog input
Figure 1.108: Programmable I/O ports (2)
1-119
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BYTE
BYTE Input
CNVss
CNVss Input
RESET
RESET Input
Note: Do not apply a voltage higher than Vcc to each port
Figure 1.109: Programmable I/O Ports (3)
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PDi (i = 0 to 3,6,7,10) Bit symbol
PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7
Address 03E216, 03E316, 03E616, 03E716, 03EE16, 03EF16, 03F616 Function
0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) (i = 0 to 3,6,7,10)
When reset 0016 RW
Bit name
Port Pi0 direction register Port Pi1 direction register Port Pi2 direction register Port Pi3 direction register Port Pi4 direction register Port Pi5 direction register Port Pi6 direction register Port Pi7 direction register
Port P8 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD8
Address 03F216 Bit name
Port P80 direction register Port P81 direction register Port P82 direction register Port P83 direction register Port P84 direction register
When reset 00X000002 Function
0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port)
Bit symbol
PD8_0 PD8_1 PD8_2 PD8_3 PD8_4
RW
Nothing is assigned. This bit can either be set nor reset. When read, its content is indeterminate. PD8_6 PD8_7 Port P86 direction register Port P87 direction register 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port)
Figure 1.110: Direction register 1-120
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Port Pi register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Pi (i = 0 to 3,6,7,10)
Address 03E016, 03E116, 03E416, 03E516 03EC16, 03ED16, 03F416 Bit name Function
Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : "L" level data 1 : "H" level data (i = 0 to 3,6,7,10)
When reset Indeterminate Indeterminate RW
Bit symbol
Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7
Port Pi0 register Port Pi1 register Port Pi2 register Port Pi3 register Port Pi4 register Port Pi5 register Port Pi6 register Port Pi7 register
Port P8 register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol P8 Bit symbol
P8_0 P8_1 P8_2 P8_3 P8_4 P8_5 P8_6 P8_7
Address 03F016 Bit name
Port P80 register Port P81 register Port P82 register Port P83 register Port P84 register Port P85 register Port P86 register Port P87 register
When reset Indeterminate Function
Data is input and output to and from each pin by reading and writing to and from each corresponding bit (except for P8 5) 0 : "L" level data 1 : "H" level data
RW
Figure 1.111: Port register
Pull-up control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR0 Bit symbol
PU00 PU01 PU02 PU03 PU04 PU05 PU06 PU07
Address 03FC16 Bit name
P00 to P03 pull-up P04 to P07 pull-up P10 to P13 pull-up P14 to P17 pull-up P20 to P23 pull-up P24 to P27 pull-up P30 to P33 pull-up P34 to P37 pull-up
When reset 0016 Function
The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high
RW
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR1 Bit symbol
PU10 PU11 PU12 PU13 PU14 PU15 PU16 PU17
Address 03FD16 Bit name
P60 to P63 pull-up P64 to P67 pull-up P70 to P73 pull-up P74 to P77 pull-up P80 to P83 pull-up P84, P86, P87 pull-up P100 to P103 pull-up P104 to P107 pull-up
When reset 0016 Function
The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high RW
Figure 1.112: Pull-up control register 1-121
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Port 2 Drive Capacity Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol P2DR Bit symbol
P2DR0 P2DR1 P2DR2 P2DR3 P2DR4 P2DR5 P2DR6 P2DR7
Address 03FA16 Bit name
P20 LED drive capacity P21 LED drive capacity P22 LED drive capacity P23 LED drive capacity P24 LED drive capacity P25 LED drive capacity P26 LED drive capacity P27 LED drive capacity
When reset 0016 Function
The N-channel high-drive capacity is activated for the corresponding bit. 0 : Normal drive 1 : N-channel high drive
RW
Timer A Output drive capacity register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TADR Bit symbol
TADR0 TADR1 TADR2 TADR3 TADR4
Address 03FB16 Bit name
TA0OUT drive capacity TA1OUT drive capacity TA2OUT drive capacity TA3OUT drive capacity TA4OUT drive capacity
When reset 0016 Function
High-drive capacity is activated for the corresponding TAiOUT pin. 0 : Normal drive 1 : High drive RW
Nothing is assigned. These bits can neither be set nor reset. When read, their content is 0.
__
Figure 1.113: Port 2 and Timer A Output drive capacity registers
1-122
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Microcomputer
Port P0 to P3, P6-P8, P10 (except P85) (Input mode) * * * (Input mode) (Output mode) USB D+ USB D* * *
Open Open Open
NMI XOUT SOF ATTACH Open Open Open VCC AVCC ExtCap (Note 1) BYTE AVSS VREF VSS
Note: This is an example when the DC-DC converter is disabled
Figure 1.114: Example connection unused pins Table 1.37: Example connection of unused pins in single-chip mode Pin name
Ports P0 to P3, P6 to P8, P10 (excluding P85) Xout NMI AVcc Avss, Vref, BYTE USB D+, USB DExtCap SOF ATTACH
Connection
After setting for input mode, connect every pin to Vss or Vcc via a resistor; or after setting for output mode, leave these pins open Open Connect via resistor to Vcc (pull-up) Connect to Vcc Connect to Vss Open Connect to Vcc (when DC-DC converter is disabled) Connect to Vss via cap (when DC-DC converter is enabled and using the ATTACH function) Open Open
1-123
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Usage Precautions
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
3.0 Usage
3.1 Usage Precautions
3.1.1 A-D Converter * Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs). In particular, when the Vref connection bit is changed from "0" to "1", start A-D conversion after an elapse of 1 s or longer. * When changing A-D operation mode, select analog input pin again. * Using one-shot mode or single sweep mode
Read the corresponding A-D register after confirming the A-D conversion is finished. (It is known by A-D conversion interrupt request bit.)
* Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1
Use the undivided main clock as the internal CPU clock.
3.1.2 Built-in PROM version * All built-in PROM versions
High voltage is required to program to the built-in PROM. Be careful not to apply excessive voltage. Be especially careful during power-on.
* One Time PROM version
One Time PROM versions shipped in blank, of which built-in PROMs are programmed by users, are also provided. For these microcomputers, a programming test and screening are not performed in the assembly process and the following processes. To improve their reliability after programming, we recommend to program and test as flow shown in Figure 115 before use. Wiring for the Vpp pin of the One-Time PROM version should be as follows (Vpp pin is also used as the CNVss pin): * Make the length of wiring between the Vpp pin and Vss pin or Vcc pin the shortest possible. * When the wiring length has to be longer, connect an approximately 5K ohm resistor in series from the Vpp pin to the Vss pin or Vcc pin with the shortest possible wiring. This is because the Vpp pin is the power source input pin for the built-in PROM. When programming in the built-in PROM, the impedance of the Vpp pin is low to allow the electric current for wiring flow into the PROM. Because of this, noise can enter easily. If noise enters the Vpp pin, abnormal instruction codes or data are read from the built-in PROM which may cause a program runaway.
3.1.3 Dedicated Input Pins If a dedicated input pin is connected to a power supply that is different than the supply that Vcc is connected to, a resistor (approximately 1k ohm) should be added between that input pin and the power supply it is connected to, otherwise, if the dedicated input pin voltage is higher than Vcc, latch up could occur.
1-124
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Usage Precautions
3.1.4 DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When the DMA enable bit (bit 3 of DM0CON and DM1CON) is set to "1", the DMAC is in an active state. The DMA request bit (bit 2 of DM0CON and DM1CON) is set to "1" when a request for DMA transfer occurs, regardless of the state of the DMA enable bit. If the DMAC is active when the request bit becomes "1", the data transfer begins immediately. The request bit is cleared to "0" when the transfer begins. It is also possible for the DMA request bit to get set to a "1" due to the DMA request cause select bits being changed. Therefore, the DMA request bit should be cleared ("0") after changing the DMA request cause select bits. To best judge the state of the DMAC, the DMA enable bit should be read instead of the DMA request bit. 3.1.5 Interrupts * Reading address 0000016
* When a maskable interrupts occurs, the CPU reads the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the corresponding interrupt written in address 0000016 is then set to "0". Reading address 0000016 by software sets enabled highest priority interrupt source request bit to "0". Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 0000016 by software.
* Setting the stack pointer
* The value of the stack pointer is initialized to 0000016 immediately after reset. Accepting an interrupt before setting a value in the stack pointer may cause program runaway. Be sure to set a value in the stack pointer before accepting an interrupt. * When using the NMI interrupt, initialize the stack pointer at the beginning of a program. Concerning the first instruction immediately after reset, generating any interrupts including the NMI interrupt is prohibited.
* Setting interrupts
* Changing the Interrupt Priority Level select bit (ILVL) and clearing the Interrupt Request bit (IR) in the Interrupt Control Registers (ICR) while the Interrupt enable flag (I-FLAG) is "1", may result in unintended operations, such as BRK and other interrupts being generated. It is recommended that the interrupts be disabled by clearing the I-FLAG before setting ILVL or clearing the IR bit. To prevent the I-FLAG from being set before the ICR is rewritten due to the effects of the instruction queue, instructions that equal a minimum of 2 cycles should be inserted between writing to the ICR and setting the I-FLAG (2-NOPs, I MOV, I POP, etc.)
* The NMI interrupt
* * As for the NMI interrupt pin, an interrupt cannot be prohibited. Connect it to the Vcc pin if unused. Do not get into stop mode or wait mode with the NMI pin set to "0".
3.1.6 Noise To reduce the possibility of noise problems: * Connect a bypass capacitor (approximately 0.1 uF) across the Vss pin and the Vcc pin with the shortest possible wiring * Use circuit traces with a larger diameter than other signal traces for Vss and Vcc. 3.1.7 Stop Mode and Wait Mode * When returning from stop mode by hardware reset, RESET pin must be set to "L" level until main clock oscillation is stabilized. * When entering either wait or stop mode, you must first enable any interrupts you want to cancel the wait or stop. Also, make sure to disable any interrupts that you don't want to cancel the wait or stop. If only hardware reset or NMI interrupts are desired to cancel wait or stop, all other interrupt priority levels should be set to "0". 1-125
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Usage Precautions
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
3.1.8 Timer A (timer mode) * Reading the Timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the Timer Ai register with the reload timing gets "FFFF16". Reading the Timer Ai register after setting a value in the Timer Ai register with a count halted but before the counter starts counting gets a proper value. 3.1.9 Timer A (event counter mode) * Reading the Timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the Timer Ai register with the reload timing gets "FFFF16" by underflow or "000016" by overflow. Reading the Timer Ai register after setting a value in the Timer Ai register with a count halted but before the counter starts counting gets a proper value. * When counting is stopped in free-run type, set the timer again. * When using Free-run type, the timer's register contents may be unknown when counting starts. Set the timer value immediately after counting has started. 3.1.10 Timer A (pulse width modulation mode) * The Timer Ai interrupt request bit becomes "1" if setting operation mode of the timer in compliance with any of the following procedures:
* Selecting PWM mode after reset. * Changing operation mode from timer mode to PWM mode. * Changing operation mode from event counter mode to PWM mode.
Therefore, to use Timer Ai interrupt (interrupt request bit), set Timer Ai interrupt request bit to "0" after the above listed changes have been made. * Setting the count start flag to "0" while PWM pulses are being output causes the counter to stop counting. If the TAiOUT pin is outputting an "H" level in this instance, the output level goes to "L", and the Timer Ai interrupt request bit goes to "1". If the TAiOUT pin is outputting an "L" level in this instance, the level does not change, and the Timer Ai interrupt request bit does not become "1". 3.1.11 Timer B (timer mode) * Reading the Timer Bi register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the Timer Bi register with the reload timing gets "FFFF16". Reading the Timer Bi register after setting a value in the Timer Bi register with a count halted but before the counter starts counting gets a proper value. 3.1.12 UART2 When using UART2 in clock asynchronous serial I/O mode (UART), use the internal clock only, otherwise, one of the following may occur:
* The interrupt may not be issued at the end of the data transmission when the hardware transfers the data from the transmit buffer to the transmit register. * Data may be corrupted when the hardware transfers data fro the transmit buffer register to the transmit register. This only applies to UART2 asynchronous serial I/O mode and does not apply to UART0 or UART1.
3.1.13 USB USB SFR refers to registers from 0x0300 to 0x033C. All these registers are physically inside the USB block and are affected by the USB reset. Also, these registers can only be accessed by 8-bit mode. USB related registers 0x00C, 0x03DB-0x3DF are not inside the USB block and are not affected by a USB reset and can be accessed by 8 or 16 bits.
1-126
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Usage Precautions
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programming with PROM programmer
Screening (Note) (Leave at 150C for 40 hours)
Verify test PROM programmer
Function check in target device
Note: Never expose to 150C exceeding 100 hours.
Figure 1.115: Programming and test flow for One-time PROM (OTP) version
1-127
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Electrical
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
4.0 Specifications
4.1 Electrical
Table 1.38:
Symbol
VCC AVCC VI VI VO Pd Topr Tstg Supply voltage Analog supply voltage Input voltage Input voltage Output voltage Power dissipation Operating ambient temperature Storage temperature
Port0, Port1, Port2, Port3, Port6, Port7, Port8, Port10, RESET, VREF, XIN
Absolute maximum ratings only, not operating conditions
Parameter Condition
VCC=AVCC VCC=AVCC -0.3 to 6.5 -0.3 to 6.5 -0.3 to Vcc+0.3 -0.3 to 6.5 -0.3 to Vcc+0.3 Ta=25 C 760 0 to 70 -65 to 150 (Note 1)
Rated Value
Unit
V V V V V mW C C
CNVSS
Port0, Port1, Port2, Port3, Port6, Port7, Port8 (except P85), Port10, RESET, VREF, XIN
Note 1: When writing to EPROM, CNVss rated value is -0.3 to 13 volts
Table 1.39:
Symbol
VCC AVCC VSS AVSS VIH VIL Ioh (peak)
Recommended operating conditions
Parameter
Supply voltage Analog supply voltage Supply voltage Analog supply voltage High input voltage Low input voltage High peak output current
Port 0, Port1, Port2, Port3, Port6, Port7, Port8, Port10, RESET, VREF, XIN, CNVSS Port0, Port1, Port2, Port3, Port6, Port7, Port8, Port10, RESET, VREF, XIN, CNVSS Port0, Port1, Port3, Port6, P71, P73, P75, P77, P81 to P87, Port10 P20 to P27, P70, P72, P74, P76, P80 Port0, Port1, Port3, Port6, P71, P73, P75, P77, P81 to P87, Port10 P20 to P27, P70, P72, P74, P76, P80 P2, P3, P6, P7, P80~P82 P0, P1, P83~P87, P10 P2, P3, P6, P7, P80~P82 P0, P1, P83~P87, P10 Port0, Port1, Port3, Port6, P71, P73, P75, P77, P81 to P87, Port10 P20 to P27, P70, P72, P74, P76, P80 Port0, Port1, Port3, Port6, P71, P73, P75, P77, P81 to P87, Port10 P20 to P27, P70, P72, P74, P76, P80 P2, P3, P6, P7, P80~P82 P0, P1, P83~P87, P10 P2, P3, P6, P7, P80~P82 P0, P1, P83~P87, P10
Standard Min
4.1
Typ
5.0 Vcc 0 0
Max
5.25
Unit
V V V V
0.8Vcc 0
Vcc 0.2Vcc -10 -20 -5 -10 -80 -80 -40 -40 10 20 5 10 80 80 40 40 12
V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA MHz
Ioh (avg.) Ioh(peak) Ioh (avg.) Iol (peak)
High avg output current High peak output current High avg output current Low peak output current
Iol (avg.) Iol (peak) Iol (avg. f(Xin)
Low avg output current Low peak output current Low avg output current
Main clock input oscillation frequency
1
Note: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
1-128
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Electrical
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.40: Symbol
VOH VOH VOH VOH VOH VOL VOL VOL VOL VOL
Electrical characteristics (Vcc=4.1~5.25V, Vss=0V, Ta= 0C~ 70C, f(Xin) = 12MHz
Parameter
High output voltage High output voltage High output voltage High output voltage High output voltage Low output voltage Low output voltage Low output voltage Low output voltage Low output voltage
Port0, Port1, Port2, Port3, Port6, Port71, P73,P75,P77,Port8 (except P85), Port10 Port 70,P72,P74,P76,P80 Port0, Port1, Port2, Port3, Port6, Port71, P73,P75,P77,Port8 (except P85), Port10 High-drive mode Port 2
Measuring condition
IOH = -5mA IOH = -10mA IOH = -200A IOH = -10mA IOH = -1mA IOH = -0.5mA IOL = 5mA IOL = 10mA IOL= 10mA IOL = 200A IOH = 1mA IOH = 0.5mA
Min
3.0 3.0 4.7 3.0 3.0 3.0
Standard Typ Max
Unit
V V V
Xout
high power low power
V V 2.0 2.0 2.0 0.45 2.0 2.0 V V V V V V V V A A k M V 80 95 50 1 20 8 mA mA mA A A mA
Port0, Port1, Port2, Port3, Port6, Port71, P73,P75,P77,Port8 (except P85), Port10 High-drive mode Port 2 Port 70,P72,P74,P76,P80 NOTE 1 Port0, Port1, Port2, Port3, Port6, Port71, P73,P75,P77,Port8 (except P85), Port10
Xout
VT+-VTVT+-VTIih Iil RPULLUP RXIN VRAM
Hysteresis Hysteresis High input current Low input current Pull-up resistance
high power low power TA0in to TA4in, INT0 to INT1, ADTRG, CTS0, CTS1, CLK0, CLK1, TA2out to TA4out, NMI, KI0 to KI15
0.2 0.2 VI = 5V VI = 0V VI = 0V When clock is stopped
Icc run with USB ON (Mask) Icc run with USB ON (OTP) Icc run with USB OFF
0.8 1.8 5.0 -5.0
RESET Port0, Port1, Port2, Port3, Port6, Port7,Port8, Port10, RESET, CNVss Port0, Port1, Port2, Port3, Port6, Port7, Port8, Port10, RESET, CNVss Port0, Port1, Port2, Port3, Port6, Port7, Port8, Port10
30 2.0
50 1.0
167
Feedback resistance, Xin RAM retention voltage
Ta=25C
Icc
Power supply current
Output pins open, other pins tied to Vss
clock stopped
Ta=70C
clock stopped
Ta=25C
wait mode with internal clocks ON
Ta=25C
wait mode with internal clocks OFF
4
mA
Note 1 Only high drive when Timer A is enabled and drive registers set for high drive mode.
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Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Timing
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.41: Symbol VOH VOL Isusp
USB Electrical Characteristics (Vcc=4.1~5.25V, Vss=0V, Ta= 0C 70C, f(Xin) = 12MHz)
Standard
Parameter
D+, DD+, DSuspend current DC-DC converter voltage
Measuring Condition Min I=18.3 mA, RX=33 , VXcap =3.0 V I=18.3 mA, RX=33 , VXcap =3.0 V USB suspend mode, internal clock stopped DC-DC converter output voltage on Xcap pin 3.0 3.3 2.2 0.8 175 Typ Max
Unit V V A
Xcap
3.6
V
Note: See Fig. 122 for recommended configuration.
4.2 Timing
Table 1.42: Symbol
R Gonave tCONV tSAMP VREF VIA AD Resolution Sample and hold function not available Absolute Sample and hold function available (10bit) accuracy Sample and hold function available (8bit) Ladder resistance Conversion time (10bit) Conversion time (8bit) Sampling time Reference voltage Analog input voltage (min. operating frequency =x) A-D clock frequency A-D conversion characteristics (Vcc, Avcc = 4.1~5.25V, Vss=0V, Ta= 0C~ 70C, f(Xin) = 12MHz)
Parameter
Measuring condition
VREF = Vcc VREF = Vcc = 5V VREF = Vcc = 5V VREF = Vcc = 5V VREF = Vcc
Min
Standard Typ Max
10 3 3 2 40
Unit
Bits LSB LSB LSB k s s s V V MHz
10 2.75 2.34 0.25 2 0 1
VREF 12
Timing requirements referenced to Vcc = 4.1~5.25V, Vss=0V, Ta= 0C~70C unless otherwise specified.
Table 1.43: Symbol
tc tw(H) tw(L) tr tf
External clock input Parameter
External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time
Standard Min Max
83.3 33 33 15 15
Unit
ns ns ns ns ns
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Mitsubishi microcomputers
M30240 Group
Timing
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.44: Symbol
tc(TA) tw(TAH) tw(TAL)
Timer A input (counter input in event counter mode) Parameter
TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width
Standard Min Max
100 40 40
Unit
ns ns ns
Table 1.45: Symbol
tc(TA) tw(TAH) tw(TAL)
Timer A input (gating input in timer mode) Parameter
TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width
Standard Min Max
400 200 200
Unit
ns ns ns
Table 1.46: Symbol
tc(TA) tw(TAH) tw(TAL)
Timer A input (external trigger input in one-shot timer mode) Parameter
TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width
Standard Min Max
200 100 100
Unit
ns ns ns
Table 1.47: Symbol
tw(TAH) tw(TAL)
Timer A input (external trigger input in pulse width modulation mode) Parameter
TAiIN input HIGH pulse width TAiIN input LOW pulse width
Standard Min Max
100 100
Unit
ns ns
Table 1.48: Symbol
tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP)
Timer A input (up/down input in event counter mode) Parameter
TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time
Standard Min Max
2000 1000 1000 400 400
Unit
ns ns ns ns ns
Table 1.49: Symbol
tc(AD) tw(ADL)
A-D trigger input Parameter
ADTRG input cycle time (triggerable minimum) ADTRG input LOW pulse width
Standard Min Max
1000 125
Unit
ns ns
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Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Timing
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.50: Symbol
tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D)
Serial I/O Parameter
CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time
Standard Min Max
200 100 100 80 0 30 90
Unit
ns ns ns ns ns ns ns
Table 1.51: Symbol
tw(INH) tw(INL)
External interrupt INTi inputs Parameter
INTi INTi
Standard Min Max
250 250
Unit
ns ns
input HIGH pulse width input LOW pulse width
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Mitsubishi microcomputers
M30240 Group
Timing Diagrams- Peripheral/interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
4.3 Timing Diagrams- Peripheral/interrupt
tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input
(When count on falling edge is selected)
th(TIN-UP)
tsu(UP-TIN)
TAiIN input
(When count on rising edge is selected)
tc(AD) tw(ADL) ADTRG input
tc(CK) tw(CKH) CLKi tw(CKL) TxDi td(C-Q) RxDi tw(INL) INTi input tw(INH) tsu(D-C) th(C-D) th(C-Q)
Figure 1.116: Peripheral / Interrupt timing diagram
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Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Frequency Synthesizer Interface and DC-DC Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
5.0 Applications
5.1 Frequency Synthesizer Interface and DC-DC Converter
This section presents the recommended method of setting up and using the frequency synthesizer that generates the 48MHz clock needed by the USB FCU and the DC-DC converter that provides power to the D+/D- drivers 5.1.1 Reset of USB Related Registers
Hardware Reset
SFR Registers: 000416 to 005F16, 000C (USBC), 37816 to 3FF16 3DC16 (FSC)
USB Reset
SFR Registers: 30016 to 33C16
(USB FCU registers)
Figure 1.117: SFR Reset Venn Diagram The special function registers (SFRs) that govern the operation of the frequency synthesizer, DC-DC converter and USB FCU are affected by one or more reset events. The addresses of the special function registers (SFRs) that are affected by Hardware Reset, USB Reset, or both are shown in Figure 1.117. All resettable SFRs, including SFRs and other registers internal to the USB FCU, are affected by a Hardware Reset, which occurs when the RESET pin is brought low or an undefined opcode is fetched. See Section 2.4 for a complete listing of SFRs and their reset values. Only registers internal to the USB FCU are reset when a USB Reset sent by the Host/Hub is detected. These USB registers are reset to their default values except for bit 5 of USBIS2 (USB Reset Interrupt Status Flag), which is set to a "1". USB FCU registers are registers from address 30016to 33C16 and all other registers within the USB FCU, many of which the MCU does not have direct access to (e.g. FIFO address pointers). The USB FIFO registers are empty after USB reset because the FIFO address pointers are reset. However, the physical contents of the FIFOs are not set to all `1`s or all `0`s. Other SFRs such as USBC, FSC, and CM0, CM1 are not affected by a USB Reset.
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Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Frequency Synthesizer Interface and DC-DC Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
5.1.2 Set up of Frequency Synthesizer and DC-DC Converter
f(Xin)
Frequency Synthesizer
enable lock
USBC5 DC-DC Converter
(enable) enable current mode
FSE
LS
USBC4
USBC3
(enable) 2.2 F
Ext Cap
1.5k 0.1 F
D+ USBCLK (48MHz) USB FCU USB Transceiver Denable enable
33
33
USBC7 USBC7
Figure 1.118: PLL, DC-DC Converter and USB Functional Block Diagram A functional block diagram of the USB system on the M30240 which shows how the control signals affect operation is given in Figure 1.118 5.1.2.1 Set up after Hardware Reset A Hardware Reset occurs when either the RESET pin is brought low for more than 2 s or an invalid opcode is fetched by the CPU. The frequency synthesizer (PLL) and DC-DC converter should be set up as follows in the Hardware Reset routine (see Figure 1.119), * Power up the M30240 and other components on the peripheral device for less than 100 mA operation. The current limit only applies for bus powered devices. * Configure the PLL for 48MHz f(VCO) operation. * Enable the PLL by setting FSE (bit 0 of the Frequency Synthesizer Control Register (FSC)) to a "1", then wait for 2 ms. * Check the lock status bit (LS, bit 7 of FSC).
* If the bit is a "1", go on. * If the bit is a "0", wait 0.1 ms longer and then re-check the bit.
* Enable the DC-DC converter in high current mode by setting USBC4 (bit 4 of the USB Control Register (USBC)) to a "1" and keeping USBC3 (bit 3 of USBC) a "0". High current mode should always be used during normal USB operation. Low current mode should only be used during a USB suspend. * Wait (C + 1)ms (where C equals the external capacitance connected to the Ext Cap pin in F) for the voltage on Ext Cap to reach a steady state voltage of approximately 3.3V. (Since the D+ pullup is connected to the Ext Cap pin, the upstream hub will detect that the peripheral device has been plugged in once the voltage on D+ reaches approximately 2.0 V.)
* Example: A 2.2 F capacitor connected to Ext Cap requires 3.2 ms for the voltage on Ext Cap to be stable.
1-135
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Frequency Synthesizer Interface and DC-DC Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
* Enable the USB clock by setting USBC5 (bit 5 of USBC) to a "1". (If the USB clock and FCU are enabled before the voltage on Ext Cap is stable, a phantom USB Reset may be detected, or the actual USB Reset may not be detected.) * Wait at least 4 cycles of , then enable the USB FCU by setting USBC7 (bit 7 of USBC) to a "1". * Enable other blocks as necessary.
RESET FSE
Enable PLL
Wait 2 ms LS Enable DC-DC converter USBC4 Wait (C+1) ms USBC5 Enable USB Clock Wait at least 4 cycles of
USBC7 Enable USB FCU Figure 1.119: PLL and DC-DC Converter Set Up Timing after Hardware Reset
5.1.2.1.1 Precautions after Software Reset A software reset occurs after writing a `1' to bit `3' of the processor mode register 0 (address 000416). During software reset, the contents of the internal RAM are preserved as well as all USB, DC-DC converter, and PLL registers. If the PLL is used as the system clock source, it is important to note that after a software reset occurs, any writes to the frequency synthesizer register will cause it to freeze. This can cause erratic device behavior. In order to avoid this, it is recommended that the following procedure be used: * Prior to software reset, switch device clock source from `fsyn to f(Xin)'. Please see the Frequency Synthesizer specification for more details. * After software reset using firmware, evaluate the condition of the synthesizer control register (FSC register, address 03DC16, bit `0'). This bit is not effected by a software reset and can check to see if the PLL is still enabled. If so, any setup routine that involves writing to the PLL registers should not be called. At this point, the clock source can be changed back to fsyn.
5.1.2.2 Set up after USB Reset Signaling Detected A USB Reset is detected by the USB FCU when an SE0 is present on D+/D- for at least 2.5 s. Detection of a USB Reset results in bit 5 of USB Interrupt Status Register 2 (USBIS2) being set to a "1" and the registers within the USB FCU being reset to their default values. Register USBC and the PLL registers are not affected by a USB Reset. A USB Function Interrupt request is also generated when the USB Reset is detected. No modifications to the frequency synthesizer or DC-DC converter configuration should be made in the USB Function Interrupt routine. However, all USB FCU registers (addresses 30016 to 33C16) must be reconfigured to their pre-enumeration state.
1-136
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Frequency Synthesizer Interface and DC-DC Converter
5.1.2.3 Set up after USB Suspend Detected
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A USB Suspend occurs if the USB FCU does not detect any bus activity on D+/D- for at least 3 ms. Detection of a suspend results in bit 7 of USBIS2 and bit 0 of USBPM (SUSPEND) being set to a "1". This causes bit 3 of SUSPIC to be set to a "1". Bit 7 of USBIS2 then needs to be cleared by writing a "1" to the bit in order to allow a future suspend event. The configuration of the frequency synthesizer and DC-DC converter should be changed as follows in the USB Suspend Interrupt routine (if the device is bus powered): * Change the DC-DC converter from high current mode to low current mode by setting USBC3 (bit 3 of the USBC) to a "1" * Disable the USB clock by setting USBC5 (bit 5 of USBC) to a "0". Once the USB clock is disabled, registers internal to the USB FCU should not be written to. This includes all USB SFRs from address 030016 to 033C16. It does not include USBC or FSC. * Perform other tasks to reduce total current to below 500A. * Disable the PLL by setting FSE (bit 0 of FSC) to a "0". * Make sure the I-FLAG is set to "1". * Stop the system clock by setting CM10 (bit 0 of CM1) to a "1". Make sure to first enable writing to the system clock control register by setting PRCO (bit 0 of PRCR) to "1'. Also, make sure to enable the USB Resume Interrupt (RSMIC register) and clear or execute any pending interrupts prior to stopping the clock so the MCU can wake up once resume signaling is detected. If the clock is stopped using an interrupt routine, make sure to set the priority of the Resume Interrupt (RSMIC) higher than the current interrupt. * Note that no action may be necessary if the device is self powered. 5.1.2.4 Set up after USB Resume Signaling Detected A resume occurs when the USB FCU is in the suspend state and detects a non-idle signaling on D+/ D-. Detection of a resume results in bit 6 of USBIS2 and bit 1 of USBPM (RESUME) being set to a "1". This causes bit 3 of RSMIC to also be set to "1". If the MCU was in the stop state prior to the detection of the resume, the USB Resume Interrupt request will cause the MCU to wake up from the stop state. Bit 6 of USBIS2 needs to be cleared (by writing a "1" to the bit) in order to allow a future resume event. See section 2.9 "Stop Mode" for details on waking up from the stop state. The configuration of the frequency synthesizer and DC-DC converter should be changed as follows in the USB Resume Interrupt routine (if the device is bus powered): * Re-enable the PLL for 48MHz f(VCO) by setting FSE (bit 0 of the FSC) to a "1", then wait for 2 ms. * Wait for 2 ms. * Check the lock status bit (LS, bit 7 of FSC).
* If the bit is a "1", continue. * If the bit is a "0", wait 0.1 ms longer and then re-check the bit.
* Enable the USB clock by setting USBC5 (bit 5 of USBC) to a "1". * Wait for a minimum of 4 cycles. * Change the DC-DC converter from low current mode to high current mode by setting USBC3 (bit 3 of the USBC) to a "0". * Enable other blocks as necessary. Registers internal to the USB FCU should not be written to until the USB clock is re-enabled. This includes all USB SFRs from address 030016 to 033C16. It does not include USBC or FSC. Note that the configuration changes described above may not need to be made if the MCU was not placed in a suspend state as described in section 5.1.2.3 Set up after USB Suspend Detected.
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Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Mitsubishi microcomputers
M30240 Group
Attach/Detach Function
5.1.2.5 PLL Lock Bit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The PLL lock bit is used to indicate when the PLL is first locked. Accordingly, after the PLL is enabled and it has been given 2.0 ms to stabilize, the lock bit status should be checked. Once the lock bit is HIGH, the USB check should be enabled. After this stage, the lock bit is no longer valid and should not be monitored, unless the PLL is re-enabled.
5.2 Attach/Detach Function
The Attach/Detach Function can be used to attach or detach a USB function from the host without disconnecting the cable. When attaching a USB function, the connect registers should be set to 3 Hex at the same time on or before the DC-DC Converter is enabled. Similarly, when detaching the connect register, it should be set to 1 Hex when powering down the DC-DC Converter. If you do not set the connect (address 1fh) to HIGH, the system will default to its normal mode. Note: If the D+ is connected to ExtCAP, this mode will not work. D+ is connected to ExtCAP through a 1.5 K resistor in compliance with the USB specification. USB Suspend/Resume Function Hardware connections are shown below
Attach is connected to D+ through 1.5 K resistor. Attach [P83] 1.5 K Attach/Detach mode disabled ExtCAP 1.5 K D+ (pin 9 M30240) D+ (pin 9 M30240)
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Mitsubishi microcomputers
M30240 Group
Low Pass Filter Network 5.3 Low Pass Filter Network
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
All passive components should be in close proximity to pin 78 (LPF), capacitors should be X7R dielectric or better. The recommended values are listed in Table 1.52 . See Figure 1.120 for schematic of the LPF. Table 1.52: Recommended Values
10% 10% 10%
R 1000 C2 = 680 pf C1 = 0.1 f
Pin 78 (LPF) R C2
C1 Pin 77 Avss
Figure 1.120: LPF Filter Schematic Analog Vss and Analog Vcc, pins 77 and 80 should have isolated connections to the digital Vss and Vcc ground planes. Figure 1.121 illustrates the power supply isolation.
Ferrite Beads
Digital Vcc (on card) C Digital Vss
Decoupling Capacitors
Analog Vcc (Pin 80) C Analog Vss (Pin 77)
Figure 1.121: Power Supply
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Mitsubishi microcomputers
M30240 Group
USB Transceiver 5.4 USB Transceiver
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When using the on-chip voltage converter to supply the necessary 3.3V to the driver circuit, a capacitor network must be connected between Ext. Cap (pin 6) and VSS (pin 13). Two capacitors are required as shown in Figure 1.122. The high frequency 0.1 F capacitor should be an X7R type or better. The low frequency decoupling capacitor of 2.2 F should be of tantalum di-electric or better. The startup time for this value of the capacitor is 3.2 ms, approximately (1ms/ F) + 1 ms. After enabling the on-chip voltage converter, a certain amount of time must pass before a wait or stop clock instruction is executed. The amount of time is given by (C+1) ms, when C is the value in F of the external capacitance connected to the Ext. Cap pin. For example, if the external capacitance is 2.2 F, at least 3.2 ms must elapse from the time that the on-chip voltage converter is enabled until a WAIT instruction or STOP command (CM10 = 1) is executed. In order to meet the impedance matching requirements of the USB Specification, a 33 resistor must be added to USB D+ (pin 9) and to USB D- (pin 10). In addition, capacitors connected between USB D+ and USB D- or USB D+/D- and Vss may need to be added for rise/fall time matching and edge control. These capacitors should be placed after the 33 resistors. Their configuration and values ` will depend on the PCs layout. The placement of external components is illustrated in Figure 1.122.
Voltage Converter Ext Cap
2.2 F
10%
0.1 F 10%
USB_Vp_out USB_Txen_n USB_Vm_out USB_Suspend USB_Rxd
XCV_Vp_out XCV_Txen_n XCV_Vm_out XCV_Suspend XCV_Rxd XCV_Vp_in
D+ D-
33 33 pF 33 = 22 pF (Note) 22 pF
USB Block
+ _
=
USB_Vp_in
USB_Vm_in
XCV_Vm_in
Transceiver
Note: Capacitor values and configuration may depend on PCB layout.
Figure 1.122: Configuration of External USB components
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Mitsubishi microcomputers
M30240 Group
Programming Notes 5.5 Programming Notes
5.5.1 Accessing USB IN/OUT CSR Registers
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Do not use read-modify-write instruction on these registers because they contain control and status bits that can be changed by both hardware and software. There is a possibility that using a read-modify-write instruction might cause incorrect data to be written back to these registers. See Table 1.53 for a list of bits that may have incorrect data written to them and the value you should write back in order to prevent this from occurring. Table 1.53: Bits that might have incorrect data
Bit name IN_PKT_RDY (b1) EP0CS DATA_END (b3) FORCE_STALL (b4) IN_PKT_RDY (b0) EPxICS (x = 1-4) UNDER_RUN (b1) OUT_PKT_RDY (b0) OVER_RUN (b1) EPxOCS (x = 1-4) FORCE_STALL (b4) DATA-ERR (b5) "1" "1" "1" "1" "1" Value to write for "No change" "0" "0" "1" "0"
Register name
The endpoint 1-4 IN CSR's (EPiICS, i = 1-4) have a bit IN_PKT_RDY (bit 0) that is set to a "1" by the firmware after a packet of data is loaded to the respective endpoint's FIFO. This signifies that a packet is ready for transmission. If the firmware wants to send a NULL packet to the host, it can simply write a "1" to the IN_PKT_RDY bit without loading data to the FIFO. This bit is cleared by the hardware. If the firmware manipulates (writes) the IN CSR for a purpose other than to signify to the hardware that a data packet is ready for transmission (for instance, set/reset ISO bit, set/reset SEND_STALL bit), it must make sure that a "0" is written back to the IN_PKT_RDY bit. Failure to do so could cause improper operation of the device. Writing a "0" to the IN_PKT_RDY bit has no effect on its state. The endpoint 1-4 OUT CSRs (EPiICS, i = 1-4) have a bit OUT_PKT_RDY (bit 0) that is set to a "1" by the hardware after a packet of data is received from the host to the respective endpoint's FIFO. This signifies that a packet is ready for download. This bit is cleared by the firmware by writing a "0" to it after the data packet is unloaded from the FIFO. If the firmware manipulates (writes) the OUT CSR for a purpose other than to signify to the hardware that a data packet has been unloaded (for instance, set/reset ISO bit, set/reset SEND_STALL bit), it must make sure that a "1" is written back to the OUT_PKT_RDY bit. Failure to do so could cause improper operation. Writing a "1" to the OUT_PKT_RDY bit has no effect on its state.
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Mitsubishi microcomputers
M30240 Group
Programming Notes
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Below is an example of how to set/reset the ISO bit of the IN CSR register (for initializing the respective endpoint as an isochronous endpoint):
[R1L] = [EPiICS].B OR.B #08H, R1L AND.B #0FEH, R1L [EPiICS].B = [R1L] [R1L] = [EPiICS].B OR.B #02, R1L AND.B #0F6H, R1L [EPiICS].B= [R1L] ;write "1" back to UNDER_RUN bit ;reset ISO bit = 0, write "0" back to IN_PKT_RDY bit ;set ISO bit = 1, write "1" back to UNDER_RUN bit ;write "0" back to IN_PKT_RDY bit
5.5.2 USB Consecutive Set Address The USB Specification states that the host can send a SET_ADDRESS request for the following cases: 1. During enumeration when the device is in default state. (The host assigns a non-zero address.) 2. When the device is in the address state. (The host can re-assign a new address.) The device handles case #1 (when the device is in the default state) and case #2 (when the device is in the address state) differently. The following is a segment of code to illustrate the program flow to properly deal with these cases.
DEFAULT_STATE: If [USBA].B ==0 [USBA.].B = wValue _ lo R1L = [EP0CS].B OR.B #48H, R1L [EP0CS].B = R1L wait for the completion of the JMP ADDR_END else ADDR_STATE R1L [EP0CS].B OR.B #48H, R1L [EP0CS].B = R1L wait for the completion of the [USBA].B= wValue_lo ADDR_END endif end of the set_address routine ;If the device is in default state, update address before STATUS completion ;USB ENDPOINT 0 CSR ;Set serviced_out_pkt_rdy & data_end
;USB ENDPOINT 0 CSR ;Set serviced_out_pkt_rdy & data_end
;If the device is in address state, update address before STATUS completion
Note: wValue_lo = assigned address from the host in SET-ADDRESS request.
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