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PRELIMINARY TECHNICAL DATA
FEATURES
SFP reference design available Input sensitivity: 4 mV p-p 80 ps rise/fall times CML outputs: 700 mV p-p differential Programmable LOS detector: 3mV to 40 mV Rx signal strength indicator (RSSI): SFF-8472 compliant average power measurement Single-supply operation: 3.3 V Low power dissipation: 145 mW Available in space-saving 3 mm x 3 mm 16-lead LFCSP Extended Temperature Range: -40oC to 95oC
3.3 V 3.2 Gb/s Limiting Amplifier ADN2891
GENERAL DESCRIPTION
The ADN2891 limiting amplifier works as a data quantizer optimized for SONET, Gigabit Ethernet (GbE), and Fibre Channel optical receivers in the range of 155Mpbs and up to 3.2Gbps . It accepts input levels of up to 2.0 V p-p differential with 4mV p-p differential input sensitivity and outputs current mode logic (CML) voltages with controlled edge speeds.. The ADN2891 measures average received power based on a direct measurement of the photodiode current with better than 1 dB of accuracy over the entire input range of the receiver. This eliminates the need for external RSSI detection circuitry in SFF8472 compliant optical transceivers. Additional features includes a programmable loss-of-signal (LOS) detect and output Squelch. The ADN2891 limiting amplifier operates from a single 3.3 V supply, has low power dissipation, and is available in a 3 mm x 3 mm 16-lead lead frame chip scale package (LFCSP).
APPLICATIONS
SFP/SFF/GBIC optical transceivers OC-3/12/48, GbE, Fibre Channel receivers 10GBASE-LX4 transceivers WDM transponders
FUNCTIONAL BLOCK DIAGRAM
ADN2880
VREF PD_VCC PD_CATHODE
+V 10k ADuC7020
CAZ1 0.01F
C AZ2
Figure 1. ADN2891 Typical Application Circuit
Rev. PrA.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
ADN2891 TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ........................................................................ 8 LIMAMP ....................................................................................... 8
PRELIMINARY TECHNICAL DATA
Loss of Signal (LOS) Detector .....................................................8 Received Signal Strength Indicator (RSSI) ................................8 Squelch Mode ................................................................................8 Applications Information .................................................................9 PCB Design Guidelines ................................................................9 Outline Dimensions ....................................................................... 11 Ordering Guide .......................................................................... 11
REVISION HISTORY
Revision PrA: Initial Version
Rev. PrA | Page 2 of 12
PRELIMINARY TECHNICAL DATA SPECIFICATIONS
Table 1. Test Conditions: VCC = 3.0V to 3.6V, VEE = 0 V, TA = -40 oC to 95 oC, unless otherwise noted.
Parameter QUANTIZER DC CHARACTERISTICS Input Voltage Range Input Common Mode Peak-to-Peak Differential Input Range Input Sensitivity Input Offset Voltage Input RMS Noise Input Resistance Input Capacitance QUANTIZER AC CHARACTERISTICS Input Data Rate Small Signal Gain S11 S22 Random Jitter Deterministic Jitter Low Frequency Cutoff Power Supply Rejection LOSS OF SIGNAL DETECTOR (LOS) LOS Assert Level Hysteresis TBD TBD LOS Assert Time LOS De-Assert Time RSSI Input Current Range RSSI Output Accuracy Gain Offset Compliance Voltage POWER SUPPLIES VCC ICC OPERATING TEMPERATURE RANGE CML OUTPUT CHARACTERISTICS Output Impedance Output Voltage Swing Output Rise and Fall Time LOGIC INPUTS (SQUELCH) VIH, Input High Voltage VIL, Input Low Voltage Input Current Min 1.8 2.1 4 3 100 205 50 0.65 3200 51 -10 -10 2.4 13.7 30 1.0 45 TBD TBD 2.0 40 3.0 3.0 4.5 4.5 600 100 5 1000 15% 10% 1.0 50 VCC - 0.9 3.0 -40 3.3 44 +25 50 700 80 VCC - 0.3 3.6 60 +95 Typ Max 2.8 2.7 2.0 Unit V p-p V V p-p mV p-p V V rms pF Mb/s dB dB dB ps rms ps p-p kHz kHz dB mV p-p mV p-p dB dB dB dB ns ns A IIN 20 A IIN > 20 A IRSSI/IPD @ PD_CATHODE
ADN2891
Test Conditions/Comments @ PIN or NIN, dc-coupled DC-coupled PIN - NIN, ac-coupled PIN - NIN, BER 1 x 10-10
Single-ended
155
Differential Differential, f < 3.2 GHz Differential, f < 3.2 GHz
Input > 10 mV p-p, OC-48, PRBS 223 - 1 Input > 10 mV p-p, OC-48, PRBS 223 - 1
5 19
CAZ = Open CAZ = 0.0 1 F 100 kHz < f < 10 MHz RTHRADJ = 1M RTHRADJ = 500
OC-3, PRBS 223 - 1, RTHRADJ = 500 OC-3, PRBS 223 - 1, RTHRADJ = 1M OC-48, PRBS 223 - 1, RTHRADJ = 500 OC-48, PRBS 223 - 1, RTHRADJ = 1M
TBD TBD TBD TBD
DC-coupled DC-coupled
mA/mA nA V V mA C V p-p ps V V nA nA
TMIN to TMAX Single-ended Differential 20% to 80%
600
800 100
2.0 0.8 -100 100
Rev. PrA | Page 3 of 12
IINH, VIN = 2.4 V IINL, VIN = 0.4 V
ADN2891
Parameter LOGIC OUTPUTS (LOS) VOH, Output High Voltage VOL, Output Low Voltage Min 2.4 0.4 Typ Max Unit V V
PRELIMINARY TECHNICAL DATA
Test Conditions/Comments Open drain output, 4.7 k - 10 k pull-up resistor to VCC Open drain output, 4.7 k - 10 k pull-up resistor to VCC
Rev. PrA | Page 4 of 12
PRELIMINARY TECHNICAL DATA ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage Minimum Input Voltage (All Inputs) Maximum Input Voltage (All Inputs) Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering 10 s) Junction Temperature Rating 4.2 V VEE - 0.4 V VCC + 0.4 V -65C to +155C -40C to +95C 300C 125C
ADN2891
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
JA is specified for 4-layer PCB with exposed paddle soldered to GND. Table 3.
Package Type 16-lead 3 mm x 3 mm LFCSP JA 28 Unit C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrA | Page 5 of 12
ADN2891 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PD _CAT H OD E PD _VCC RSSI _OU T SQU EL CH
PRELIMINARY TECHNICAL DATA
16 15 14 13
AVCC PIN N IN AVEE
1 2 AD N2891 T OP VI EW 3 (N ot to Scale) 4
T H RAD J 5 CAZ1 6 CAZ2 7 L OS 8
12 11 10 9
D RVCC OU T P OU T N D RVEE
Figure 2. Pin Configuration
Note: There is an exposed pad on the bottom of the package that must be connected to the GND plane with filled vias.
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Exposed Pad Mnemonic AVCC PIN NIN AVEE THRADJ CAZ1 CAZ2 LOS DRVEE OUTN OUTP DRVCC SQUELCH RSSI_OUT PD_VCC PD_CATHODE Pad I/O Power Input Input Power Input Description Analog Power Differential Data Input Differential Data Input Analog Ground LOS Threshold Adjust Resistor Offset Correction Loop Capacitor Offset Correction Loop Capacitor LOS Detector Output Output Buffer Ground Differential Data Output Differential Data Output Output Buffer Power Disable Outputs Average Current Output Power Input for RSSI Measurement Photodiode Bias Voltage Connect to Ground
Output Power Output Output Power Input Output Power Output Power
Rev. PrA | Page 6 of 12
PRELIMINARY TECHNICAL DATA TYPICAL PERFORMANCE CHARACTERISTICS
0.96 0.88 0.80 0.72
RSSI_OUT (mA)
ADN2891
VERTICAL SCALE: 100mV/DIV
0.64 0.56 0.48 0.40 0.32 0.24
04509-0-002
0.16 0.08 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
RSSI_IN (mA)
Figure 3. RSSI Output vs. Average PIN Photodiode Current
Figure 6. Eye Diagram at 3.2 Gb/s
LOS Trip Point -vs- RTHRADJ 50 40 30 20 10 0 10 100 1000 ohm s 10000 100000
VERTICAL SCALE: 100mV/DIV
mV
Figure 4. LOS Trip Point vs. Threshold Adjust Resistor
Figure 7. Eye Diagram at 2.488 Gb/s
70 60 50 40 30 20 10 0 100k
SUPPLY-NOISE REJECTION (dB)
1M SUPPLY-NOISE FREQUENCY (Hz)
10M
Figure 5. Typical PSRR vs. Supply-Noise Frequency
04509-0-010
Rev. PrA | Page 7 of 12
04509-0-021
04509-0-020
ADN2891 THEORY OF OPERATION
LIMAMP
Input Buffer
The ADN2891 limiting amplifier has differential inputs (PIN/NIN), with an internal 50 termination. The amplifier input supports DC- or AC-coupled to TIAs. In real applications, the ROSA (receive optical sub-assembly) is typically ACcoupled to the amplifier inputs because if DC-coupled, TIA output offset degrades receiver performance. The ADN2891 limiting amplifier is a high gain device. It is susceptible to DC offsets in the signal path. The pulse-width distortion present in a 50% duty cycle NRZ data or distortion generated from TIA appears as a DC offset to the inputs. An internal offset correction loop requires that a capacitor be connected between the CAZ1 and CAZ2 pins. For GbE and FC applications, no external capacitor is necessary, but for SONET applications, a 0.01 F capacitor provides the data path a lower 3dB frequency cutoff of 1 kHz.
PRELIMINARY TECHNICAL DATA
RECEIVED SIGNAL STRENGTH INDICATOR (RSSI)
The ADN2891 has an on-chip RSSI circuit. With a photodiode biased directly by the ADN2891, a very accurate, on-chip, average power measurement is available via the RSSI circuit by monitoring the current supplied to the photodiode. The output of the RSSI is a current that is directly proportional to the average amount of PIN photodiode current. Placing a resistor between the RSSI_OUT pin and GND converts the current to a GND referenced voltage. This function eliminates the need for external RSSI circuitry in SFF-8472 compliant optical receivers.
SQUELCH MODE
Driving the SQUELCH input to a logic high disables the limiting amplifier outputs. The SQUELCH input can be connected to the LOS output to keep the limiting amplifier outputs at a static voltage level anytime the input level to the limiting amplifier drops below the programmed LOS threshold.
CML Output Buffer
The ADN2891 provides CML outputs, OUTP/OUTN. The outputs are internally terminated with 50 to VCC. The outputs can be kept at a static voltage by driving the SQUELCH pin to a logic high. The SQUELCH pin can be driven directly by the LOS pin, which automatically disables the amplifer outputs in situations when the input signal level drops below the programmed LOS threshold.
LOSS OF SIGNAL (LOS) DETECTOR
The receiver front-end LOS detector circuit indicates when the input signal level has fallen below the user-adjustable threshold. The threshold level can be set to anywhere from 2mVpp to 40mVpp, typically, and is set by a resistor connected between the THRADJ pin and VEE. See Figure 4 for a plot of LOS Threshold -vs- THRADJ. The ADN2891 LOS circuit has a trip point down to <3.0 mV with >3 dB electrical hysteresis to prevent chatter at the LOS output. The LOS output is an opencollector output that must be pulled up externally with a 4.7 k to 10 k resistor.
Rev. PrA | Page 8 of 12
PRELIMINARY TECHNICAL DATA APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Generic RF PCB design technique applies with special consideration implemented for the optimal performance.
ADN2891
schematic in Figure 8 for the connection recommendation.
Output Buffer Power Supply and Ground Planes
Pin 9 and 12 are the power supply and ground pins to provide current to differential OUTP and OUTN pins. To reduce any possible serial inductance, pin 9, which is the ground return of the output buffer, should connect to ground directly. If the ground plane is an internal plane and connections to the ground plane are vias, multiple vias in parallel to the ground can reduce the series inductance.. Similarly, to reduce the possible series inductance, pin 12, which supplies power to the high-speed differential OUTP/OUTN output buffer, should connect to power plane directly. If the power plane is an internal plane and connections to the power plane are vias, multiple vias in parallel can reduce the series inductance, especially on Pin 12. Please refer to the
The exposed pad should be connected to the GND plane using filled vias so that solder does not leak through the vias during reflow. Using filled vias in parallel under the package greatly reduce the thermal resistance and enhances the reliability of the connectivity of the exposed pad to the GND plane during reflow. To reduce power noise, a 10 F electrolytic decoupling capacitor between VCC and VEE is at the location where the 3.3 V supply enters the PCB. The other 0.1 F and 1 nF ceramic chip decoupling capacitors should be as close as possible to the ADN2891 VCC and VEE pins to reduce any possible current return loop.
VCC C9 PD_CATHODE VCC 0.1F VCC C5 C6 AVCC C1 PIN NIN AVEE
1 2 3 4 5 6 7 8
RSSI_OUT
SQUELCH
200
PD_VCC
R1
C10
RSSI MEASUREMENT TO ADC
VCC C7
12
16
15
14
13
C8
DRVCC OUTP C3 TO HOST BOARD
ADN2880
C2
CONNECT EXPOSED PAD TO GND
11 10 9
OUTN C4 DRVEE
CAZ1
THRADJ
CAZ2
LOS
C1-C4, C11: 0.01F X5R/X7R DIELECTRIC, 0201 CASE C5, C7, C9, C10, C12: 0.1F X5R/X7R DIELECTRIC, 0402 CASE C6, C8: 1nF X5R/X7R DIELECTRIC, 0201 CASE R3 4.7k TO 10k ON HOST BOARD
C11 C12 R2
VCC
Figure 8. Typical ADN2891 Applications Circuit
Rev. PrA | Page 9 of 12
04509-0-007
ADN2891
PCB Layout
Figure 9 shows a recommended PC board layout. The 50 transmission lines are the traces to bring the high frequency input and output signals: PIN, NIN, OUTP and OUTN to the SMA connectors with minimum reflections. To avoid a signal skew between the differential traces, each differential PIN/NIN pair and the differential OUTP/OUTN pair should have their matched trace length to the SMA connectors. C1, C2, C3, and C4 are ac-coupling capacitors in series with the high speed I/O. To minimize the possible mismatch , the AC coupling capacitor pad should be the same width as that of the 50 transmission line. The transmission lines should be in same width, on same signal plate, no layer changes, run from the high speed pads directly to SMA connectors. For supply decoupling, the 1 nF decoupling capacitor should be placed on the same layer as the ADN2891 as close as possible to the VCC pin. The 0.1 F capacitor can be placed on the bottom of the PCB directly underneath the 1 nF decoupling capacitor. All high speed CML
PRELIMINARY TECHNICAL DATA
outputs have on chip, 50 resistors terminated between the output pin and VCC. The high speed inputs, PIN and NIN, also have the internally 50 terminated to an internal reference voltage. As with any high speed mixed-signal design, make sure to keep all high speed digital traces away from sensitive analog nodes.
Soldering Guidelines for Chip Scale Package
The lands on the 16 LFCSP are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a central exposed pad. The pad on the printed circuit board should be at least as large as this exposed pad. The user must connect the exposed pad to VEE using filled vias so that solder does not leak through the vias during reflow. This ensures a solid connection from the exposed pad to VEE.
R1, C9, C10 ON BOTTOM TO ROSA DOUBLE-VIAS TO REDUCE INDUCTANCE TO SUPPLY AND GND PLACE C7 ON BOTTOM OF BOARD UNDERNEATH C8 C8 VIAS TO GND NIN C2 C4 OUTN C3 OUTP
PLACE C5 ON BOTTOM OF BOARD UNDERNEATH C6 C1 PIN C6
1
EXPOSED PAD
4mm
DOUBLE-VIA TO GND TO REDUCE INDUCTANCE
04509-0-008
VIA TO C12, R2 ON BOTTOM C11 VIA TO BOTTOM
Figure 9. Recommended ADN2891 PCB Layout (TOP VIEW)
Rev. PrA | Page 10 of 12
PRELIMINARY TECHNICAL DATA OUTLINE DIMENSIONS
0.50 0.40 0.30 PIN 1 INDICATOR
16 1
ADN2891
3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 12 MAX 1.00 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF
0.60 MAX
13 12
BOTTOM VIEW
1.65 1.50 SQ* 1.35
9
8
5
4
0.25 MIN
1.50 REF
* COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION
Figure 10. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm x 3 mm Body (CP-16-3) Dimensions shown in millimeters
ORDERING GUIDE
Model ADN2891ACP ADN2891ACP-RL ADN2891ACP-RL7 Temperature Range -40C to +95C -40C to +95C -40C to +95C Package Description 16-LFCSP 16-LFCSP 16-LFCSP Package Option CP-16-3 CP-16-3 CP-16-3 Branding F02 F02 F02
Rev. PrA | Page 11 of 12
ADN2891 NOTES
PRELIMINARY TECHNICAL DATA
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
PR05244-0-11/04(PrA)
Rev. PrA | Page 12 of 12
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