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FET Drive Simple Sequencers(R) ADM6819/ADM6820
FEATURES
Single chip enables power supply sequencing of two supplies On-board charge pump fully enhances N-channel FET Adjustable primary supply monitor to 0.618 V Delay from primary supply to secondary supply enabled Fixed 300 ms delay (ADM6819) Capacitor adjustable delay (ADM6820) Logic/analog driven enable input (ADM6819) -40C to +85C operating range Packaged in small 6-lead SOT-23 package Pin-to-pin compatibility with MAX6819/MAX6820
VCC1 VCC2 VCC1 VCC2 CHARGE PUMP UVLO R1 SETV 0.618V LOGIC FET DRIVER GATE VFET
FUNCTIONAL BLOCK DIAGRAM
Q1 VCC1 VCC2 OUT
R2
TIMER
ADM6819/ ADM6820
0.618V
Multivoltage systems Dual voltage microprocessors/FPGAs/ASICs/DSPs Network processors Telecom and datacom systems PC/server applications
EN (ADM6819) - DIGITAL/ANALOG SETD (ADM6820)
Figure 1.
GENERAL DESCRIPTION
The ADM6819 and ADM6820 are simple power supply sequencers with FET drive capability for enhancing N-channel MOSFETs. These devices can monitor a primary supply voltage and enable/disable an external N-channel FET for a secondary supply. The ADM6819 has the ability to monitor two supplies. When more than two voltages require sequencing, multiple ADM6819/ADM6820 devices can be cascaded to achieve this. The devices operate over a supply range of 2.95 V to 5.5 V. An internal comparator monitors the primary supply using the VSET pin. The input to this comparator is externally set via a resistor divider from the primary supply. When the voltage at the VSET pin rises above the comparator threshold, an internal charge pump on the GATE output enhances the secondary supply FET. The ADM6819 features an enable (EN) pin that is fed to the input of an additional comparator and reference circuit. This pin can be used as a digital enable or a secondary power good comparator to monitor a second supply and enables the GATE only if both supplies are valid. When both inputs of the internal comparators are above the threshold, a fixed 300 ms timeout occurs before the GATE is driven high and the secondary supply is enabled. The ADM6820 has only one comparator that is on the SETV pin. It also features a timeout period that is adjustable via a single external capacitor on the SETD pin. The ADM6819/ADM6820 are packaged in small 6-lead SOT-23 packages.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
05133-001
APPLICATIONS
GND
ADM6819/ADM6820 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Diagrams.............................................................................. 4 Absolute Maximum Ratings............................................................ 6 Thermal Characteristics .............................................................. 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions..............................7 Typical Performance Characteristics ..............................................8 Theory of Operation ...................................................................... 10 SETV Pin ..................................................................................... 10 EN Pin.......................................................................................... 10 GATE Pin .................................................................................... 10 SETD Pin ..................................................................................... 10 Outline Dimensions ....................................................................... 11 Ordering Guide .......................................................................... 11
REVISION HISTORY
7/06--Rev. 0: Initial Version
Rev. 0 | Page 2 of 12
ADM6819/ADM6820 SPECIFICATIONS
VCC1 or VCC2 = 2.95 V to 5.5 V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = 25C. 1 Table 1.
Parameter VCC1, VCC2 PINS Operating Voltage Range, VCC1 or VCC2 VCC1 or VCC2 Supply Current, ICC VCC1 or VCC2 Disable Mode Current VCC1 or VCC2 Slew Rate 2 Undervoltage Lockout, VUVLO SETV PIN SETV Threshold, VTH SETV Input Current2 SETV Threshold Hysteresis SETV to GATE Delay, tDELAY SETD PIN SETD Ramp Current, ISETD SETD Voltage, VSETD GATE PIN GATE Turn-On Time, tON GATE Turn-Off Time, tOFF GATE Voltage, VGATE Min 0.9 350 250 6 1.2/tDELAY 2.4 0.602 Typ Max 5.5 500 Units V A A V/s V/s V V nA % ms nA nA V ms s V V V V V V Conditions VCC1 or VCC2 must be > 2.95 V VCC1 or VCC2 must be > 2.95 V VCC1 = VCC2 = 3.3 V VCC1 = VCC2 = 3.3 V, EN = GND ADM6819 ADM6820 3 VCC falling VSETV rising, enables GATE VSETV falling, disables GATE VSETV > VTH ; VEN > VTH (ADM6819) ADM6820 TA = 25C
2.525 0.618 10 -1 300 500 500 1.326 1.5 30 5.5 5.0 9.4 8.6
2.65 0.634 100 350 730 600 1.357 10 6.0 6 9.9 9.1 0.4
240 300 400 1.295 0.5 4.5 4.0 8.9 8.2
CGATE = 1500 pF, VCC2 = 3.3 V, VGATE = 7.8 V CGATE = 1500 pF, VCC2 = 3.3 V, VGATE = 0.5 V With respect to VCCx, RGATE > 50 M to VCCx 4 With respect to VCCx, RGATE > 5 M to VCCx4 With respect to VCCx, RGATE > 50 M to VCCx 5 With respect to VCCx, RGATE > 5 M to VCCx5 VCC1 or VCC2 must be > 2.95 V VCC1 or VCC2 must be > 2.95 V
ENABLE PIN EN Input Voltage Low, VIL EN Input Voltage High, VIH
1 2
2.0
100% production tested at TA = +25C. Specifications over temperature limit are guaranteed by design. Guaranteed by design, not production tested. 3 tDELAY (s) = 2.65 x 106 x CSET. 4 Highest supply pin is represented by VCCx = 2.95 V. 5 Highest supply pin is represented by VCCx = 5.5 V.
Rev. 0 | Page 3 of 12
ADM6819/ADM6820 TIMING DIAGRAMS
VCC1 VCC2 VCC1 VCC2 CHARGE PUMP UVLO R1 R3 SETV 0.618V LOGIC FET DRIVER GATE VFET Q1 VCC1 VCC2 OUT
R2 R4
ADM6819
GND
0.618V
Figure 2. ADM6819 Solution for Validating Two Supplies Before Sequencing
VSETV
0.618V
tON
90%
VCC2 + 5.5V (typ)
VGATE
10%
10%
(ADM6819 = 300ms, ADM6820 = ADJ)
Figure 3. ADM6819/ADM6820 Timing Diagram Using SETV for Sequencing
VSETV VEN
0.618V
0.618V
tON
90%
VCC2 + 5.5V (typ)
VGATE
10%
10%
05133-016
tDELAY
(300ms)
tOFF
Figure 4. ADM6819 Timing Diagram Using EN and SETV for Sequencing
Rev. 0 | Page 4 of 12
05133-015
tDELAY
tOFF
05133-014
EN
ADM6819/ADM6820
VIN = 5V VIN = 3.3V VIN = 3.0V VOUT = 5V Q2 VOUT = 3.3V VOUT = 3.0V
Q1
VCC2 GATE VCC1 R1
VCC2 GATE VCC1 R3
ADM6819/ ADM6820
SETV EN/SETD GND
ADM6819/ ADM6820
SETV EN/SETD GND
05133-017
R2
R4
Figure 5. ADM6819/ADM6820 Solution for Sequencing Three Supply Rails
Rev. 0 | Page 5 of 12
ADM6819/ADM6820 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter VCC1, VCC2 SETV, SETD, EN GATE Storage Temperature Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Rating -0.3 V to +6.0 V -0.3 V to +30 V -0.3 V to (VCCx + 11 V) -65C to +150C -40C to +85C 300C 150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance
Package Type 6-Lead SOT-23 JA 169.5 Unit C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 6 of 12
ADM6819/ADM6820 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VCC1 1
6
VCC2
VCC1 1
6
VCC2
ADM6819
GND 2 SETV 3
05133-002
ADM6820
GND 2 SETV 3
05133-003
TOP VIEW 5 GATE (Not to Scale)
4
TOP VIEW 5 GATE (Not to Scale)
4
EN
SETD
Figure 6. ADM6819 Pin Configuration
Figure 7. ADM6820 Pin Configuration
Table 4. Pin Function Descriptions
Pin Number ADM6819 ADM6820 1 1 2 3 4 2 3 - Mnemonic VCC1 GND SETV EN Description Supply Voltage 1. Either VCC1 or VCC2 must be greater than the UVLO to enable external FET Drive. Chip Ground Pin. Sequenced Threshold Set. Connect to an external resistor divider to set the VCC1 threshold that enables GATE turn-on. The internal reference is 0.618 V. Active-High Enable. GATE drive is enabled tDELAY after EN is driven high. GATE drive is immediately disabled when EN is driven low. Connect this pin to the higher of VCC1 or VCC2 if not used. EN is internally identical to SETV (0.618 V threshold) and, therefore, can be used as a second supply monitor, enabling two supplies to be validated before sequencing begins. GATE Delay Set Input. Connect an external capacitor from SETD to GND to adjust the delay from SETV > VTH to GATE turn-on. tDELAY(s) = 2.652 x 106 x CSET(F). GATE Drive Output. GATE drives an external N-channel FET to connect VCC2 to the load. GATE drive enables tDELAY after SETV exceeds VTH and ENABLE is driven high. GATE drive is immediately disabled when SETV drops below VTH or ENABLE is driven low. When enabled, an internal charge pump drives GATE above VCCX to fully enhance the external N-channel FET. Supply Voltage 2. Either VCC1 or VCC2 must be greater than the UVLO to enable the external FET Drive.
- 5
4 5
SETD GATE
6
6
VCC2
Rev. 0 | Page 7 of 12
ADM6819/ADM6820 TYPICAL PERFORMANCE CHARACTERISTICS
0.50 0.45 ICC2 (VCC1 = 3.3V, VCC2 = 5V) 0.40 0.35 0.30 0.25 0.20 0.15 0.10 -50 ICC1 (VCC1 = 5V, VCC2 = 3.3V) 0.65 0.64
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
0.63
0.62 0.61
0.60 0.59
VEN = 2V VSETV = 2V
05133-004
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
TEMPERATURE (C)
TEMPERATURE (C)
Figure 8. Supply Current vs. Temperature
0.50 0.45 0.40 0.35
ICC2 (mA)
VGATE (V)
Figure 11. Supply Current vs. Temperature
14 12 10 8 6 4 2 VCC1 = 3.3V VEN = 2V VSETV = VCC2 0 1 2 3 VCC2 (V) 4 5 6
05133-008 05133-009
VCC1 = 0V VEN = 2V VSETV = 2V
0.30 0.25 0.20 0.15 0.10 0.05 0 1 2 3 4 5 6 7
05133-005
0 VCC2 (V)
0
Figure 9. ICC2 vs. VCC2
0.50 0.45 0.40 0.35
ICC2 (mA)
Figure 12. VGATE vs. VCC2
14 12 10
VGATE (V)
VCC1 = 3.3V VEN = 2V VSETV = 2V
0.30 0.25 0.20 0.15 0.10 0.05 0 1 2 3 4 5 6 7
05133-006
8 6 4 2 0 0 1 2 3 VCC2 (V) 4 5 6 VCC1 = 0V VEN = 2V VSETV = 1V
0 VCC2 (V)
Figure 10. ICC2 vs. VCC2
Figure 13. VGATE vs. VCC2
Rev. 0 | Page 8 of 12
05133-007
0.58 -50
ADM6819/ADM6820
14 12
VSETV
10
VGATE (V)
8 6 4 2 0 0 1 2 3 VCC2 (V) 4 5 6 VCC1 = 3.3V VEN = 2V VSETV = 1V
05133-010
VGATE 5V/DIV
20s/DIV
Figure 14. VGATE vs. VCC2
340 330 320 310
Figure 16. Gate Turn-Off Time
tDELAY (ms)
300 290 280 270 260 250 -25 0 25 50 75 100 125 150
05133-011
VGATE 5V/DIV
240 -50
1ms/DIV
TEMPERATURE (C)
Figure 15. tDELAY vs. Temperature
Figure 17. Gate Turn-On Time
Rev. 0 | Page 9 of 12
05133-019
CLOAD = 1500pF
05133-018
CLOAD = 1500pF
ADM6819/ADM6820 THEORY OF OPERATION
The ADM6819/ADM6820 provide local voltage sequencing in multisupply systems. Figure 18 and Figure 19 show typical application diagrams for these devices.
VIN = 3.3V VIN = 3.0V Q1 VOUT = 3.3V VOUT = 3.0V
SETV PIN
The ADM6819/ADM6820 enable a supply after a monitored supply voltage exceeds a programmed threshold. This threshold is programmed by a R1/R2 resistor divider on the SETV pin. Once the voltage on SETV exceeds the 0.618 V threshold, the FET switches on after the delay timer expires. On the ADM6820, this delay is programmable using a capacitor on the SETD pin. On the ADM6819, this delay is fixed at 300 ms and the EN pin must be valid high to begin the timer. The required turn-on voltage is calculated by the following equation: R1 = R2 ((VTRIP/VTH) - 1) where: VTRIP is the minimum turn-on voltage at the supply being monitored. VTH = 0.618 V. High value resistors can be used because the SETV input current is typically 10 nA.
VCC2 GATE VCC1 R1
ADM6819
ON SETV GND
05133-012
EN
OFF
R2
Figure 18. ADM6819 Applications Diagram
VIN = 3.3V VIN = 3.0V Q1 VOUT = 3.3V VOUT = 3.0V
VCC2 GATE VCC1 R1
EN PIN
The ADM6819 has an enable (EN) pin connected to the input of a second comparator, which is identical to that on the VSET pin. EN can be used as a digital input provided the signal VOL is below 0.6 V. Alternatively, the enable input can be used to validate a second supply. The fixed 300 ms timer does not begin counting until both SETV and EN are above the threshold. As a result, the output is not enabled until this timer has expired.
ADM6820
SETV GND
05133-013
SETD CSET
R2
Figure 19. ADM6820 Applications Diagram
When the primary supply is above the desired threshold, the ADM6819/ADM6820 are designed to control the N-channel FET in the secondary power path to enable the secondary supply. The GATE pin is held low while both VCC1 and VCC2 are below the undervoltage threshold, ensuring that the FET is held off. When VCC1 or VCC2 is above UVLO and the primary supply is above the desired level dictated by the resistor divider to the VSET pin, the external FET is driven on after the delay has expired. An internal charge pump enhances the external FET. A FET with a low drain-source resistance and low VTH should be chosen to reduce voltage drop across the drain-source when the FET is fully enhanced. Either supply may act as the primary source if VCC1 or VCC2 is greater that 2.95 V. A decoupling capacitor of typically 100 nF should be used on whichever VCC is the main supply.
GATE PIN
The internal charge pump is capable of driving the gate of an N-channel MOSFET with no external capacitors. This ensures that the MOSFET is enhanced to provide a minimum voltage drop across the MOSFET, thus reducing the voltage drop across the FET. This charge pump is designed to drive the high impedance capacitive load of a MOSFET gate input. The GATE pin should not be resistively loaded because it reduces the gate drive capability. During undervoltage lockout, GATE is held to GND.
SETD PIN
The ADM6820 features a capacitor adjustable sequencing delay. A capacitor connected to the SETD pin determines the length of the sequencing delay. The sequencing delay can be calculated by the following equation: tDELAY (s) = 2.652 x 106 x CSET The ADM6819 has a fixed 300 ms delay.
Rev. 0 | Page 10 of 12
ADM6819/ADM6820 OUTLINE DIMENSIONS
2.90 BSC
6
5
4
1.60 BSC
1 2 3
2.80 BSC
PIN 1 INDICATOR 0.95 BSC 1.30 1.15 0.90 1.90 BSC
1.45 MAX
0.22 0.08 10 4 0 0.60 0.45 0.30
0.15 MAX
0.50 0.30
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 20. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters
ORDERING GUIDE
Model ADM6819ARJZ-REEL7 1 ADM6820ARJZ-REEL71
1
Temperature Range -40C to +85C -40C to +85C
Package Description 6-Lead Small Outline Transistor Package [SOT-23] 6-Lead Small Outline Transistor Package [SOT-23]
Package Option RJ-6 RJ-6
Branding M2R M2S
Z = Pb-free part.
Rev. 0 | Page 11 of 12
ADM6819/ADM6820 NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05113-0-7/06(0)
Rev. 0 | Page 12 of 12

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