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ISL9005A
Data Sheet March 14, 2007 FN6452.0
LDO with Low ISUPPLY, High PSRR
ISL9005A is a high performance Low Dropout linear regulator capable of sourcing 300mA current. It has a low standby current and high-PSRR and is stable with output capacitance of 1F to 10F with ESR of up to 200m. The ISL9005A has a high PSRR of 75dB and output noise less than 45VRMS. When coupled with a no load quiescent current of 50A (typical) and 0.1A shutdown current, the ISL9005A is an ideal choice for portable wireless equipment. Several different fixed voltage outputs are standard. Other output voltage options for the LDO may be available on request and range from 1.35V to 3.6V.
Features
* 300mA high performance LDO * Excellent transient response to large current steps * Excellent load regulation: <0.1% voltage change across full range of load current * High PSRR: 75dB @ 1kHz * Wide input voltage capability: 2.3V to 6.5V * Very low quiescent current: 50A * Low dropout voltage: typically 200mV @ 300mA * Low output noise: typically 45VRMS @ 100A (1.5V) * Stable with 1F to 10F ceramic capacitors
Pinout
ISL9005A (8 LD DFN 2x3) TOP VIEW
VIN EN NC NC 1 2 3 4 8 VO 7 NC 6 NC 5 GND
* Soft-start to limit input current surge during enable * Current limit and overheat protection * 1.8% accuracy over all operating conditions * Tiny 2mmx3mm 8 Ld DFN package * -40C to +85C operating temperature range * Pb-free plus anneal available (RoHS compliant)
Applications
* PDAs, cell phones and smart phones * Portable instruments, MP3 players * Handheld devices including medical handhelds
Ordering Information
PART NUMBER (Note 1) ISL9005AIRNZ-T ISL9005AIRMZ-T ISL9005AIRLZ-T ISL9005AIRKZ-T ISL9005AIRJZ-T ISL9005AIRRZ-T ISL9005AIRFZ-T ISL9005AIRCZ-T ISL9005AIRBZ-T NOTES: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. For other output voltages, contact Intersil Marketing. PART MARKING EBV EBT EBS EBR EBP EBW EBN EBM EBL VO VOLTAGE (V) (Note 2) 3.3 3.0 2.9 2.85 2.8 2.6 2.5 1.8 1.5 TEMP RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-Free) 8 Ld DFN 2x3 Tape and Reel 8 Ld DFN 2x3 Tape and Reel 8 Ld DFN 2x3 Tape and Reel 8 Ld DFN 2x3 Tape and Reel 8 Ld DFN 2x3 Tape and Reel 8 Ld DFN 2x3 Tape and Reel 8 Ld DFN 2x3 Tape and Reel 8 Ld DFN 2x3 Tape and Reel 8 Ld DFN 2x3 Tape and Reel PKG. DWG. # L8.2x3 L8.2x3 L8.2x3 L8.2x3 L8.2x3 L8.2x3 L8.2x3 L8.2x3 L8.2x3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL9005A
Absolute Maximum Ratings
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3)V ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2500V Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .200V
Thermal Information
Thermal Resistance (Notes 3, 4) JA (C/W) JC (C/W) 8 Ld DFN 2x3 Package . . . . . . . . . . . . 69 10 Junction Temperature Range . . . . . . . . . . . . . . . . .-40C to +125C Operating Temperature Range . . . . . . . . . . . . . . . . .-40C to +85C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300C
Recommended Operating Conditions
Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40C to +85C Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 6.5V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 4. JC, "case temperature" location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40C to +85C; VIN = (VO + 0.5V) to 5.5V with a minimum VIN of 2.3V; CIN = 1F; CO = 1F SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER DC CHARACTERISTICS Supply Voltage Ground Current
VIN Quiescent condition: IO = 0A IDD LDO active LDO disabled @ +25C
2.3
6.5
V
50 0.1 1.9 1.6 2.1 1.8
75 1.0 2.3 2.0 +0.7 +0.8 +1.8
A A V V % % % mA
Shutdown Current UVLO Threshold
IDDS VUV+ VUV-
Regulation Voltage Accuracy
Initial accuracy at VIN = VO + 0.5V, IO = 10mA, TJ = +25C VIN = VO + 0.5V to 5.5V, IO = 10A to 300mA, TJ = +25C VIN = VO + 0.5V to 5.5V, IO = 10A to 300mA, TJ = -40C to +125C
-0.7 -0.8 -1.8 300 350 475 300 250 200 145 110
Maximum Output Current Internal Current Limit Dropout Voltage (Note 6)
IMAX ILIM VDO1 VDO2 VDO3
Continuous
600 500 400 325
mA mV mV mV C C
IO = 300mA; VO < 2.5V IO = 300mA; 2.5V VO 2.8V IO = 300mA; VO > 2.8V
Thermal Shutdown Temperature
TSD+ TSD-
AC CHARACTERISTICS Ripple Rejection (Note 5) IO = 10mA, VIN = 2.8V (min), VO = 1.8V @ 1kHz @ 10kHz @ 100kHz Output Noise Voltage (Note 5) IO = 100A, VO = 1.5V, TA = +25C BW = 10Hz to 100kHz 75 60 40 45 dB dB dB VRMS
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FN6452.0 March 14, 2007
ISL9005A
Electrical Specifications
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40C to +85C; VIN = (VO + 0.5V) to 5.5V with a minimum VIN of 2.3V; CIN = 1F; CO = 1F (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER
DEVICE START-UP CHARACTERISTICS Device Enable TIme LDO Soft-start Ramp Rate EN PIN CHARACTERISTICS Input Low Voltage Input High Voltage Input Leakage Current Pin Capacitance NOTES: 5. Guaranteed by characterization. 6. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.85V. VIL VIH IIL, IIH CPIN Informative 5 -0.3 1.4 0.5 VIN + 0.3 0.1 V V A pF tEN tSSR Time from assertion of the ENx pin to when the output voltage reaches 95% of the VO (nom) Slope of linear portion of LDO output voltage ramp during start-up 250 30 500 60 s s/V
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FN6452.0 March 14, 2007
ISL9005A Typical Performance Curves
0.8 0.6 OUTPUT VOLTAGE, VO (%) 0.4 0.2 -40C 0.0 +25C -0.2 -0.4 -0.6 -0.8 3.4 3.8 4.2 4.6 5.0 5.4 5.8 6.2 6.6 INPUT VOLTAGE (V) +85C VO = 3.3V ILOAD = 0mA OUTPUT VOLTAGE CHANGE (%) 0.10 0.08 0.06 0.04 0.02 0.00 -0.02 +85C -0.04 -0.06 -0.08 -0.10 0 50 100 150 200 250 300 350 400 +25C -40C VIN = 3.8V VO = 3.3V
LOAD CURRENT - IO (mA)
FIGURE 1. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT)
0.10 0.08 OUTPUT VOLTAGE CHANGE (%) 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 -40 VIN = 3.8V VO = 3.3V ILOAD = 0mA
FIGURE 2. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT
3.4 VO = 3.3V 3.3 OUTPUT VOLTAGE, VO (V) IO = 0mA
3.2 IO = 150mA 3.1 IO = 300mA 3.0
2.9
2.8 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 3.1 3.6 4.1 4.6 5.1 5.6 6.1 6.5 INPUT VOLTAGE (V)
FIGURE 3. OUTPUT VOLTAGE CHANGE vs TEMPERATURE
FIGURE 4. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT)
350 300 250 VO = 2.8V 200 VO = 3.3V 150 100 50 0
2.9 IO = 0mA
VO = 2.8V DROPOUT VOLTAGE, VDO (mV) 4.6 5.1 5.6 6.1 6.5
2.8 OUTPUT VOLTAGE, VO (V)
2.7
IO = 150mA
2.6 IO = 300mA 2.5
2.4
2.3 2.6
3.1
3.6
4.1
0
50
100
INPUT VOLTAGE (V)
150 200 250 OUTPUT LOAD (mA)
300
350
400
FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE (2.8V OUTPUT)
FIGURE 6. DROPOUT VOLTAGE vs LOAD CURRENT
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FN6452.0 March 14, 2007
ISL9005A Typical Performance Curves
350 VO = 3.3V 300 DROPOUT VOLTAGE, VDO (mV) 250 +85C 200 150 100 50 0 0 50 100 150 200 250 OUTPUT LOAD (mA) 300 350 400 +25C -40C GROUND CURRENT (A) 70 +125C 60 +25C 50 -40C 40 VO = 3.3V 30
(Continued)
80
20 3.0 3.5 4.0 4.58 5.0 5.5 6.0 6.5 INPUT VOLTAGE (V)
FIGURE 7. DROPOUT VOLTAGE vs LOAD CURRENT
FIGURE 8. GROUND CURRENT vs INPUT VOLTAGE
80
200 180 160 GROUND CURRENT (A) 140 120 100 -40C 80 60 40 20 0 0 50 100 150 200 250 300 VIN = 3.8V VO = 3.3V 350 400 +25C +85C GROUND CURRENT (A)
70
60
50
40
30
VIN = 3.8V VO = 3.3V ILOAD = 0A -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125
20 -40 -25
LOAD CURRENT (mA)
FIGURE 9. GROUND CURRENT vs LOAD
FIGURE 10. GROUND CURRENT vs TEMPERATURE
VO = 2.85V IL = 150mA 5 VOLTAGE (V) 4 3 2 1 0 VO VEN (V) VO (V) VIN 3 2 1 0 5 0
VIN = 5.0V VO = 2.85V
IL = 150mA
CL = 1F
0
0.5
1.0
1.5
2.0 2.5 TIME (s)
3.0
3.5
4.0
4.5
5.0
0
0.2
0.4
0.6
0.8
1.0 1.2 TIME (ms)
1.4
1.6
1.8
2.0
FIGURE 11. POWER-UP/POWER-DOWN
FIGURE 12. TURN ON/TURN OFF RESPONSE
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FN6452.0 March 14, 2007
ISL9005A Typical Performance Curves
(Continued)
VO = 3.3V ILOAD = 300mA CLOAD = 1F
VO = 2.8V ILOAD = 300mA CLOAD = 1F
4.3V 3.6V
4.2V 3.5V
10mV/DIV
10mV/DIV
400s/DIV
400s/DIV
FIGURE 13. LINE TRANSIENT RESPONSE, 3.3V OUTPUT
FIGURE 14. LINE TRANSIENT RESPONSE, 2.8V OUTPUT
10 SPECTRAL NOISE DENSITY (V/Hz)
1.000
VO (25mV/DIV)
VO = 1.8V VIN = 2.8V
0.100
VIN = 3.6V VO = 1.8V ILOAD = 10mA
300mA ILOAD 100A
0.010
CIN = 1F CLOAD = 1F
0.001 10 100s/DIV
100
1k 10k FREQUENCY (Hz)
100k
1M
FIGURE 15. LOAD TRANSIENT RESPONSE
FIGURE 16. SPECTRAL NOISE DENSITY vs FREQUENCY
100 90 80 70 PSRR (dB) 60 50 40 30 20 10 0 100 1k 10k FREQUENCY (Hz) 100k 1M VIN = 3.6V VO = 1.8V IO = 10mA CLOAD = 1F
FIGURE 17. PSRR vs FREQUENCY
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FN6452.0 March 14, 2007
ISL9005A Pin Description
PIN # 1 2 3 4 5 6 7 8 PIN NAME VIN EN NC NC GND NC NC VO DESCRIPTION Supply Voltage/LDO Input: Connect a 1F capacitor to GND. LDO Enable. Do not connect. Do not connect. GND is the connection to system ground. Connect to PCB Ground plane. Do not connect. Do not connect. LDO Output: Connect capacitor of value 1F to 10F to GND (1F recommended).
Typical Application
ISL9005A VIN (2.3V TO 5V) ENABLE OFF C1 1 ON 2 3 4 NC 8 VIN EN NC VO NC NC GND 7 6 5 C2 VOUT
C1, C2: 1F X5R CERAMIC CAPACITOR
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FN6452.0 March 14, 2007
ISL9005A Block Diagram
VIN
During operation, whenever the VIN voltage drops below about 1.84V, the ISL9005A immediately disables the LDO output. When VIN rises back above 2.1V, the device reinitiates its start-up sequence and LDO operation will resume automatically.
VO
UVLO
Reference Generation
SHORT CIRCUIT, THERMAL PROTECTION, SOFT-START
CONTROL LOGIC
The reference generation circuitry includes a trimmed bandgap, a trimmed voltage reference divider, a trimmed current reference generator, and an RC noise filter. The bandgap generates a zero temperature coefficient (TC) voltage for the reference divider. The reference divider provides the regulation reference and other voltage references required for current generation and overtemperature detection. The current generator outputs references required for adaptive biasing as well as references for LDO output current limit and thermal shutdown determination.
GND
EN
LDO Regulation and Programmable Output Divider
The LDO Regulator is implemented with a high-gain operational amplifier driving a PMOS pass transistor. The design of the ISL9005A provides a regulator that has low quiescent current, fast transient response, and overall stability across all operating and load current conditions. LDO stability is guaranteed for a 1F to 10F output capacitor that has a tolerance better than 20% and ESR less than 200m, and the design is performance-optimized for a 1F output capacitor. Unless limited by the application, use of an output capacitor value above 4.7F is not recommended as LDO performance improvement is minimal. Soft-start circuitry integrated into each LDO limits the initial ramp-up rate to about 30s/V to minimize current surge. The ISL9005A provides short-circuit protection by limiting the output current to about 425mA. The LDO uses an independently trimmed 1V reference as its input. An internal resistor divider drops the LDO output voltage down to 1V. This is compared to the 1V reference for regulation. The resistor division ratio is programmed in the factory.
BANDGAP AND TEMPERATURE SENSOR
VOLTAGE AND REFERENCE GENERATOR
1.0V 0.94V 0.9V
GND
Functional Description
The ISL9005A contains all circuitry required to implement a high performance LDO. High performance is achieved through a circuit that delivers fast transient response to varying load conditions. In a quiescent condition, the ISL9005A adjusts its biasing to achieve the lowest standby current consumption. The device also integrates current limit protection, smart thermal shutdown protection, and soft-start. Smart thermal shutdown protects the device against overheating.
Power Control
The ISL9005A has an enable pin, EN, to control power to the LDO output. When EN is low, the device is in shutdown mode. During this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.1A. When the enable pin is asserted, the device first monitors the output of the UVLO detector to ensure that VIN voltage is at least about 2.1V. Once verified, the device initiates a startup sequence. During the start-up sequence, trim settings are first read and latched. Then, sequentially, the bandgap, reference voltage and current generation circuitry power up. Once the references are stable, a fast-start circuit powers up the LDO.
Overheat Detection
The bandgap outputs a proportional-to-temperature current that is indicative of the temperature of the silicon. This current is compared with references to determine if the device is in danger of damage due to overheating. When the die temperature reaches about +140C, if the LDO is sourcing more than 50mA it shuts down until the die cools sufficiently. Once the die temperature falls back below about +110C, the disabled LDO is re-enabled and soft-start automatically takes place.
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FN6452.0 March 14, 2007
ISL9005A Dual Flat No-Lead Plastic Package (DFN)
2X 0.15 C A A D 2X 0.15 C B
L8.2x3
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A
E
MIN 0.80 -
NOMINAL 0.90 0.20 REF
MAX 1.00 0.05
NOTES -
A1 A3 b D
6 INDEX AREA B
0.20
0.25 2.00 BSC
0.32
5,8 -
TOP VIEW
D2 E
// 0.10 C
1.50
1.65 3.00 BSC
1.75
7,8 -
E2
A 0.08 C
1.65
1.80 0.50 BSC
1.90
7,8 -
e k L N 0.20 0.30
C SEATING PLANE
SIDE VIEW
A3
0.40 8 4
0.50
8 2 3 Rev. 0 6/04
D2 (DATUM B) 1 2 D2/2
7
8
Nd NOTES:
6 INDEX AREA (DATUM A)
NX k
1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D.
E2 E2/2
4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
NX L N N-1 NX b 8 e (Nd-1)Xe REF. BOTTOM VIEW (A1) NX (b) 5 SECTION "C-C" CC e FOR EVEN TERMINAL/SIDE TERMINAL TIP L C L 5 0.10 M C AB
7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 9
FN6452.0 March 14, 2007

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