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ISL2110, ISL2111
Data Sheet July 11, 2006 FN6295.1
100V, 3A/4A Peak, High Frequency Half-Bridge Drivers
The ISL2110, ISL2111 are 100V, high frequency, half-bridge N-channel power MOSFET driver ICs. They are based on the popular HIP2100, HIP2101 half-bridge drivers, but offer several performance improvements. Peak output pull-up/ pull-down current has been increased to 3A/4A, which significantly reduces switching power losses and eliminates the need for external totem-pole buffers in many applications. Also, the low end of the VDD operational supply range has been extended to 8VDC. The ISL2110 has additional input hysteresis for superior operation in noisy environments and the inputs of the ISL2111, like those of the ISL2110, can now safely swing to the VDD supply rail.
Features
* Drives N-Channel MOSFET Half-Bridge * SOIC and DFN Package Options * SOIC and DFN Packages Compliant with 100V Conductor Spacing Guidelines per IPC-2221 * Pb-Free Plus Anneal Available (RoHS Compliant) * Bootstrap Supply Max Voltage to 114VDC * On-Chip 1 Bootstrap Diode * Fast Propagation Times for Multi-MHz Circuits * Drives 1nF Load with Typical Rise/Fall Times of 9ns/7.5ns * CMOS Compatible Input Thresholds (ISL2110) * 3.3V/TTL Compatible Input Thresholds (ISL2111) * Independent Inputs Provide Flexibility
Ordering Information
PART NUMBER PART TEMP. (Notes 1, 2) MARKING RANGE (C) ISL2110ABZ 2110ABZ -40 to 125 -40 to 125 -40 to 125 -40 to 125 PACKAGE (Pb-Free) 8 Ld SOIC PKG. DWG. # M8.15
* No Start-Up Problems * Outputs Unaffected by Supply Glitches, HS Ringing Below Ground or HS Slewing at High dv/dt * Low Power Consumption * Wide Supply Voltage Range (8V to 14V) * Supply Undervoltage Protection * 1.6/1 Typical Output Pull-Up/Pull-Down Resistance
ISL2110AR4Z 2110AR4Z ISL2111ABZ 2111ABZ
12 Ld 4x4 DFN L12.4x4A 8 Ld SOIC M8.15
ISL2111AR4Z 2111AR4Z NOTES:
12 Ld 4x4 DFN L12.4x4A
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Add "-T" suffix for Tape and Reel packing option.
Applications
* Telecom Half-Bridge DC/DC Converters * Telecom Full-Bridge DC/DC Converters * Two-Switch Forward Converters * Active-Clamp Forward Converters * Class-D Audio Amplifiers
Pinouts
ISL2110, ISL2111 (SOIC) TOP VIEW
VDD HB HO HS 1 2 3 4 8 7 6 5 LO VSS LI NC HI HB HO HS 4 5 6 3 EPAD 9 8 7 NC LI HI
ISL2110, ISL2111 (DFN) TOP VIEW
VDD NC
1 2
12 LO 11 VSS 10 NC
NOTE: EPAD = Exposed PAD.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL2110, ISL2111 Application Block Diagram
+12V +100V
VDD HB
SECONDARY CIRCUIT
HI CONTROL PWM CONTROLLER LI
DRIVE HI
HO HS
DRIVE LO ISL2110 ISL2111 VSS
LO
REFERENCE AND ISOLATION
Functional Block Diagram
HB VDD UNDER VOLTAGE LEVEL SHIFT DRIVER HS HI ISL2111 HO
ISL2111 LI VSS
UNDER VOLTAGE DRIVER
LO
EPAD (DFN Package Only)
*EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For best thermal performance connect the EPAD to the PCB power ground plane.
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FN6295.1 July 11, 2006
ISL2110, ISL2111
+48V +12V
PWM
ISL2110 ISL2111
SECONDARY CIRCUIT
ISOLATION
FIGURE 1. TWO-SWITCH FORWARD CONVERTER
+48V +12V SECONDARY CIRCUIT
PWM
ISL2110 ISL2111
ISOLATION
FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE-CLAMP
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FN6295.1 July 11, 2006
ISL2110, ISL2111
Absolute Maximum Ratings
Supply Voltage, VDD, VHB - VHS (Notes 3, 4) . . . . . . . . -0.3V to 18V LI and HI Voltages (Note 4) . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V Voltage on LO (Note 4) . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V Voltage on HO (Note 4) . . . . . . . . . . . . . . VHS - 0.3V to VHB + 0.3V Voltage on HS (Continuous) (Note 4) . . . . . . . . . . . . . . -1V to 110V Voltage on HB (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V Average Current in VDD to HB Diode . . . . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) SOIC (Note 5) . . . . . . . . . . . . . . . . . . . 95 N/A DFN (Note 6) . . . . . . . . . . . . . . . . . . . . 40 3 Max Power Dissipation at 25C in Free Air (SOIC, Note 5) . . . . 1.3W Max Power Dissipation at 25C in Free Air (DFN, Note 6) . . . . . 3.1W Storage Temperature Range . . . . . . . . . . . . . . . . . . . -65C to 150C Junction Temperature Range. . . . . . . . . . . . . . . . . . . -55C to 150C Lead Temperature (Soldering 10s - SOIC Lead Tips Only) . . . 300C For recommended soldering conditions see Tech Brief TB389.
Maximum Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 14V Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V Voltage on HS . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V Voltage on HB . . VHS + 7V to VHS + 14V and VDD - 1V to VDD + 100V HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the recommended operating conditions of this specification is not implied.
NOTES: 3. The ISL2110 and ISL2111 are capable of derated operation at supply voltages exceeding 14V. Figure 22 shows the high-side voltage derating curve for this mode of operation. 4. All voltages referenced to VSS unless otherwise specified. 5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board. See Tech Brief TB379 for details. 6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. For JC, the "case temp" is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379 for details.
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified TJ = 25C TJ = -40C to 125C MAX MIN MAX UNITS
PARAMETERS SUPPLY CURRENTS VDD Quiescent Current VDD Quiescent Current VDD Operating Current VDD Operating Current Total HB Quiescent Current Total HB Operating Current HB to VSS Current, Quiescent HB to VSS Current, Operating INPUT PINS Low Level Input Voltage Threshold Low Level Input Voltage Threshold High Level Input Voltage Threshold High Level Input Voltage Threshold Input Voltage Hysteresis Input Pull-down Resistance UNDER VOLTAGE PROTECTION VDD Rising Threshold VDD Threshold Hysteresis
SYMBOL
TEST CONDITIONS
MIN
TYP
IDD IDD IDDO IDDO IHB IHBO IHBS IHBSO
ISL2110; LI = HI = 0V ISL2111; LI = HI = 0V ISL2110; f = 500kHz ISL2111; f = 500kHz LI = HI = 0V f = 500kHz LI = HI = 0V; VHB = VHS = 114V f = 500kHz; VHB = VHS = 114V
-
0.1 0.3 3.4 3.5 0.1 3.4 0.05 1.2
0.25 0.45 5.0 5.0 0.15 5.0 1.5 -
-
0.3 0.55 5.5 5.5 0.2 5.5 10 -
mA mA mA mA mA mA A mA
VIL VIL VIH VIH VIHYS RI
ISL2110 ISL2111 ISL2110 ISL2111 ISL2110
3.7 1.4 -
4.4 1.8 6.6 1.8 2.2 210
7.4 2.2 -
3.5 1.2 100
7.6 2.4 500
V V V V V k
VDDR VDDH
6.1 -
6.6 0.6
7.1 -
5.8 -
7.4 -
V V
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FN6295.1 July 11, 2006
ISL2110, ISL2111
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified (Continued) TJ = 25C PARAMETERS HB Rising Threshold HB Threshold Hysteresis BOOT STRAP DIODE Low Current Forward Voltage High Current Forward Voltage Dynamic Resistance LO GATE DRIVER Low Level Output Voltage High Level Output Voltage Peak Pull-Up Current Peak Pull-Down Current HO GATE DRIVER Low Level Output Voltage High Level Output Voltage Peak Pull-Up Current Peak Pull-Down Current VOLH VOHH IOHH IOLH IHO = 100mA IHO = -100mA, VOHH = VHB - VHO VHO = 0V VHO = 12V 0.1 0.16 3 4 0.18 0.23 0.25 0.3 V V A A VOLL VOHL IOHL IOLL ILO = 100mA ILO = -100mA, VOHL = VDD - VLO VLO = 0V VLO = 12V 0.1 0.16 3 4 0.18 0.23 0.25 0.3 V V A A VDL VDH RD IVDD-HB = 100A IVDD-HB = 100mA IVDD-HB = 100mA 0.5 0.7 0.7 0.6 0.9 1 0.7 1 1.5 V V SYMBOL VHBR VHBH TEST CONDITIONS MIN 5.5 TYP 6.1 0.6 MAX 6.8 TJ = -40C to 125C MIN 5.0 MAX 7.1 UNITS V V
Switching Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified TJ = 25C MIN 1 1 CL = 1nF CL = 1nF CL = 0.1F CL = 0.1F TYP 32 32 39 38 8 6 9 7.5 0.3 0.19 10 MAX 50 50 50 50 0.4 0.3 TJ = -40C to 125C MIN MAX 60 60 60 60 16 16 0.5 0.4 50 UNITS ns ns ns ns ns ns ns ns s s ns ns
PARAMETERS Lower Turn-Off Propagation Delay (LI Falling to LO Falling) Upper Turn-Off Propagation Delay (HI Falling to HO Falling) Lower Turn-On Propagation Delay (LI Rising to LO Rising) Upper Turn-On Propagation Delay (HI Rising to HO Rising) Delay Matching: Upper Turn-Off to Lower Turn-On Delay Matching: Lower Turn-Off to Upper Turn-On Either Output Rise Time (10% to 90%) Either Output Fall Time (90% to 10%) Either Output Rise Time (3V to 9V) Either Output Fall Time (9V to 3V) Minimum Input Pulse Width that Changes the Output Bootstrap Diode Turn-On or Turn-Off Time
SYMBOL tLPHL tHPHL tLPLH tHPLH tMON tMOFF tRC tFC tR tF tPW tBS
TEST CONDITIONS
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FN6295.1 July 11, 2006
ISL2110, ISL2111 Pin Descriptions
SYMBOL VDD HB HO HS HI LI VSS LO EPAD DESCRIPTION Positive supply to lower gate driver. Bypass this pin to VSS. High-side bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin. Bootstrap diode is on-chip. High-side output. Connect to gate of high-side power MOSFET. High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. High-side input. Low-side input. Chip negative supply, which will generally be ground. Low-side output. Connect to gate of low-side power MOSFET. Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
Timing Diagrams
LI
HI, LI tHPLH , tLPLH HO, LO tHPHL, tLPHL
HI
LO tMON HO tMOFF
FIGURE 3. PROPAGATION DELAYS
FIGURE 4. DELAY MATCHING
Typical Performance Curves
10
10
IDDO (mA)
1
IDDO (mA) 1 .10
1
0.1
10
100 FREQUENCY (kHz)
3
0.1
10
100 FREQUENCY (kHz)
1 .10
3
T = -40C T = 25C T = 125C T = 150C
T = -40C T = 25C T = 125C T = 150C
FIGURE 5. ISL2110 IDD OPERATING CURRENT vs FREQUENCY
FIGURE 6. ISL2111 IDD OPERATING CURRENT vs FREQUENCY
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FN6295.1 July 11, 2006
ISL2110, ISL2111 Typical Performance Curves
10
(Continued)
10
IHBSO (mA)
IHBO (mA)
1
1
0.1
0.1
0.01
10
100 FREQUENCY (kHz)
1 .10
3
0.01
10
100 FREQUENCY (kHz)
1 .10
3
T = -40C T= 25C T = 125C T = 150C
T = -40C T = 25C T = 125C T = 150C
FIGURE 7. IHB OPERATING CURRENT vs FREQUENCY
FIGURE 8. IHBS OPERATING CURRENT vs FREQUENCY
300 250 200 150 100 50
200
VOHL, VOHH (mV)
VOLL, VOLH (mV) 50 0 50 TEMPERATURE (C) 100 150
150
100
50
50
0
50 TEMPERATURE (C)
100
150
VDD = VHB = 8V VDD = VHB = 12V VDD = VHB = 14V
VDD = VHB = 8V VDD = VHB = 12V VDD = VHB = 14V
FIGURE 9. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE
FIGURE 10. LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE
6.7 6.5 VDDR, VHBR (V) 6.3 6.1 5.9 5.7 5.5 5.3 50 0 50 TEMPERATURE (C) 100 150 VDDH, VHBH (V)
0.7 0.65 0.6 0.55 0.5 0.45 0.4 50 0 50 TEMPERATURE (C) 100 150
VDDR VHBR
VDDH VHBH
FIGURE 11. UNDERVOLTAGE LOCKOUT THRESHOLD vs TEMPERATURE
FIGURE 12. UNDERVOLTAGE LOCKOUT HYSTERESIS vs TEMPERATURE
7
FN6295.1 July 11, 2006
ISL2110, ISL2111 Typical Performance Curves
tLPLH, tLPHL, tHPLH, tHPHL (ns) 55 50 45 40 35 30 25 50 0 50 TEMPERATURE (C) 100 150
(Continued)
tLPLH, tLPHL, tHPLH, tHPHL (ns)
55 50 45 40 35 30 25 50 0 50 TEMPERATURE (C) 100 150
tLPLH tLPHL tHPLH tHPHL
tLPLH tLPHL tHPLH tHPHL
FIGURE 13. ISL2110 PROPAGATION DELAYS vs TEMPERATURE
FIGURE 14. ISL2111 PROPAGATION DELAYS vs TEMPERATURE
8 7.5 tMON, tMOFF (ns) 7 6.5 6 5.5 5 4.5 4 50 0 50 TEMPERATURE (C) 100 150 tMON, tMOFF (ns)
10 9.5 9 8.5 8 7.5 7 6.5 6 5.5 5 4.5 4
50
0
50 TEMPERATURE (C)
100
150
tMON tMOFF
tMON tMOFF
FIGURE 15. ISL2110 DELAY MATCHING vs TEMPERATURE
FIGURE 16. ISL2111 DELAY MATCHING vs TEMPERATURE
3.5 3 IOHL, IOHH (A) IOLL, IOLH (A) 0 2 4 6 VLO, VHO (V) 8 10 12 2.5 2 1.5 1 0.5 0
4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 2 4 6 VLO, VHO (V) 8 10 12
FIGURE 17. PEAK PULL-UP CURRENT vs OUTPUT VOLTAGE
FIGURE 18. PEAK PULL-DOWN CURRENT vs OUTPUT VOLTAGE
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FN6295.1 July 11, 2006
ISL2110, ISL2111 Typical Performance Curves
120 110 100 90 80 70 60 50 40 30 20 10 0
(Continued)
0
5
10 VDD, VHB (V)
15
20
320 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0
IDD, IHB (uA)
IDD, IHB (uA)
0
5
10 VDD, VHB (V)
15
20
IDD IHB
IDD IHB
FIGURE 19. ISL2110 QUIESCENT CURRENT vs VOLTAGE
FIGURE 20. ISL2111 QUIESCENT CURRENT vs VOLTAGE
1 FORWARD CURRENT (A) 0.1 0.01 1 .10 1 .10 1 .10 1 .10
3 4 5 6
120 VDD to VSS VOLTAGE (V) 100 80 60 40 20 0 12 13 14 VHS to VSS VOLTAGE (V) 15 16
0.3
0.4
0.5 0.6 FORWARD VOLTAGE (V)
0.7
0.8
FIGURE 21. BOOTSTRAP DIODE I-V CHARACTERISTICS
FIGURE 22. VHS VOLTAGE vs VDD VOLTAGE
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FN6295.1 July 11, 2006
ISL2110, ISL2111 Dual Flat No-Lead Plastic Package (DFN) Micro Lead Frame Plastic Package (MLFP)
2X 0.15 A D D/2 D1 D1/2 2X N 0.15 C B C A
L12.4x4A
12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 A2 A3 b D D1 0.18 MIN 0.00 NOMINAL 0.85 0.01 0.65 0.20 REF 0.23 4.00 BSC 3.75 BSC 2.65 2.80 4.00 BSC 3.75 BSC 1.43 1.58 0.50 BSC 0.635 0.30 0.40 12 6 0.24 0.42 0.60 12 0.50 1.73 2.95 0.30 MAX 0.90 0.05 0.70 NOTES 5, 8 7, 8 7, 8 8 2 3 Rev. 0 8/03
E1/2 E1
E/2 E 9
D2 E E1 E2
6 INDEX AREA 0.15 2X 0.15 2X 4X 0 A2 C A C B 123
TOP VIEW
B
e k
A
L
//
0.10 0.08 C C
N Nd P
SEATING PLANE
C
SIDE VIEW
A3
A1
7
8 D2
NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. N is the number of terminals.
D2/2
(Nd-1)Xe REF.
1 6 INDEX AREA
23 NX k
3. Nd refer to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
5
M
E2 7 8
E2/2
4X P N N-1 e NX b 0.10 CAB
7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. COMPLIANT TO JEDEC MO-229-VGGD-2 ISSUE C except for the L dimension.
BOTTOM VIEW
C L NX b 5 CC e A1
L
5
TERMINAL TIP
FOR EVEN TERMINAL/SIDE
10
FN6295.1 July 11, 2006
ISL2110, ISL2111 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 8 8 0 8 MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.2284 0.0099 0.016 8 0
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 0.2440 0.0196 0.050
B C D E e H
C
A1 0.10(0.004)
0.050 BSC
1.27 BSC
e
B 0.25(0.010) M C AM BS
h L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN6295.1 July 11, 2006

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