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STSMIA832
1.8V/2.8V High speed dual differential line receivers, standard mobile imaging architecture (SMIA) decoder deserializer
Feature summary
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Sub-low voltage differential signaling inputs: VID = 100mV MIN. with RT = 100, CL = 10pF High signaling rate: fIN = 650 Mbps MAX (D+,D-,STRB+,STRB-) fOUT = 82 MHz MAX (CLK) fOUT = 82 Mbps MAX (for each data line D1-D8) Very high speed strobe to clock: tpLH~tpHL=5.2ns (TYP) at VDD=2.8V; VL=1.8V Operating voltage range: VDD(OPR) = 2.65V to 3.6V VL(OPR) =1.65V to 1.95V Symmetrical output impedance (D1-D8, HSYNC, V-SYNC, CLK): IIOHI=IOL=4mA (MIN) at VDD=2.65V;VL=1.8V Low power dissipation (DISABLED: EN=Gnd): ISOFF = IDD + IL = 10 A (Max) SMIA specification compliant CLASS 0 and CLASS 1,2 supported (config by CLASS_SEL) CMOS logic input threshold (EN, SYNC_SEL, CLASS_SEL): VIL = 0.3xVL; VL = 1.65V to 1.95V VIH = 0.7xVL; VL = 1.65V to 1.95V 3.6V tolerant on inputs (EN, SYNC_SEL, CLASS_SEL) 32 BIT synchronization codes (SOF, EOF, SOL, EOL) Leadfree TFBGA package (RoHS Restriction of hazardous substances)
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TFBGA25
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Description
The STSMIA832 receiver converts the subLVDS clock/datastream (up to 650 Mbps throughput bandwidth) back into parallel 8 bits of CMOS/LVTTL. The device recognizes the SMIA 32 bit start of frame (SOF), end of frame (EOF), start of line (SOL) and end of line (EOL) sequences to generate the H-SYNC and V-SYNC signals. Output LVTTL clock (up to 82 MHz) is transmitted in parallel with data. Output data are rising-edge strobes. This chipset is an ideal means to link mobile camera modules to Baseband processors. In order to minimize static current consumption, it is possible to shut down the device when the interface is not being used by a power-down (EN) pin that reduces the Maximum Current Consumption to 10 A making this device ideal for portable applications like Mobile Phone and Portable Battery Equipment. A configurable input (Class_Sel) is provided to select different CLASS (0 or 1,2) mode inside the SMIA STD specifications. The STSMIA832 is offered in a TFBGA package to optimize PCB space. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity from transient excess voltage. The STSMIA832 is characterized for operation over the commercial temperature range -40C to 85C.
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Order codes
Part number STSMIA832TBR May 2006 Temperature Range -40 to 85 C Package TFBGA25 3x3mm (TAPE & REEL) Rev. 2 Packaging 3000 parts per reel 1/23
www.st.com 23
STSMIA832
Contents
1 2 Schematic diagram ......................................... 3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 Pin descriptions for reference: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Supplementary notes: SMIA specification . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power saving at the inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Switching off digital blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Disabling the outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4 5 6 7 8 9
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Frame structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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STSMIA832
Schematic diagram
1
Figure 1.
Schematic diagram
Simplified application block diagram
Figure 2.
Block diagram
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Pin configuration
STSMIA832
2
Figure 3.
Pin configuration
Pin connections (top through view - bumps are on the other side)
Table 1.
PlN N D5 E5 D4 D3 D2 D1 E1 C3 A2, A1 A5, A4 B3 E3 C2 B2 E2, E4 A3, B1 B5 C1, C5 B4 C4
Pin description
SYMBOL D1 D2 D3 D4 D5 D6 D7 D8 D+, DSTRB+, STRBEN CLK H-SYNC V-SYNC GND GND VDD VL SYNC_SEL CLASS_SEL Decoder output (LSB) Decoder output Decoder output Decoder output Decoder output Decoder output Decoder output Decoder output (MSB) Differential data receiver inputs Differential strobe receiver inputs (Class_Sel = VL) Differential clock receiver inputs (Class_Sel = GND) Receivers enable input Clock output Horizontal sync output Vertical sync output Ground (Digital I/O reference) Ground (Analog subLVDS part) Core supply voltage Digital I/O supply voltage Select sync input Select CLASS input NAME AND FUNCTION
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STSMIA832
Pin configuration
2.1
Pin descriptions for reference:
(D+, D-, STRB+, STRB-)
Differential subLVDS data and strobe inputs to the receiver from the camera sensor interface. The signals operate at 150mV typical differential voltage levels and a common mode voltage of 900mV. The operating data rate is 650Mbps maximum. Depending on the CLASS_SEL pin selection mode, Data/Clock signaling or Data/Strobe signaling modes are activated.
D1-D8, CLK
STSMIA832 output data and clock lines. Parallel 8 bits of CMOS/LVTTL data is output at a maximum data rate of 82Mbps per line. Output LVTTL clock is transmitted in parallel with the data at 82MHz Max.
SYNC-SEL
The Horizontal Sync and Vertical Sync signals are extracted from the data stream before transmitting data on the parallel output D1-D8 if the device is working in ENABLED SYNC mode (SYNC_SEL = VL). If the device is working in DISABLED SYNC mode (SYNC_SEL = GND) the sync codes are not extracted from the data stream and the embedded Sync codes are transmitted along with the data on the parallel output. This allows for two modes of functioning, formatted and unformatted transmission of data on the data lines based on the selection by the Baseband processor. The main function table lists the functions for various combinations of SYNC_SEL pin and EN pin.
CLASS-SEL
The device embeds all functions forecast inside the SMIA Standard. STRB+ and STRBsignals are considered STROBE Signals when the device is working in HIGH CLASS mode (CLASS_SEL = VL). If the device is working in LOW CLASS mode (CLASS_SEL = GND) the STRB+ and STRB- inputs change their strobe functionality to CLOCK in order to be compliant with SMIA CLASS 0. In Class 0 mode of operation, data is read on the rising edge only. This allows for two modes of functioning, Clocked and Strobed transmission according to different applications and provides high flexibility to configure the final application in different Baseband processors.
H-SYNC, V-SYNC
In the ENABLED SYNC mode, the parallel data on D1-D8 is accompanied by the Horizontal and Vertical Sync signals on the H-SYNC and V-SYNC pins and together they are used to reconstruct the image frame. The H-SYNC and V-SYNC are generated by extracting the SMIA 32-bit Synchronization codes (SOF, EOF, SOL, EOL) on the serial input data stream.
EN
Enable pin is to enable the Power-Down Mode. This mode enables the shutting down of the device when the interface is not in use. The maximum current consumption can be reduced to 10 A. This provision makes this device suitable for portable applications like Mobile phones or Portable Battery Equipment.
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Pin configuration
STSMIA832
VDD, VL
Both the Camera Sensor module and the Baseband processor interface operate at VL = 1.8V. The subLVDS receiver core operating voltage is VDD = 2.8V typical.
2.2
Supplementary notes: SMIA specification
The Standard Mobile Imaging Architecture (SMIA) specification defines an interface between the digital camera module and mobile phone engine. It defines a standard data transmission and control interface between transmitter (camera module) and receiver (mobile phone engine). The data transmission interface (referred to as CCP2) is a unidirectional differential serial interface with data and clock/strobe signals. The physical layer of CCP2 is based on signaling scheme called SubLVDS, which is current mode differential low voltage signaling method modified from the IEEE 1596.3 LVDS standard for reduced power consumption. STSMIA832 operates in a data/strobe signaling mode. The use of data-strobe coding together with SubLVDS enables the use of high data rates with low EMI.
Data/Clock signaling
Data is a differential output from camera module. Data format is in most of cases bytewise (i.e. on 8-bit boundary) least significant bit (LSB) first. When nothing is being transferred, the DATA lines remain high, except in power shutdown. Figure illustrates the bytewise LSB first transmission.. Figure 4. Data clock signaling
Clock is a differential signal, output from camera module. The receiver reads the data on rising edge of the CCP_CLK. The clock signal may be free running or gated. For most cases free running clock is preferred due to simpler implementation in the transmitting end. However, in some cases gated clock may be better solution. If gated transmission clock is used, clock remains high when nothing is being transferred, except in power shutdown.
Data/Strobe signaling
The data-strobe coding consists of two parallel signals, data and strobe. The data signal carries the bit-serial data while the strobe signal state toggles whenever data signal does not change state. Thus, either the data signal or the strobe signal changes between two data bits. If both signals change simultaneously it is interpreted as an error. The signaling method is presented in the figure 2 below. The benefit of using data-strobe signaling is that there is no need for transferring continuous clock over the CCP2 bus. The frequency of the bus is also divided by two. The clock is reconstructed at the receiving end from the data and strobe signals. This simplifies the EMC design and in addition, EMI is reduced compared to normal data/clock signaling.
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STSMIA832 . Figure 5. Data-Strobe signaling
Pin configuration
Data is sent byte-wise LSB first. The state of the data and strobe signals at the beginning of transmission are fixed i.e. the state of data is logic high and the state of strobe is logic low. The number of clock cycles between synchronization codes has to be even, both between SOL (or SOF) - EOL (or EOF) and EOL (or EOF) - SOL (or SOF). This ensures synchronization is possible with minimum complexity to achieve the fastest possible implementation. The strobe signal can be gated when using the data/strobe signaling, but only if the number of clock cycles is even between synchronization codes. If the number of transmission clock cycles between synchronization codes is even, it ensures that for each synchronization code sequence FF0000h there will be corresponding strobe sequence of 55AAAAh as illustrated in the Figure 3 below. Figure 6. Data-Strobe phase relationship
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Pin configuration
STSMIA832
Frame synchronization
Each image frame begins with frame start synchronization code (SOF) and ends with frame end synchronization code (EOF). Each line inside the frame begins with line start synchronization code (SOL) and ends with line end synchronization code (EOL). The period between EOL code and new SOL code is called line blanking period. Similarly, the time between EOF code and new SOF code is called frame blanking period. The total size of one image frame shall be a multiple of 128 bits. In the beginning of frame and in the end of frame, line synchronization codes are replaced by the frame synchronization codes. Synchronization signal usage is shown in Figure 4 below. Bit order of the synchronization codes is the same as for data, byte-wise LSB first. Figure 7. CCP2 Synchronization codes
The purpose of logical channels is to separate different data flows, which are interleaved in the data stream. The DMA channel identifier number is directly encoded in the 4-byte CCP embedded sync codes. The CCP receiver will monitor the DMA channel identifier and de-multiplex the interleaved video streams to their appropriate DMA channel. A maximum of 8 data streams is supported. Valid channel identifiers are 0 to 7. Table 2.
Name SOL EOL SOF EOF Logical Channels
Synchronization codes as per SMIA specifications
Synchronization Codes FFH 00H 00H X0H FFH 00H 00H X1H FFH 00H 00H X2H FFH 00H 00H X3H FFH 00H 00H 0XH (to) FFH 00H 00H 7XH Line Start Code Line End Code Frame Start Code Frame End Code DMA Channel Identifier from Channel 0 to 7 Notes
X = channel number 0 to 7.
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STSMIA832
Application information
3
3.1
Application information
Inputs
Technological advancements in deeper submicron processes have lowered the supply voltage levels of semiconductor devices, creating a design environment where system board devices may potentially use many different supply voltages, which can ultimately lead to voltage conflicts. However, STSMIA832 device has been designed to work with a 3.6V input tolerance. This implies that all input pins (differential inputs and control inputs) can be connected to 3.6V logic or bus even when power to the device is only 1.8V. The device would not be damaged.
3.2
Power down mode
STSMIA832 comes equipped with a Power Down mode that permits an exceptionally low level of power consumption (ISOFF = 10 A maximum), making the device ideal for portable battery-powered applications as well as for designs with tight thermal budgets. The low quiescent supply current possible with Power Down mode is especially useful for products that must use power as efficiently as possible. Low power offers additional benefits such as low operating temperature, low cost packages and high device reliability. The device saves significant quiescent power while internal functions are temporarily suspended. The activation and de-activation of the power down mode is controlled by the EN pin. The mode becomes active once a low-level pulse is applied to the EN pin. The maximum quiescent supply current gets reduced to ISOFF = 10 A maximum. Power Down mode is initiated by applying a low-level pulse to the EN input of STSMIA832 device. The device remains in a DC state, drawing minimal power, until EN goes High, at which point it returns to full operation.
Figure 8.
STSMIA832 Power down mode
The power saving in the Power Down Mode is obtained by employing the following techniques:
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Application information
STSMIA832
3.3
Power saving at the inputs
All internal blocks of the input circuitry are shutdown by turning off the bias currents for the subLVDS Receivers. This eliminates the power associated with any dynamic activity on the input pins. With no pull-up and pull-down resistors, any remaining current drawn by an input is known as leakage current (IL), which ranges from 1 A to 4 A typical. But care should be taken that the driving circuit for the inputs is also switched to a known state and that there are no transitions on the inputs when the device is in Power Down Mode.
3.4
Switching off digital blocks
To save power, all signals within the device are prevented from switching by resetting all the digital blocks in the internal circuits. In many designs, a major portion of the total dynamic power is due to its clock tree, which consists of all the inter-connects that distributes the clock signal internally. Power drawn varies according to how extensive the tree is. Pulling the clock input to a static logic level (LOW in this case) is an important way to save power, especially as the clock frequency is high
3.5
Disabling the outputs
In the power down mode, to save the power due to transition on output flip flops, the Clock Enable (CE) signal for all the flip-flops is used in the design. All the clock transitions are ignored when the CE signal is inactive and so the output flip flops do not toggle. The CE signal is activated once again when the registered outputs need to be operating under normal conditions. All the outputs (including D1-D8) are driven LOW in the power down state. This reset state is held as long as the device remains in Power Down mode. Once having exited the mode, normal operation recommences from the reset state.
3.6
Load capacitance
Power dissipation is proportional to capacitance. The capacitance consists both of internal and external capacitance. The lumped internal capacitance is associated with the power dissipated internally by the device and depends on the device characteristics (in STSMIA832, CIN is 4pF). The external capacitance is associated with power dissipated outside the device and it is a function of PCB traces loading and other IC loads. In high frequency operation, it is essential to have equal trace lengths for all the output lines in order to minimize the skew. A reduced external capacitance leads to reduced current consumption and also reduced rise time and fall time. The parallel output driving capacitance in STSMIA832 is 10pF and the rise time and fall times for the LVTTL parallel outputs are 2.2ns maximum.
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STSMIA832 . Figure 9.
Application information
STSMIA832 Load capacitance and rise and fall time of LVTTL parallel outputs
3.7
Board layout
To obtain the maximum benefit from the noise and EMI reductions of subLVDS, attention should be paid to the layout of differential lines. Lines of a differential pair should always be adjacent to eliminate noise interference from other signals and take full advantage of the noise canceling of the differential signals. Equal length should be maintained on signal traces for a given differential pair. As with any high-speed design, the impedance discontinuities should be limited (reduce the numbers of vias and no 90 degree angles on traces). Any discontinuities which do occur on one signal line should be mirrored in the other line of the differential pair. Care should be taken to ensure that the differential trace impedance match the differential impedance of the selected physical media (this impedance should also match the value of the termination resistor (100 ohms) that is connected across the differential pair at the receiver's input). Surface mount resistors are recommended to avoid the additional inductance that accompanies leaded resistors. These resistors should be placed as close as possible to the receiver input pins to reduce stubs and effectively terminate the differential lines. All of these considerations will limit reflections and crosstalk which adversely effect high frequency performance and EMI.
3.8
Decoupling capacitors
Bypassing capacitors are needed to reduce the impact of switching noise which could limit performance. For a conservative approach three parallel-connected decoupling capacitors (Multi-Layered Ceramic capacitors in surface mount form factor) between each VCC and the ground plane(s) are recommended. An example is shown in the figure below. Wide traces for power and ground should be used and it should be ensured each capacitor has its own via to the ground plane.
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Application information . Figure 10. Bypass decoupling capacitors
STSMIA832
Table 3.
Synchronization codes as per SMIA specifications
INPUT OUTPUT FUNCTION DX STRB+ STRB- V-SYNC H-SYNC X X L H L No Change No Change L H L H L See Detailed Timing Diagram D1-D8 L CLK L SMIA disabled Start of Frame End of Frame Start of Line End of Line D+, DSee Disabled Sync data in Detailed (D1-D8 will get parallel Timing out data, including mode Diagram Sync Code)
EN L H H H H
SYNC_SEL X H H H H
D+ X
SOF (FFH 00H 00H 02H) EOF(FFH 00H 00H 03H) SOL(FFH 00H 00H 00H) EOL(FFH 00H 00H 01H)
H
L
X
X
X
X
L
L
X = Don't care
Table 4.
Class function table (CSI Classification)
CLASS Class 0 Class 1 Class 2 Data Transfer Capacity (Sustained Data Rate) <208 Mbps 208-416 Mbps 416-650 Mbps Signaling Method Data/Clock Data/Strobe Data/Strobe CLASS_SEL GND VL VL
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STSMIA832
Maximum ratings
4
Table 5.
Symbol VDD VL VD VSTRB VI VO Tstg ESD
Maximum ratings
Absolute maximum ratings
Parameter Main Supply Voltage Secondary Supply Voltage SubLVDS Data Bus Input Voltage (D+, D-) SubLVDS Clock Bus Input Voltage (STRB+, STRB-) DC Input Voltage (SYNC_SEL, CLASS_SEL, EN) DC Output Voltage (D1-D8, H-SYNC, V-SYNC, CLK) Storage Temperature Range Electrostatic Discharge Protection HBM Human Body Model (All Pins) Value -0.5 to 4.6 -0.5 to (VDD + 0.5) -0.5 to 4.6 -0.5 to 4.6 -0.5 to 4.6 -0.5 to (VL + 0.5) -65 to +150 2 Unit V V V V V V C kV
Note:
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. Recommended operating conditions
Parameter Main Supply Voltage Secondary Supply Voltage Differential Level Input Voltage (D+, D-, STRB+, STRB-) Common Level Input Voltage (D+, D-, STRB+, STRB-) Level Input Voltage (SYNC_SEL, CLASS_SEL, EN) Termination Resistance (per pair differential input line) Termination Capacitance (per line vs Gnd Pin) Operating Ambient Temperature Range Operating Junction Temperature Range Rise and Fall Time (SYNC_SEL, CLASS_SEL, EN; 10% to 90%; 90% to 10%) -40 -40 Min. 2.65 1.65 0.1 0.5 1.65 80 0.9 1.8 100 10 85 125 10 Typ. 2.8 1.8 Max. 3.6 1.95 0.4 1.3 3.6 120 Unit V V V V V pF C C ns
Table 6.
Symbol VDD VL VID VCM VIC RT CL TA TJ tR, tF
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Characteristics
STSMIA832
5
Table 7.
Characteristics
Electrical characteristics (Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25C, and VDD = 2.8V, VL = 1.8V)
Parameter Common Mode Input Voltage Receiver Input Low Threshold (1) Receiver Input High Threshold Input Leakage Current (D+, D-, STRB+, STRB-)
(1)
Symbol VCM VTHL VTHH II
Test Conditions RT = 100 1% RT = 100 1% RT = 100 1% VI = 0.4V VI = 1.4V EN=VDD, D+, STRB+ = Gnd or VDD, D-, STRB- = VDD or Gnd EN=Gnd, VDD=2.65V to 3.6V VL=1.65V to 1.95V VDD = 2.65V to 3.6V VL = 1.65V to 1.95V VDD = 2.65V to 3.6V VL = 1.65V to 1.95V VIH = 0.7xVL VIL= 0.3xVL IOH = -4mA IOL = +4mA
Min. 0.5 -25
Typ. 0.9
Max. 1.3
Unit V mV
+25 10 10 3.5 9.0
mV A A mA
IS
Supply Current (IL + IDD) Shutdown Supply Current (IL+ IDD) HIGH Level Input Voltage (SYNC_SEL, CLASS_SEL, EN) LOW Level Input Voltage (SYNC_SEL, CLASS_SEL, EN) HIGH Level Input Current (SYNC_SEL, CLASS_SEL, EN) LOW Level Input Current (SYNC_SEL, CLASS_SEL, EN) HIGH Level Output Voltage (D1-D8, H-SYNC, V-SYNC, CLK) LOW Level Output Voltage (D1-D8, H-SYNC, V-SYNC, CLK)
ISOFF VIH VIL IIH IIL VOH VOL
10 0.7xVL 0 3.6V 0.3xVL 10 10 1.25 0.30
A V V A A V V
1. Guaranteed by design
Table 8.
Capacitive characteristics
Test Conditions Value TA = 25C VDD (V) Min. Typ. 4 Max. pF Input Capacitance (SYNC_SEL, CLASS_SEL, EN) VL = 1.65V to 1.95V, VI = GND or VL Unit
Symbol
Parameter
CIN
2.65 to 3.6
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STSMIA832 Table 9.
Characteristics
Switching characteristics (RT = 100 1%, CL = 10pF, over recommended operating conditions unless otherwise noted. Typical values are referred to TA = 25C and VDD = 2.8V, VL = 1.8V)
Parameter Rise Time LVTTL Output Voltage (10% to 90%) Fall Time LVTTL Output Voltage (90% to 10%) Propagation Delay Time (STRB to V-SYNC, H-SYNC) Low to High Strobed Transmission Propagation Delay Time (STRB to CLASS_SEL=VL V-SYNC, H-SYNC) High to Low Propagation Delay Time (STRB to CLK) Low to High Propagation Delay Time (STRB to CLK) High to Low Propagation Delay (STRB to D1-D8) Low to High Propagation Delay (STRB to D1-D8) High to Low Test Conditions Min. Typ. 1.9 1.6 6.3 6.9 5.2 Strobed Transmission CLASS_SEL=VL 5.2 6.8 Strobed Transmission CLASS_SEL=VL 6.4 6.0 6.0 4.7 Clocked Transmission CLASS_SEL= Gnd 4.7 6.0 Clocked Transmission CLASS_SEL= Gnd 5.4 trEN = 2.0ns (10% to 90%) tfEN = 2.0ns (90% to 10%) trEN = 2.0ns (10% to 90%) tfEN = 2.0ns (90% to 10%) CLASS_SEL=VL CLASS_SEL=VL CLASS_SEL=VL 1538 780 7.5 20 100 650 ns s ns Mbps ps ps 6.0 7.5 ns ns Max. 2.5 2.5 8.5 8.5 6.5 6.5 8.5 8.5 7.0 7.0 6.0 Unit ns ns ns ns ns ns ns ns ns ns ns
Symbol tr tf tpLH tpHL tpLH tpHL tpLH tpHL tpLH tpHL tpLH tpHL tpLH tpHL tEN tDIS DRMAX TSTRB tDS
Propagation Delay Time (STRB to V-SYNC, H-SYNC) Low to High Clocked Transmission Propagation Delay Time (STRB to CLASS_SEL= Gnd V-SYNC, H-SYNC) High to Low Propagation Delay Time (STRB to CLK) Low to High Propagation Delay Time (STRB to CLK) High to Low Propagation Delay (STRB to D1-D8) Low to High Propagation Delay (STRB to D1-D8) High to Low Enable Delay Time (EN to V-SYNC, H-SYNC) Disable Delay Time (EN to V-SYNC, H-SYNC) Max Usable Data Rate Strobe Target Period Minimum Data/Strobe Edge Separation
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Frame structure.
STSMIA832
6
Frame structure.
Figure 11. Frame structure in VGA case (allowed synchronization codes sequence)
Figure 12. Bit order in synchronization codes and data, LSB first (example start of frame), image frame structure
1. LSB (bytewise Least Significant Bit first)
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STSMIA832
Timing diagram
7
Timing diagram
(unless otherwise specified TA = 25C)
Figure 13. Disabled Sync Mode (SYNC_SEL = GND) (D1-D8 will transmit the input data DIN, including SYNC CODE) and CLASS_SEL = VL
1. Note: DATA_IN and STROBE are the input signals, CLKH is an internal signal i.e internal extracted clock having half frequency respect to the external clock. All others are output signals.
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Timing diagram
STSMIA832
Figure 14. Enabled sync mode (SYNC_SEL = VDD) (D1-D8 will transmit the input data DIN, excluding SYNC CODE) and CLASS_SEL = VL
1. Note: DATA_IN and STROBE are the input signals, CLKH is an internal signal i.e internal extracted clock having half frequency respect to the external clock. All others are output signals.
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STSMIA832
Package mechanical data
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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Package mechanical data
STSMIA832
TFBGA25 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 b D D1 E E1 e SE 2.9 0.78 0.25 2.9 0.30 3.0 2 3.0 2 0.5 0.25 3.1 114.2 1.0 TYP 1.1 MAX. 1.16 0.25 0.86 0.35 3.1 30.7 9.8 114.2 11.8 118.1 78.8 118.1 78.8 19.7 9.8 122.0 MIN. 39.4 TYP. 43.3 MAX. 45.7 9.8 33.9 13.8 122.0 mils
7539979/A
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STSMIA832
Package mechanical data
Tape & Reel TFBGA25 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 3.9 7.9 3.3 3.3 1.60 4.1 8.1 0.153 0.311 12.8 20.2 60 14.4 0.130 0.130 0.063 0.161 0.319 TYP MAX. 330 13.2 0.504 0.795 2.362 0.567 MIN. TYP. MAX. 12.992 0.519 inch
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Revision history
STSMIA832
9
Table 10.
Date
Revision history
Revision history
Revision 1 2 Initial release. Mistake on table 3 - Output. Changes
13-Mar-2006 3-May-2006
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STSMIA832
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