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| 16-Bit, 200 MSPS/500 MSPS TxDAC+(R) with 2x/4x/8x Interpolation and Signal Processing AD9786 FEATURES 16-bit resolution, 200 MSPS input data rate IMD 90 dBc @10 MHz Noise spectral density (NSD) -164 dBm/Hz @ 10 MHz WCDMA ACLR = 80 dBc @ 40 MHz IF DNL = 0.3 LSB INL = 0.6 LSB Selectable 2x/4x/8x interpolation filters Selectable fDAC/2, fDAC/4, fDAC/8 modulation modes Single or dual channel signal processing Selectable image rejection Hilbert transform Flexible calibration engine Direct IF transmission features Serial control interface Versatile clock and data interface 3.3 V compatible digital interface On-chip 1.2 V reference 80-lead thermally enhanced TQFP package PRODUCT DESCRIPTION The AD9786 is a 16-bit, high speed, CMOS DAC with 2x/4x/8x interpolation and signal processing features tuned for communications applications. It offers state-of-the-art distortion and noise performance. The AD9786 was developed to meet the demanding performance requirements of multicarrier and third generation base stations. The selectable interpolation filters simplify interfacing to a variety of input data rates while also taking advantage of oversampling performance gains. The modulation modes allow convenient bandwidth placement and selectable sideband suppression. The flexible clock interface accepts a variety of input types such as 1 V p-p sine wave, CMOS, and LVPECL in single-ended or differential mode. Internal dividers generate the required data rate interface clocks. The AD9786 provides a differential current output, supporting single-ended or differential applications; it provides a nominal full-scale current from 10 mA to 20 mA. The AD9786 is manufactured on an advanced low cost 0.25 m CMOS process. APPLICATIONS Base stations: Multicarrier WCDMA, GSM/EDGE, TD-SCDMA, IS136, TETRA Instrumentation: RF Signal Generators, Arbitrary Waveform Generators HDTV Transmitters Broadband Wireless Systems Digital Radio Links Satellite Systems FUNCTIONAL BLOCK DIAGRAM CALIBRATION LATCH 2x 2x 2x Q 90 fDAC/2 fDAC/4 fDAC/8 REFERENCE CIRCUITS 16-BIT DAC FSADJ REFIO P1B[15:0] P2B[15:0] DATA ASSEMBLER Re()/Im() 0 t 0 90 0 ZERO STUFF IOUTA IOUTB SDIO DATA PORT SYNCHRONIZER SPI 90 Q x1 LATCH 2x 2x 2x HILBERT SDO CSB SCLK RESET DATACLK CLK+ CLK- CLOCK DISTRIBUTION AND CONTROL Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved. 03152-0-001 AD9786 TABLE OF CONTENTS Product Highlights ........................................................................... 3 Specifications..................................................................................... 4 DC Specifications ......................................................................... 4 Dynamic Specifications ............................................................... 5 Digital Specifications ................................................................... 6 Absolute Maximum Ratings ....................................................... 6 Thermal Characteristics .............................................................. 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Clock .............................................................................................. 8 Analog............................................................................................ 9 Data ................................................................................................ 9 Serial Interface ............................................................................ 10 Definition of Specifications........................................................... 11 Typical Performance Characteristics ........................................... 13 Serial Control Interface.................................................................. 19 General Operation of the Serial Interface ............................... 19 Serial Interface Port Pin Descriptions ..................................... 19 MSB/LSB Transfers..................................................................... 20 Notes on Serial Port Operation ................................................ 20 Mode Control (via SERIAL Port)................................................. 21 Digital Filter Specifications ........................................................... 25 Digital Interpolation Filter Coefficients.................................. 25 AD9786 Clock/Data Timing..................................................... 26 Real and Complex Signals......................................................... 33 Modulation Modes..................................................................... 34 Power Dissipation ...................................................................... 39 Hilbert Transform Implementation......................................... 41 Operating the AD9786 Rev F Evaluation Board ........................ 45 Power Supplies............................................................................ 45 PECL Clock Driver .................................................................... 45 Data Inputs.................................................................................. 46 Serial Port .................................................................................... 46 Analog Output ............................................................................ 47 Outline Dimensions ....................................................................... 60 Ordering Guide .......................................................................... 61 REVISION HISTORY 7/04--Revision 0: Initial Version Rev. 0 | Page 2 of 60 AD9786 PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. The AD9786 is a 16-bit high speed interpolating TxDAC+. 2x/4x/8x user selectable interpolating filter eases data rate and output signal reconstruction filter requirements. 200 MSPS input data rate. Ultra high speed 500 MSPS DAC conversion rate. Flexible clock with single-ended or differential input: CMOS, 1 V p-p sine wave, and LVPECL capability. Complete CMOS DAC function operates from a 3.1 V to 3.5 V single analog (AVDD) supply, 2.5 V (DVDD) 8. digital supply, and a 2.5 to 3.3V DRVDD supply. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 7. On-chip voltage reference: The AD9786 includes a 1.20 V temperature-compensated band gap voltage reference. Multichip synchronization: Multiple AD9786 DACs can be synchronized to a single master AD9786 to ease timing design requirements and optimize image reject transmit performance. Rev. 0 | Page 3 of 60 AD9786 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD1, AVDD2 = 3.3 V, ACVDD, ADVDD, CLKVDD, DVDD, DRVDD = 2.5 V, IOUTFS = 20 mA, unless otherwise noted. Table 1. Parameter RESOLUTION DC Accuracy1 Integral Nonlinearity Differential Nonlinearity ANALOG OUTPUT Offset Error Gain Error (with Internal Reference) Full-Scale Output Current2 Output Compliance Range Output Resistance REFERENCE OUTPUT Reference Voltage Reference Output Current3 REFERENCE INPUT Input Compliance Range Reference Input Resistance (Ext Reference Mode) Small Signal Bandwith TEMPERATURE COEFFICIENTS Unipolar Offset Drift Gain Drift (with Internal Reference) Reference Voltage Drift POWER SUPPLY AVDD1, AVDD2 Voltage Range Analog Supply Current (IAVDD1 + IAVDD2) IAVDD1 + IAVDD2 in SLEEP Mode ACVDD, ADVDD Voltage Range Analog Supply Current (IACVDD + IADVDD) CLKVDD Voltage Range Clock Supply Current (ICLKVDD) DVDD Voltage Range Digital Supply Current (IDVDD) DRVDD Voltage Range Digital Supply Current (IDRVDD) Nominal Power Dissipation4 OPERATING RANGE Min Typ 16 0.6 0.3 0.015 1.5 Max Unit Bits LSB LSB 0.0175 20 +1.0 10 -1.0 10 1.15 1.23 1 % of FSR % of FSR mA V M V A V M kHz ppm of FSR/C ppm of FSR/C ppm/C 1.30 0.1 10 200 0 4 30 1.25 3.1 3.3 50 18 2.5 2.5 2.5 12 2.5 52.5 2.5/3.3 5.3 1.25 3.5 V mA mA V mA V mA V mA V A W C 2.35 2.65 2.35 2.65 2.35 2.65 2.35 3.5 -40 +85 1 2 3 Measured at IOUTA driving a virtual ground. Nominal full-scale current, IOUTFS, is 32x the IREF current. Use an external amplifier to drive any external load. 4 Measured under the following conditions: fDATA = 125 MSPS, fDAC = 500 MSPS, 4x interpolation, fDAC/4 modulation, Hilbert Off. Rev. 0 | Page 4 of 60 AD9786 DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD1, AVDD2 = 3.3 V, ACVDD, ADVDD, CLKVDD, DVDD, DRVDD = 2.5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 doubly terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Maximum DAC Output Update Rate (fDAC) Output Settling Time (tST) (to 0.025%) Output Propagation Delay1 (tPD) Output Rise Time (10% to 90% of Full Scale)2 Output Fall Time (90% to 10% of Full Scale)2 AC LINEARITY-BASEBAND MODE Spurious-Free Dynamic Range (SFDR) to Nyquist (fOUT = 0 dBFS) fDATA = 100 MSPS; fOUT = 5 MHz, 4x, 2x interpolation fDATA = 200 MSPS; fOUT = 10 MHz fDATA = 200 MSPS; fOUT = 25 MHz fDATA = 200 MSPS; fOUT = 50 MHz Two-Tone Intermodulation (IMD) to Nyquist (fOUT1 = fOUT2 = -6 dBFS) fDATA = 200 MSPS; fOUT1 = 5 MHz; fOUT2 = 6 MHz fDATA = 200 MSPS; fOUT1 = 15 MHz; fOUT2 = 16 MHz fDATA = 200 MSPS; fOUT1 = 25 MHz; fOUT2 = 26 MHz fDATA = 200 MSPS; fOUT1 = 45 MHz; fOUT2 = 46 MHz fDATA = 200 MSPS; fOUT1 = 65 MHz; fOUT2 = 66 MHz fDATA = 200 MSPS; fOUT1 = 85 MHz; fOUT2 = 86 MHz Noise Power Spectral Density (NPSD) fDATA = 156 MSPS; fOUT = 10 MHz; 0 dBFS, 8 tones, separation = 500 kHz fDATA = 156 MSPS; fOUT = 50 MHz; 0 dBFS, 8 tones, separation = 500 kHz Adjacent Channel Power Ratio (ACLR) WCDMA ACLR with 3.84 MHz BW, single carrier IF = 21 MHz, fDATA = 122.88 MSPS, 4x interpolation IF = 224.76 MHz, fDATA = 122.88 MSPS, 4x interpolation, high-pass interpolation filter mode Min 500 Typ Max Unit MSPS ns ns ns ns 93 85 78 78 85 85 84 80 78 75 -164 -161 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBm/Hz dBm/Hz 80 72 dB dB 1 2 Propagation delay is delay from CLK input to DAC update. Measured doubly terminated into 50 load. Rev. 0 | Page 5 of 60 AD9786 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD1, AVDD2 = 3.3 V, ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V, IOUTFS = 20 mA, unless otherwise noted. Table 3. Parameter DIGITAL INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance CLOCK INPUTS Input Voltage Range Common-Mode Voltage Differential Voltage Input Setup Time (tS)1 Input Hold Time (tH)1 Latch Pulse Width (tLPW)1 CLK to PLLLOCK Delay (tOD)1 1 Min DRVDD - 0.9 -10 -10 Typ DRVDD 0 Max Unit V V A A pF V V V 0.9 +10 +10 5 0 0.75 0.5 2.65 2.25 1.5 1.5 See timing specifications on Pages 26 to 31 for details in each timing mode. Rev. 0 | Page 6 of 60 AD9786 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter AVDD1, AVDD2, DRVDD ACVDD, ADVDD, CLKGND, DVDD AGND1, AGND2, ACGND, ADGND, CLKGND, DGND REFIO, FSADJ IOUTA, IOUTB P1B15-P1B0, P2B15-P2B0 DATACLK CLK+, CLK-, RESET CSB, SCLK, SDIO, SDO Junction Temperature Storage Temperature Lead temperature (10 sec) With Respect to AGND1, AGND2, ACGND, ADGND, CLKGND, DGND AGND1, AGND2, ACGND, ADGND, CLKGND, DGND AGND1, AGND2, ACGND, ADGND, CLKGND, DGND AGND1 AGND1 DGND DGND CLKGND DGND Min -0.3 -0.3 -0.3 -0.3 -1.0 -0.3 -0.3 -0.3 -0.3 -65 Max +3.6 +2.8 +0.3 AVDD1 + 0.3 AVDD1 + 0.3 DVDD + 0.3 DRVDD + 0.3 CLKVDD + 0.3 DVDD + 0.3 +125 150 300 Unit V V V V V V V V V C C C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. THERMAL CHARACTERISTICS Thermal Resistance 80-Lead Thermally Enhanced TQFP Package JA = 23.5 C/W (with thermal pad soldered to PCB) ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 7 of 60 AD9786 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADGND ACVDD ACGND ACGND ADGND ADVDD ACVDD ADVDD AGND2 AGND1 AGND1 AVDD1 AGND2 AVDD2 AVDD1 AVDD2 IOUTA IOUTB DNC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 DNC CLKVDD 1 DNG 2 CLKVDD 3 CLKGND 4 CLK+ 5 CLK- 6 CLKGND 7 DGND 8 DVDD 9 P1B15 10 P1B14 11 P1B13 12 P1B12 13 P1B11 14 P1B10 15 DGND 16 DVDD 17 P1B9 18 P1B8 19 P1B7 20 PIN 1 IDENTIFIER 60 59 58 57 56 55 54 53 FSADJ REFIO RESET CSB SCLK SDIO SDO DGND DVDD P2B0 P2B1 P2B2 P2B3 P2B4 P2B5 DGND DVDD P2B6 P2B7 P2B8 AD9786 TOP VIEW (Not to Scale) 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DRVDD DATACLK IQSEL/P2B15 ONEPORTCLOCK/P2B14 P2B13 P2B12 P2B11 DNC = DO NOT CONNECT P2B10 P2B9 P1B6 P1B5 P1B4 P1B3 P1B2 P1B1 DVDD P1B0 DGND DVDD DGND Figure 2. Pin Configuration CLOCK Table 5. Clock Pin Function Descriptions Pin No. 5, 6 2 31 Name CLK+, CLK- DNC DATACLK Direction I I/O Description Differential Clock Input. Do Not Connect. DCLKEXT 02h[3] Mode 0 Pin configured for input of channel data rate or synchronizer clock. Internal clock synchronizer may be turned on or off with DCLKCRC (02h[2]). 1 Pin configured for output of channel data rate or synchronizer clock. Clock Domain 2.5 V. Clock Domain 0 V. 1, 3 4, 7 CLKVDD CLKGND Rev. 0 | Page 8 of 60 03152-0-002 AD9786 ANALOG Table 6. Analog Pin Function Descriptions Pin No. 59 60 70, 71 61 62, 79 63, 78 64, 77 65, 76 66, 75 67, 74 68, 73 69, 72 80 Name REFIO FSADJ IOUTB, IOUTA DNC ADVDD ADGND ACVDD ACGND AVDD2 AGND2 AVDD1 AGND1 DNC Direction A A A Description Reference. Full-Scale Adjust. Differential DAC Output Currents. Do Not Connect. Analog Domain Digital Content 2.5 V. Analog Domain Digital Content 0 V. Analog Domain Clock Content 2.5 V. Analog Domain Clock Content 0 V. Analog Domain Clock Switching 3.3 V. Analog Domain Switching 0 V. Analog Domain Quiet 3.3 V. Analog Domain Quiet 0 V. Do Not Connect. DATA Table 7. Data Pin Function Descriptions Pin No. 10-15, 18-24, 27-29 Name P1B15-P1B0 Direction I Description Input Data Port One. ONEPORT 02h[6] Mode 0 Latched data routed for I channel processing. 1 Latched data demultiplexed by IQSEL and routed for interleaved I/Q processing. ONEPORT IQPOL IQSEL/ 02h[6] 02h[1] P2B15 Mode (IQPOL = 0) 0 X X Latched data routed to Q channel Bit 15 (MSB) processing. 1 0 0 Latched data on Data Port One routed to Q channel processing. 1 0 1 Latched data on Data Port One routed to I channel processing. 1 1 0 Latched data on Data Port One routed to I channel processing. 1 1 1 Latched data on Data Port One routed to Q channel processing. ONEPORT 02h[6] 0 Latched data routed for Q channel Bit 14 processing. 1 Pin configured for output of clock at twice the channel data route. Input Data Port Two Bits 13-0. Digital Output Pin Supply, 2.5 V or 3.3 V. Digital Domain 2.5 V. Digital Domain 0 V. 32 IQSEL/P2B15 I 33 ONEPORTCLK/P2B14 I/O 34, 37-43, 46-51 30 9, 17, 26, 36, 44, 52 8, 16, 25, 35, 45, 53 P2B13-P2B0 DRVDD DVDD DGND I Rev. 0 | Page 9 of 60 AD9786 SERIAL INTERFACE Table 8. Serial Interface Pin Function Descriptions Pin No. 54 Name SDO Direction O Description SDIODIR CSB 00h[7] Mode 1 X High Impedance. 0 0 Serial Data Output. 0 1 High Impedance. SDIODIR CSB 00h[7] Mode 1 X High Impedance. 0 0 Serial Data Output. 0 1 Serial Data Input/Output Depending on Bit 7 of the Serial Instruction Byte. Serial Interface Clock. Serial Interface Chip Select. Resets entire chip to default state. 55 SDIO I/O 56 57 58 SCLK CSB RESET I I I Rev. 0 | Page 10 of 60 AD9786 DEFINITION OF SPECIFICATIONS Linearity Error (Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (or DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity A D/A converter is monotonic if the output either increases or remains constant as the digital input increases. Offset Error The deviation of the output current from the ideal of zero is called offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s. Gain Error The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s, minus the output when all inputs are set to 0s. Output Compliance Range The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (+25C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree C. For reference drift, the drift is reported in ppm per degree C. Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Settling Time The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Glitch Impulse Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s. Spurious-Free Dynamic Range The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Total Harmonic Distortion THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels (dB). Signal-to-Noise Ratio (SNR) S/N is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of fDATA (interpolation rate), a digital filter can be constructed which has a sharp transition band near fDATA/2. Images that would typically appear around fDAC (output data rate) can be greatly suppressed. Pass Band Frequency band in which any input applied therein passes unattenuated to the DAC output. Stop-Band Rejection The amount of attenuation of a frequency outside the pass band applied to the DAC, relative to a full-scale signal applied at the DAC input within the pass band. Group Delay Number of input clocks between an impulse applied at the device input and peak DAC output current. A half-band FIR filter has constant group delay over its entire frequency range Impulse Response Response of the device to an impulse applied to the input. Adjacent Channel Leakage Ratio (or ACLR) A ratio in dBc between the measured power within a channel relative to its adjacent channel. Rev. 0 | Page 11 of 60 AD9786 Complex Modulation The process of passing the real and imaginary components of a signal through a complex modulator (transfer function = ejwt = coswt + jsinwt) and realizing real and imaginary components on the modulator output. Hilbert Transform A function with unity gain over all frequencies, but with a phase shift of 90 degrees for negative frequencies, and a phase shift of -90 degrees for positive frequencies. Although this function can not be implemented ideally, it can be approximated with a short FIR filter with enough accuracy to be very useful in single sideband radio architectures. Complex Image Rejection In a traditional two part upconversion, two images are created around the second IF frequency. These images are redundant and have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Rev. 0 | Page 12 of 60 AD9786 TYPICAL PERFORMANCE CHARACTERISTICS TMIN to TMAX, AVDD1, AVDD2 = 3.3 V, ACVDD, ADVDD, CLKVDD, DVDD, DRVDD = 2.5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 doubly terminated, unless otherwise noted. 120 120 100 -6dBFS 80 -3dBFS 100 -6dBFS 80 -3dBFS SFDR (dBc) SFDR (dBc) 60 0dBFS 60 0dBFS 40 40 20 03152-PrD-035 20 03152-PrD-037 03152-PrD-041 03152-PrD-039 0 0 10 20 30 40 50 FREQUENCY (MHz) 60 70 80 0 0 10 20 30 40 50 FREQUENCY (MHz) 60 70 80 Figure 3. SFDR vs. Frequency, FDATA = 200 MSPS, 1x Interpolation 120 Figure 6. SFDR vs. Frequency, FDATA = 200 MSPS, 2x Interpolation 120 100 -3dBFS -6dBFS 100 -3dBFS 80 0dBFS -6dBFS 80 SFDR (dBc) 60 SFDR (dBc) 60 0dBFS 40 40 20 03152-PrD-038 20 0 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 45 0 0 10 20 30 40 FREQUENCY (MHz) 50 60 Figure 4. SFDR vs. Frequency, FDATA = 100 MSPS, 4x Interpolation 120 -6dBFS 100 -3dBFS 80 0dBFS Figure 7. SFDR vs. Frequency, FDATA = 125 MSPS, 4x Interpolation 120 -6dBFS 100 80 SFDR (dBc) SFDR (dBc) 0dBFS 60 -3dBFS 40 60 40 20 03152-PrD-040 20 0 0 5 10 15 FREQUENCY (MHz) 20 25 0 0 5 10 15 20 FREQUENCY (MHz) 25 30 Figure 5. SFDR vs. Frequency, FDATA = 50 MSPS, 8x Interpolation Figure 8. SFDR vs. Frequency, FDATA = 62.5 MSPS, 8x Interpolation Rev. 0 | Page 13 of 60 AD9786 100 95 90 85 80 -6dBFS -3dBFS 100 95 90 85 80 -6dBFS -3dBFS IMD (dBc) 75 70 65 60 55 03152-PrD-045 IMD (dBc) 75 70 0dBFS 65 60 55 50 0 20 40 60 80 100 120 FOUT (MHz) 140 160 180 200 03152-PrD-046 03152-PrD-039 03152-PrD-040 0dBFS 50 0 20 40 60 80 100 120 FOUT (MHz) 140 160 180 200 Figure 9. Out of Band SFDR, FDATA = 200 MSPS, 2x Interpolation 100 95 0dBFS 90 85 80 Figure 12. Out of Band SFDR, FDATA = 100 MSPS, 4x Interpolation 120 -6dBFS 100 -3dBFS 80 0dBFS IMD (dBc) SFDR (dBc) 03152-PrD-047 -6dBFS 60 75 70 65 60 55 -3dBFS 40 20 0 0 5 10 15 FREQUENCY (MHz) 20 25 50 0 20 40 60 80 100 120 140 160 180 200 220 240 260 FOUT (MHz) Figure 10. Out of Band SFDR, FDATA = 125 MSPS, 4x Interpolation 100 95 90 85 -6dBFS 80 IMD (dBc) 75 70 0dBFS 65 60 03152-PrD-049 Figure 13. Out of Band SFDR, FDATA = 50 MSPS, 8x Interpolation 120 -3dBFS 100 -3dBFS 80 -6dBFS SFDR (dBc) 60 0dBFS 40 20 55 50 0 20 40 60 80 100 120 140 160 180 200 220 240 260 FOUT (MHz) 0 0 10 20 30 40 FREQUENCY (MHz) 50 60 Figure 11. Out of Band SFDR, FDATA = 62.5 MSPS, 8x Interpolation Figure 14. Third Order IMD vs. Frequency, FDATA = 160 MSPS, 1x Interpolation Rev. 0 | Page 14 of 60 AD9786 100 95 -3dBFS 90 85 IMD (dBc) 100 95 -3dBFS -6dBFS -6dBFS 90 85 80 75 70 65 60 55 03152-PrD-044 80 IMD (dBc) 75 0dBFS 70 65 60 55 50 0 20 40 60 80 100 FOUT (MHz) 120 140 160 0dBFS 50 0 20 40 60 FOUT (MHz) 80 100 Figure 15. Third Order IMD vs. Frequency, FDATA = 160 MSPS, 2x Interpolation 100 95 90 85 80 IMD (dBc) Figure 18. Third Order IMD vs. Frequency, FDATA = 200 MSPS,1x Interpolation 100 95 -3dBFS -3dBFS 90 -6dBFS IMD (dBc) 85 80 75 70 -6dBFS 75 70 65 60 55 03152-PrD-045 0dBFS 65 0dBFS 60 55 50 0 20 40 60 80 100 120 FOUT (MHz) 140 160 180 200 03152-PrD-046 03152-PrD-048 50 0 20 40 60 80 100 120 FOUT (MHz) 140 160 180 200 Figure 19. Third Order IMD vs. Frequency, FDATA = 100 MSPS, 4x Interpolation 100 Figure 16. Third Order IMD vs. Frequency, FDATA = 200 MSPS, 2x Interpolation 100 95 0dBFS 90 85 -6dBFS 80 IMD (dBc) 95 90 85 80 IMD (dBc) 75 70 -3dBFS -6dBFS 75 70 65 60 55 50 0 20 40 60 80 100 120 140 160 180 200 220 240 260 FOUT (MHz) 03152-PrD-047 0dBFS -3dBFS 65 60 55 50 0 20 40 60 80 100 120 FOUT (MHz) 140 160 180 200 Figure 17. Third Order IMD vs. Frequency, FDATA = 125 MSPS, 4x Interpolation Figure 20. Third Order IMD vs. Frequency, FDATA = 50 MSPS, 8x Interpolation Rev. 0 | Page 15 of 60 03152-PrD-043 AD9786 100 95 90 85 -6dBFS DNL (LSBs) 03152-PrD-049 0.3 -3dBFS 0.2 0.1 0 -0.1 -0.2 -0.3 80 IMD (dBc) 75 70 0dBFS 65 60 55 50 0 20 40 60 80 100 120 140 160 180 200 220 240 260 FOUT (MHz) -0.4 0 8192 16384 24576 32768 40960 49152 57344 65536 CODE Figure 21. Third Order IMD vs. Frequency, FDATA = 62.5 MSPS, 8x Interpolation 0.6 -140 -145 Figure 24. Typical DNL NOISE SPECTRAL DENSITY (dBm/Hz) 0.4 -150 -155 -160 -165 FDATA = 78MSPS, 2x INTERPOLATION -170 -175 -180 0 10 20 30 40 50 60 ANALOG OUTPUT FREQUENCY (MHz) 70 80 03152-PrD-053 03152-PrD-054 0.2 FDATA = 78MSPS, 1x INTERPOLATION INL (LSBs) 0 -0.2 -0.4 03152-0-046 -0.6 0 8192 16384 24576 32768 40960 49152 57344 65536 CODE Figure 22. Typical INL -140 -145 -140 -145 Figure 25. Noise Spectral Density vs. Analog Input Frequency, FDATA = 78 MSPS, Interpolation = 1x NOISE SPECTRAL DENSITY (dBm/Hz) -150 FDATA = 156MSPS, 1x INTERPOLATION -155 -160 -165 FDATA = 156MSPS, 2x INTERPOLATION -170 -175 -180 0 20 40 60 80 100 120 ANALOG OUTPUT FREQUENCY (MHz) 140 160 03152-PrD-054 NOISE SPECTRAL DENSITY (dBm/Hz) -150 FDATA = 156MSPS, 1x INTERPOLATION -155 -160 -165 FDATA = 156MSPS, 2x INTERPOLATION -170 -175 -180 0 20 40 60 80 100 120 ANALOG OUTPUT FREQUENCY (MHz) 140 160 Figure 23. Noise Spectral Density vs. Analog Input Frequency, FDATA = 156 MSPS, Interpolation = 1x Figure 26. Noise Spectral Density vs. Analog Input Frequency, FDATA = 78 MSPS Interpolation = 2x Rev. 0 | Page 16 of 60 03152-0-047 AD9786 -140 10 -145 NOISE SPECTRAL DENSITY (dBm/Hz) 0 -10 -150 FDATA = 156MSPS, 1x INTERPOLATION -155 -160 -165 FDATA = 156MSPS, 2x INTERPOLATION -170 -175 -180 0 20 40 60 80 100 120 ANALOG OUTPUT FREQUENCY (MHz) 140 160 03152-PrD-054 -20 -30 1AVG -40 -50 -60 -70 -80 1 -90 -100 -110 START 100 kHz 19.9 MHz/ STOP 200 MHz 1MA Figure 30. Two Tones around 23 MHz, FDATA = 200 MSPS, 2x Interpolation, Low-Pass Digital Filter Mode Figure 27. Noise Spectral Density vs. Analog Input Frequency, FDATA = 156 MSPS Interpolation = 2x -60 10 0 -10 -65 -70 ACLR (dBc) 0dBFS -75 -3dBFS -20 -30 1AVG -40 -50 -60 1MA -80 -6dBFS -85 03152-PrD-055 -70 -80 -90 -100 -110 START 100 kHz 19.9 MHz/ STOP 200 MHz 1 -90 0 25 50 75 FOUT (MHz) 100 125 150 Figure 31. Two Tones around 177 MHz, FDATA = 200 MSPS, 2x Interpolation, High-Pass Digital Filter Mode Figure 28. ACLR for First Adjacent Band vs. Frequency, FDATA = 61.44 MSPS, 4x Interpolation -60 REF -29.82dBm *AVG Log 10dB/ *ATTEN 6dB -65 -70 ACLR (dBc) -6dBFS -75 0dBFS -3dBFS -80 AVERAGE 103 -85 03152-PrD-056 -90 0 20 40 60 80 100 120 FOUT (MHz) 140 160 180 200 PAVG 22 W1 S2 CENTER 51.44MHz *RES BW 30kHz VBW 300kHz REF BW 3.840MHz 3.840MHz 3.840MHz 3.840MHz Figure 29. ACLR for First Adjacent Band vs. Frequency, FDATA = 76.8 MSPS, 4x Interpolation SPAN 43.84MHz SWEEP 142.2ms (601 pts) LOWER dBm dBc -17.26 0.15 -74.24 -91.65 -75.73 -93.14 -75.67 -93.08 UPPER dBm dBc -74.63 -92.05 -75.67 -93.08 -76.38 -93.79 -75.75 -93.17 RMS RESULTS FREQ OFFSET CARRIER POWER 5.000MHz 10.000MHz -17.41dBm/ 15.000MHz 3.84MHz 20.000MHz 03152-PrD-060 03152-PrD-059 Figure 32. ACLR for Two WCDMA Carriers at 51.44 MHz, FDATA = 61.44 MSPS, 4x Interpolation Rev. 0 | Page 17 of 60 03152-0-031 AD9786 REF -22.76dBm *AVG Log 10dB/ *ATTEN 8dB REF -33.3dBm *AVG Log 10dB/ *ATTEN 6dB AC-COUPLED AC-COUPLED AVERAGE 104 AVERAGE 22 PAVG 104 W1 S2 PAVG 22 W1 S2 CENTER 20.00MHz *RES BW 30kHz VBW 300kHz REF BW 3.840MHz 3.840MHz 3.840MHz SPAN 33.84MHz SWEEP 109.8ms (601 pts) LOWER dBm dBc -79.00 -89.38 -80.78 -91.16 -79.71 -90.09 UPPER dBm dBc -79.63 -90.01 -81.77 -92.15 -81.45 -91.83 03152-0-028 CENTER 46.40MHz *RES BW 30kHz VBW 300kHz SPAN 53.84MHz SWEEP 174.6ms (601 pts) LOWER dBc dBm 0.22 -20.11 -0.60 -20.92 -72.68 -93.00 -72.74 -93.06 -73.05 -93.37 UPPER dBc dBm -0.16 -20.48 -72.05 -92.37 -72.85 -93.18 -72.55 -92.88 -72.02 -92.35 Figure 33. ACLR for Single WCDMA Carrier at 20 MHz, FDATA = 61.44 MSPS, 4x Interpolation REF -28.2dBm *AVG Log 10dB/ *ATTEN 6dB Figure 35. ACLR for Four-Carrier WCDMA Signal Near 50 MHz, FDATA = 61.44 MSPS, 4x Interpolation AVERAGE 22 PAVG 22 W1 S2 CENTER 142.88MHz *RES BW 30kHz VBW 300kHz REF BW 3.840MHz 3.840MHz 3.840MHz SPAN 33.84MHz SWEEP 109.8ms (601 pts) LOWER dBm dBc -72.33 -87.64 -72.41 -87.71 -72.67 -87.97 UPPER dBm dBc -72.13 -87.43 -73.02 -88.32 -73.50 -88.88 03152-0-030 RMS RESULTS FREQ OFFSET CARRIER POWER 5.000MHz 10.000MHz -15.30dBm/ 15.000MHz 3.84MHz Figure 34. ACLR for Single WCDMA Carrier at 142.88 MHz, FDATA = 61.44 MSPS, 4x Interpolation Rev. 0 | Page 18 of 60 03152-0-032 RMS RESULTS FREQ OFFSET CARRIER POWER 5.000MHz 10.000MHz -10.38dBm/ 15.000MHz 3.84 MHz RMS RESULTS FREQ OFFSET REF BW CARRIER POWER 5.000MHz -20.32dBm/ 10.000MHz 3.84MHz 15.000MHz 20.000MHz 25.000MHz 3.840MHz 3.840MHz 3.840MHz 3.840MHz 3.840MHz AD9786 SERIAL CONTROL INTERFACE Instruction Byte SDO (PIN 54) SDIO (PIN 55) SCLK (PIN 56) CSB (PIN 57) 03152-0-048 The instruction byte contains the following information: AD9786 SPI PORT INTERFACE Table 9. N1 0 0 1 1 N2 0 1 0 1 Description Transfer 1 Byte Transfer 2 Bytes Transfer 3 Bytes Transfer 4 Bytes Figure 36. AD9786 SPI Port Interface The AD9786 serial port is a flexible, synchronous serial communications port, allowing easy interface to many industrystandard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI(R) and Intel(R) SSR protocols. The interface allows read/write access to all registers that configure the AD9786. Single or multiple byte transfers are supported, as well as MSB first or LSB first transfer formats. The AD9786's serial interface port can be configured as a single pin I/O (SDIO) or two unidirectional pins for in/out (SDIO/SDO). R/W, Bit 7 of the instruction byte, determines whether a read or a write data transfer will occur after the instruction byte write. Logic high indicates read operation. Logic 0 indicates a write operation. N1, N0, Bits 6 and 5 of the instruction byte, determine the number of bytes to be transferred during the data transfer cycle. The bit decodes are shown in Table 10. Table 10. MSB I7 R/W I6 N1 I5 N0 I4 A4 I3 A3 I2 A2 I1 A1 LSB I0 A0 GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases to a communication cycle with the AD9786. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9786, coincident with the first eight SCLK rising edges. The instruction byte provides the AD9786 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9786. A logic high on the CS pin, followed by a logic low, will reset the SPI port timing to the initial state of the instruction cycle. This is true regardless of the present state of the internal registers or the other signal levels present at the inputs to the SPI port. If the SPI port is in the midst of an instruction cycle or a data transfer cycle, none of the present data will be written. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9786 and the system controller. Phase 2 of the communication cycle is a transfer of 1, 2, 3, or 4 data bytes as determined by the instruction byte. Using one multibyte transfer is the preferred method. Single byte data transfers are useful to reduce CPU overhead when register access requires one byte only. Registers change immediately upon writing to the last bit of each transfer byte. A4, A3, A2, A1, A0, Bits 4, 3, 2, 1, 0 of the instruction byte, determine which register is accessed during the data transfer portion of the communications cycle. For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the AD9786. SERIAL INTERFACE PORT PIN DESCRIPTIONS SCLK--Serial Clock. The serial clock pin is used to synchronize data to and from the AD9786 and to run the internal state machines. SCLK's maximum frequency is 20 MHz. All data input to the AD9786 is registered on the rising edge of SCLK. All data is driven out of the AD9786 on the falling edge of SCLK. CSB--Chip Select. Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. The SDO and SDIO pins will go to a high impedance state when this input is high. Chip select should stay low during the entire communication cycle. SDIO--Serial Data I/O. Data is always written into the AD9786 on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Bit 7 of register address 00h. The default is Logic 0, which configures the SDIO pin as unidirectional. SDO--Serial Data Out. Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9786 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. Rev. 0 | Page 19 of 60 AD9786 MSB/LSB TRANSFERS The AD9786 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by register address DATADIR (00h[6]). The default is MSB first. When this bit is set active high, the AD9786 serial port is in LSB first format. That is, if the AD9786 is in LSB first mode, the instruction byte must be written from least significant bit to most significant bit. Multibyte data transfers in MSB format can be completed by writing an instruction byte that includes the register address of the most significant byte. In MSB first mode, the serial port internal byte address generator decrements for each byte required of the multibyte communication cycle. Multibyte data transfers in LSB first format can be completed by writing an instruction byte that includes the register address of the least significant byte. In LSB first mode, the serial port internal byte address generator increments for each byte required of the multibyte communication cycle. The AD9786 serial port controller address will increment from 1Fh to 00h for multibyte I/O operations if the MSB first mode is active. The serial port controller address will decrement from 00h to 1Fh for multibyte I/O operations if the LSB first mode is active. CSB SCLK INSTRUCTION CYCLE DATA TRANSFER CYCLE SDIO R/W N0 N1 A0 A1 A2 A3 A4 D7 D6N D5N D30 D20 D10 D00 03152-0-004 03152-PrD-007 03152-PrD-006 SDO D7 D6N D5N D30 D20 D10 D00 Figure 37. Serial Register Interface Timing MSB First INSTRUCTION CYCLE CSB DATA TRANSFER CYCLE SCLK SDIO A0 A1 A2 A3 A4 N1 N0 R/W D00 D10 D20 D4N D5N D6N D7N 03152-0-005 SDO D00 D10 D20 D4N D5N D6N D7N Figure 38. Serial Register Interface Timing LSB First tDS CSB tSCLK NOTES ON SERIAL PORT OPERATION The AD9786 serial port configuration bits reside in Bits 6 and 7 of register address 00h. It is important to note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register may occur during the middle of communication cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. The same considerations apply to setting the software reset, SWRST (00h[5]) bit. All other registers are set to their default values, but the software reset does not affect the bits in Register Address 00h and 04h. It is recommended to use only single byte transfers when changing serial port configurations or initiating a software reset. SCLK tPWH tPWL tDS SDIO tDH INSTRUCTION BIT 6 INSTRUCTION BIT 7 Figure 39. Timing Diagram for Register Write CSB SCLK tDV SDIO SDO DATA BIT n DATA BIT n -1 Figure 40. Timing Diagram for Register Read Rev. 0 | Page 20 of 60 AD9786 MODE CONTROL (VIA SERIAL PORT) Table 11. Address COMMS FILTER DATA MODULATE RESERVED DCLKCRC 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 Bit 7 SDIODIR INTERP[1] DATAFMT CHANNEL RESERVED DATADJ[3] Bit 6 DATADIR INTERP[0] ONEPORT HILBERT RESERVED DATADJ[2] Bit 5 SWRST DCLKSTR MODDUAL RESERVED DATADJ[1] Bit 3 PDN ZSTUFF DCLKPOL DCLKEXT SIDEBAND MOD[1] RESERVED RESERVED DATADJ[0] MODSYNC Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CALMEN[0] XFEREN SMEMWR MEMADDR[4] MEMADDR[3] MEMDATA[4] MEMDATA[3] Bit 4 SLEEP Bit 2 HPFX8 DCLKCRC MOD[0] RESERVED MODADJ[2] Bit 1 HPFX4 IQPOL RESERVED MODADJ[1] Bit 0 EXREF HPFX2 CRAYDIN RESERVED MODADJ[0] CALMEMCK MEMRDWR MEMADDR MEMDATA DCRCSTAT CALSTAT MEMADDR[7] CALEN MEMADDR[6] CALMEM[1] XFERSTAT MEMADDR[5] MEMDATA[5] CALCKDIV[2] SMEMRD MEMADDR[2] MEMDATA[2] DCRCSTAT[2] CALCKDIV[2] FMEMRD MEMADDR[1] MEMDATA[1] DCRCSTAT[1] CALCKDIV[2] UNCAL MEMADDR[0] MEMDATA[0] DCRCSTAT[0] Table 12. COMMS(00) SDIODIR DATADIR SWRST SLEEP PDN EXREF Bit 7 6 5 4 3 0 Direction I I I I I I Default 0 0 0 0 0 0 Description 0: SDIO pin configured for input only during data transfer 1: SDIO configured for input or output during data transfer 0: Serial data uses MSB first format 1: Serial data uses LSB first format 1: Default all serial register bits, except addresses 00h and 04h 1: DAC output current off 1: All analog and digital circuitry, except serial interface, off 0: Internal band gap reference 1: External reference Table 13. FILTER(01) INTERP[1:0] Bit [7:6] Direction I Default 00 Description 00: No interpolation 01: Interpolation 2x 10: Interpolation 4x 11: Interpolation 8x 1: Zero Stuffing on 0: x8 interpolation filter configured for low pass 1: x8 interpolation filter configured for high pass 0: x4 interpolation filter configured for low pass 1: x4 interpolation filter configured for high pass 0: x2 interpolation filter configured for low pass 1: x2 interpolation filter configured for high pass ZSTUFF HPFX8 HPFX4 HPFX2 3 2 1 0 I I I I 0 0 0 0 Rev. 0 | Page 21 of 60 AD9786 Table 14. DATA(02) DATAFMT ONEPORT DCLKSTR DCLKPOL DCLKEXT DCLKCRC IQPOL Bit 7 6 5 4 3 2 1 Direction I I I I I I I Default 0 0 0 0 0 0 0 Description 0: Twos complement data format 1: Unsigned binary input data format 0: I and Q input data onto ports one and two, respectively 1: I and Q input data interleaved onto port one 0: DATACLK pin 12 mA drive strength 1: DATACLK pin 24 mA drive strength 0: Input data latched on DATACLK rising edge 1: Input data latched on DATACLK falling edge 0: DATACLK pin inputs channel data rate or modulator synchronizer clock 1: DATACLK pin outputs channel data rate or modulator synchronizer clock 0: With DATACLK pin as input, DATACLK clock recovery off 1: With DATACLK pin as input, DATACLK clock recovery on 0: In one port mode, IQSEL = 1 latches data into I channel, IQSEL = 0 latches data into Q channel 1: In one port mode, IQSEL = 0 latches data into I channel, IQSEL = 1 latches data into Q channel 0: Gray decoder off 1: Gray decoder on GRAYDIN 0 I 0 Table 15. MODULATE(03) CHANNEL Bit 7 Direction I Default 0 Description MODDUAL CHANNEL 03h [5] 03h[7] 0 0 I channel processing routed to DAC 0 1 Q channel processing routed to DAC 1 0 Modulator real output routed to DAC 1 1 Modulator imaginary output routed to DAC 1: With MODDUAL on, Hilbert transform on 0: Modulator uses a single channel 1: Modulator uses both I and Q channels 0: With MODDUAL on, lower sideband rejected 1: With MODDUAL on, upper sideband rejected 00: No modulation 01: fS/2 modulation 10: fS/4 modulation 11: fS/8 modulation HILBERT MODDUAL SIDEBAND MOD[1:0] 6 5 4 [3:2] I I I I 0 0 0 00 Rev. 0 | Page 22 of 60 AD9786 Table 16. DCLKCRC(05) DATADJ[3:0] Bit [7:4] Direction I Default 0000 Description DATACLK offset. Twos complement representation 0111: +7 : 0000: 0 : 1000: -8 0: Channel data rate clock synchronizer mode 1: State machine clock synchronizer mode Modulator coefficient offset fS/8 fS/4 fS/2 000 1 1 1 001 1/2 0 -1 010 0 -1 1 011 -1/2 0 -1 100 -1 1 1 101 -1/2 0 -1 110 0 -1 1 111 1/2 0 -1 MODSYNC MODADJ[2:0] 3 [2:0] I I 00 000 Table 17. VERSION(0D) VERSION[3:0] Bit [3:0] Direction O Default Description Hardware version identifier Table 18. CALMEMCK(OE) CALMEM Bit [5:4] Direction O Default 00 Description Calibration memory 00: Uncalibrated 01: Self calibration 10: Factory calibration 11: User input Calibration clock divide ratio from channel data rate 000: /32 001: /64 : 110: /2048 111: /4096 CALCKDIV[2:0] [2:0] I 00 Table 19. MEMRDWR(OF) CALSTAT CALEN XFERSTAT XFEREN SMEMWR SMEMRD FMEMRD UNCAL Bit 7 6 5 4 3 2 1 0 Direction O I O I I I I I Default 0 0 0 0 0 0 0 0 Description 0: Self calibration cycle not complete 1: Self calibration cycle complete 1: Self calibration in progress 0: Factory memory transfer not complete 1: Factory memory transfer complete 1: Factory memory transfer in progress 1: Write static memory data from external port 1: Read static memory to external port 1: Read factory memory data to external port 1: Use uncalibrated Rev. 0 | Page 23 of 60 AD9786 Table 20. MEMADDR(10) MEMADDR [7:0] Bit [7:0] Direction I/O Default 00000000 Description Address of factory or static memory to be accessed Table 21. MEMDATA(11) MEMDATA [5:0] Bit [5:0] Direction I/O Default 000000 Description Data or factory or static memory access Table 22. DCRCSTAT(12) DCRCSTAT (2) DCRCSTAT(1) DCRCSTAT(0) Bit 2 1 0 Direction O O O Default 0 0 0 Description 0: With DATACLK CRC on, lock has never been achieved. 1: With DATACLK CRC on, lock has been achieved at least once. 0: With DATACLK CRC on, system is currently not locked. 1: With DATACLK CRC on, system is currently locked. 0: With DATACLK CRC on, system is currently locked. 1: With DATACLK CRC on, system lost lock due to jitter. Rev. 0 | Page 24 of 60 AD9786 DIGITAL FILTER SPECIFICATIONS DIGITAL INTERPOLATION FILTER COEFFICIENTS 0 Table 23. Stage 1 Interpolation Filter Coefficients Lower Coefficient H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(13) H(14) H(15) H(16) H(17) H(18) H(19) H(20) H(21) H(22) Upper Coefficient H(43) H(42) H(41) H(40) H(39) H(38) H(37) H(36) H(35) H(34) H(33) H(32) H(31) H(30) H(29) H(28) H(27) H(26) H(25) H(24) H(23) Integer Value 9 0 -27 0 65 0 -131 0 239 0 -407 0 665 0 -1070 0 1764 0 -3273 0 10358 16384 -20 -40 -60 -80 -100 -120 -140 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 Figure 41. x2 Interpolation Filter Response 0 -20 -40 -60 -80 -100 -120 -140 -0.5 Lower Coefficient H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) Upper Coefficient H(19) H(18) H(17) H(16) H(15) H(14) H(13) H(12) H(11) Integer Value 19 0 -120 0 436 0 -1284 0 5045 8192 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 Figure 42. x4 Interpolation Filter Response 0 -20 -40 -60 -80 Table 25. Stage 3 Interpolation Filter Coefficients Lower Coefficient H(1) H(2) H(3) H(4) H(5) H(6) Upper Coefficient H(11) H(10) H(9) H(8) H(7) Integer Value 7 0 -53 0 302 512 -100 -120 -140 -0.5 03152-PrD-010 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 Figure 43. x8 Interpolation Filter Response Rev. 0 | Page 25 of 60 03152-PrD-009 Table 24. Stage 2 Interpolation Filter Coefficients 03152-PrD-008 AD9786 AD9786 CLOCK/DATA TIMING Table 26. Data Port Synchronization DCLKEXT 02h, Bit 3 1 1 0 0 0 0 MODSYNC 05h, Bit 3 0 1 0 0 1 1 DCLKCRC 02h, Bit 2 X X 0 1 0 1 Mode DATACLK Master Modulator Master External Sync Mode DATACLK Slave Low Setup/Hold Modulator Slave Function Channel data rate clock output Modulator synchronization DATACLK output DATACLK inactive, DACCLK synchronous with external data DATACLK input, data rate clock, Data Recovery On DATACLK input, input data synchronous with DATACLK Input modulator synchronizer DATACLK input Two-Port Data Input Mode, DATACLK Master With the interpolation set to 1x, the DATACLK output is a delayed and inverted version of DACCLK at the same frequency. Note that DACCLK refers to the differential clock inputs applied at Pins 5 and 6. As Figure 44 and Figure 45 show, there is a constant delay between the edges of DACCLK and DATACLK. The DCLKPOL bit (Reg 02 Bit 4) allows the data to be latched into the AD9786 on either the rising or falling edge of DACCLK. With DCLKPOL = 0, the data is latched in on the falling edge of DACCLK, as shown in Figure 44. With DCLKPOL = 1, as shown in Figure 45, data is latched in on the rising edge of DACCLK. The setup and hold times are always with respect to the latching edge of DACCLK. DACCLKIN DATACLKOUT tD = 6ns TYP tS = -0.5ns MIN t12 tH = 2.9ns MIN DATA 03152-0-040 03152-0-045 Figure 44. Data Timing, 1x Interpolation, DCLKPOL = 0 DACCLKIN tS = -300ps TYP tH = 2.9ns TYP DATA Figure 45. Data Timing, 1x Interpolation, DCLKPOL = 1 Rev. 0 | Page 26 of 60 AD9786 With the interpolation set to 2x, the DACCLK input runs at twice the speed of the DATACLK. Data is latched into the digital inputs of the AD9786 on every other rising edge of DACCLK, as shown in Figure 47 and Figure 48. With DCLKPOL = 0, as shown in Figure 47, the latching edge of DACCLK is the rising edge that occurs just before the falling edge of DATACLK. With DCLKPOL = 1, as in Figure 48, the latching edge of DACCLK is the rising edge of DACCLK that occurs just before the rising edge of DATACLK. The setup and hold time values are identical to those in Figure 44 and Figure 45. Note that there is a slight difference in the delay from the rising edge of DACCLK to the falling edge of DATACLK, and the delay from the rising edge of DACCLK to the rising edge of DATACLK. As Figure 46 shows, the DATACLK duty cycle is slightly less than 50%. This is true in all modes. With the interpolation set to 4x or 8x, the DACCLK input runs at 4x or 8x the speed of the DATACLK output. The data is latched in on a rising edge of DACCLK, similar to the 2x interpolation mode. However, the latching edge is every fourth edge in 4x interpolation mode and every eighth edge in the 8x DACCLKIN 03152-PrD-068 interpolation mode. Similar to operation in the 2x interpolation mode, with DCLKPOL = 0, the latching edge of DACCLK is the rising edge that occurs just before the falling edge of DATACLK. With DCLKPOL = 1, the latching edge of DACCLK is the rising edge that occurs just before the rising edge of DATACLK. The setup and hold time values are identical to those in 1x and 2x interpolation. Figure 46. DATACLKOUT tD = 5ns TYP tS = -0.5ns MIN tH = 2.9ns MIN DATA 03152-0-020 03152-0-022 Figure 47. Data Timing, 2x Interpolation, DCLKPOL = 0 DACCLKIN DATACLKOUT tD = 6ns TYP tS = -0.5ns MIN tH = 2.9ns MIN DATA Figure 48. Data Timing, 2x Interpolation, DCLKPOL = 1 Rev. 0 | Page 27 of 60 AD9786 AD9786 DATACLK Slave Mode, Data Recovery On DATACLK (Pin 31) can be used as an input in order to synchronize multiple AD9786s. A clock generated by an AD9786 operating in master mode, or a clock from an external source, can be used to drive DATACLK. In this mode, there are two clocks required to be applied to the AD9786. A clock running at the DAC sample rate, referred to as DACCLK, must be applied to the differential inputs (Pins 5 and 6) of the AD9786. As described above, a clock at the input sample rate must also be applied to Pin 31 (DATACLK). An internal DLL synchronizes the two applied clocks. The timing relationships between the input data, DATACLK, and DACCLK are given in Figure 49 and Figure 50. Note that DCLKPOL (Reg 02h, Bit 4) can be used to select the edge of DACCLK upon which the input data is latched. There is a defined setup and hold window with respect to input data and the latching edge of DACCLK. There is also a required timing relationship between DATACLK and DACCLK. This is referred to in Figure 49 and Figure 50 as tST and tHT (setup and hold for transition). As an example, with DCLKPOL set to logic 0, the input data will latch on the first rising edge of DACCLK which occurs greater than 1.5 ns before the falling edge of DATACLK. DACCLK should not be given a rising edge in the window of 500 ps to 1.5 ns before the latching edge (falling when DCLKPOL = 0, rising when DCLKPOL = 1) of DATACLK. Failure to account for this timing relationship may result in corrupt data. There are three status bits available for read which allow the user to verify DLL lock. These are Bits 0, 1, and 2 (DCRCSTAT) in Reg 12h. DACCLKIN DATACLKIN tHT = 1.5ns MIN tST = -500ps MIN tS = 0.0ns MIN tH = 3.2ns MIN DATA 03152-0-023 03152-0-042 Figure 49. Slave Mode Timing, 2x Interpolation, DCLKPOL = 0 DACCLKIN DATACLKIN tST = -1.0ns MIN tHT = 2.0ns MIN tH = 3.2ns MIN DATA tS = 0.0ns MIN Figure 50. Slave Mode Timing, 2x Interpolation, DCLKPOL = 1 Rev. 0 | Page 28 of 60 AD9786 AD9786 Low Setup/Hold Mode (DATACLK input, data recovery off) Some applications may require that digital input data be synchronized with the DATACLK input, rather than DACCLK. For these applications, the AD9786 can be programmed for Low Setup/Hold Mode by entering the values in Table 26 into the SPI registers. With data recovery off and the MODSYNC bit set to logic 1, the AD9786 will latch data in on the rising or falling edge of DATACLK input, depending on the state of DCLKPOL. The timing is similar to the slave mode with data recovery on. There is still a required timing relationship between DACCLK and DATACLK in, as shown in Figure 51 and Figure 52. As these show, the digital input data is latched in on the DATACLK edge, rather than DACCLK. One advantage of this mode is that the setup and hold numbers for the input data with respect to DATACLK are much smaller than the similar specs in the slave/clock recovery mode. Note that in this mode, the DATAADJ bits have no effect. DACCLKIN DATACLKIN tST = 3.0ns MIN tHT = 0.0ns MIN tH = 2.8ns MIN 03152-0-043 03152-0-044 tS = -1.1ns MIN DATA Figure 51. Low Setup and Hold Mode Timing, 2x Interpolation, DCLKPOL = 0 DACCLKIN DATACLKIN tST = 2.0ns MIN tHT = 1.0ns MIN tS = -1.8ns MIN tH = 3.1ns MIN DATA Figure 52. Low Setup and Hold Mode Timing, 2x Interpolation, DCLKPOL = 1 Rev. 0 | Page 29 of 60 AD9786 AD9786 External Sync Mode There is one additional timing mode in which the AD9786 may be used. In the External Sync Mode, the DATACLK is programmed as an input, but is not used. Applying a DATACLK input while in this mode will have no effect. The digital input data is synchronized solely to the DACCLK input. With 1x interpolation, this means that the data input will be latched on every rising edge of DACCLK. The challenge is that the user has no way of knowing exactly which edge is the latching edge when the interpolating filters are in use. In 2x, 4x, and 8x interpolation modes, the latching edge of DACCLK will be either every 2nd, 4th, or 8th edge, respectively. With the 2 ns keep out window, as shown in Figure 53, there is a strong possibility of violating setup and hold times, especially at high speeds. It is recommended that users sense the DAC output noise floor for setup and hold violations. If setup and hold is violated, DCLKPOL can be switched. The effect of switching the state of DCLKPOL is that the latching edge will be moved by one, two, or four DACCLK cycles if the AD9786 is in 2x, 4x, or 8x interpolation modes, respectively. Note that in this mode, the DATAADJ bits have no effect. DACCLKIN tS = -300ps TYP tH = 2.9ns TYP DATA 03152-0-045 Figure 53. External Sync Mode with 2x Interpolation DATAADJUST Synchronization When designing the digital interface for high speed DACs, care must be taken to ensure that the DAC input data meets setup and hold requirements. Often, compensation must be used in the clock delay path to the digital engine driving the DAC. The AD9786 has the on-chip capability to vary the latching edge of DACCLK. With the interpolation function enabled, this allows the user the choice of multiple edges upon which to latch the data. For instance, if the AD9786 is using 8x interpolation, the user may latch from one of eight edges before the rising edge of DATACLK, or seven edges after this rising edge. The specific edge upon which data is latched is controlled by SPI Register 05h, Bits 7:4. Table 27 shows the relationship of the latching edge of DACCLK and DATACLK with the various settings of the DATAADJ bits. Table 27. DATAADJ Values for Latching Edge Sync Bit 7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SPI Reg 05h Bit 6 Bit 5 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Bit 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Latching Edge wrt DATACLK 0 +1 +2 +3 +4 +5 +6 +7 -8 -7 -6 -5 -4 -3 -2 -1 Rev. 0 | Page 30 of 60 AD9786 Note that the data in Figure 44 to Figure 53 was taken with the DATAADJ default of 0000. With DCLKPOL = 0, the latching edge of DACCLK is just previous to the rising edge of DATACLK; with DCLKPOL = 1, the latching edge of DACCLK is just previous to the falling edge of DATACLK. Table 27 describes the values available for 8x interpolation which gives a choice of 16 edges to sync data. With 4x interpolation, there will be a choice of 8 edges, and the relevant values from Table 27 will be 0000, 0010, 0100, 0110, 1000, 1010, 1100, and 1110. These options will allow latching edge placement from +3 cycles to -4 cycles. In 2x interpolation, 4 edges will be available, and the relevant values from Table 27 will be 0000, 0100, 1000, and 1100. The choices for DATAADJ are diminished to +1 cycle to -2 cycles. Figure 54, Figure 55, and Figure 56 show the alignment for the latching edge of DACCLK with 4x interpolation and different settings for DATAADJ. In Figure 54, the AD9786 is in DATACLK Master Mode. DATAADJ is set to 0000, with DCLKPOL set to 0 so that the latching edge of DACCLK is immediately before the rising edge of DATACLK. The data transitions shown in Figure 54 are synchronous with the DACCLK, so that DACCLK and input data are constant with respect to each other. The only visible change when DATAADJ is altered is that DATACLK moves, indicating the latching edge has moved as well. Note that in DATACLK Master Mode, when DATAADJ is altered, the latching edge with respect to DATACLK remains the same. RISING EDGE OF DATACLK CONCURRENT WITH LATCHING EDGE OF DACCLK RISING EDGE OF DATACLK CONCURRENT WITH LATCHING EDGE OF DACCLK DACCLK LATCHING EDGE DATA TRANSITION Figure 55. DATAADJ = 1111 Figure 56 shows the same conditions, with DATAADJ set to 0001, thus moving DATACLK to the right in the plot. This indicates that it occurs one DACCLK cycle after it did in Figure 54. In this case, the latching edge of DACCLK moves forward in time one cycle. RISING EDGE OF DATACLK CONCURRENT WITH LATCHING EDGE OF DACCLK DACCLK LATCHING EDGE 03152-PrD-072 DATA TRANSITION DACCLK LATCHING EDGE Figure 56. DATAADJ = 0001 Figure 54. DATAADJ = 0000 Figure 55 shows the same conditions, but with DATAADJ set to 1111. This moves DATACLK to the left in the plot, indicating that it occurs one DACCLK cycle before it did in Figure 54. As explained previously, the latching edge of DACCLK also moves one cycle back in time. 03152-0-006 DATA TRANSITION Rev. 0 | Page 31 of 60 03152-PrD-073 AD9786 Interpolation Modes Table 28. Interpolation Modes INTERP[1] 0 0 1 1 INTERP[0] 0 1 0 1 Mode No Interpolation x2 Interpolation x4 Interpolation x8 Interpolation A DAC shapes its output with a sinc function, having a null at the sampling frequency of the DAC. The higher the DAC sampling rate compared to the input signal bandwidth, the less the DAC sinc function will shape the output. The higher the interpolation rate, the more input data images fall in the interpolation filter stop band and are rejected; the bandwidth between passed images is larger with higher interpolation factors. The sinc function shaping is also reduced with a higher interpolation factor. Table 29. Sinc Shaping at Band Edge of Interpolation Filters Mode No Interpolation x2 Interpolation x4 Interpolation x8 Interpolation Sinc Shaping at 0.43fSIN (dB) -2.8241 -0.6708 -0.1657 -0.0413 Bandwidth to First Image fSIN 2fSIN 4fSIN 8fSIN Interpolation is the process of increasing the number of points in a time domain waveform by approximating points between the input data points, on a uniform time grid. This produces a higher output data rate. Applied to an interpolation DAC, a digital interpolation filter is used to approximate the interpolated points, having an output data rate increased by the interpolation factor. Interpolation filter responses are achieved by cascading individual digital filter banks, whose filter coefficients are given in Table 23, Table 24, and Table 25. Filter responses are shown in Figure 57, which shows the interpolation filters of the AD9786 under different interpolation rates, normalized to the input data rate, fSIN. The digital filter's frequency domain response exhibits symmetry about half the output data rate and dc. It will cause images of the input data to be shaped by the interpolation filter's frequency response. This has the advantage of causing input data images, which fall in the stop band of the digital filter to be rejected by the stop-band attenuation of the interpolation filter; input data images falling in the interpolation filter's pass band will be passed. In band-limited applications, the images at the output of the DAC must be limited by an analog reconstruction filter. The complexity of the analog reconstruction filter is determined by the proximity of the closest image to the required signal band. Higher interpolation rates yield larger stop-band regions, suppressing more input images and resulting in a much relaxed analog reconstruction filter. Rev. 0 | Page 32 of 60 AD9786 SINC RESPONSE NO INTERPOLATION 0 -50 -100 -150 -8 0 -50 -100 -150 -8 0 -50 -100 -150 -8 0 -50 -100 -150 -8 -6 -4 -2 0 2 4 6 8 fSIN INTERP[1] = 1 INTERP[0] = 1 03152-PrD-011 INTERP[1] = 0 INTERP[0] = 0 -6 -4 -2 -0 2 4 6 8 fSIN x2 INTERPOLATION INTERP[1] = 0 INTERP[0] = 1 -6 -4 -2 0 2 4 6 8 fSIN x4 INTERPOLATION INTERP[1] = 1 INTERP[0] = 0 -6 -4 -2 0 2 4 6 8 fSIN x8 INTERPOLATION Figure 57. Interpolation Modes REAL AND COMPLEX SIGNALS A complex signal contains both magnitude and phase information. Given two signals at the same frequency, if a point in time can be taken such that the signal leading in phase is cosinusoidal and the lagging signal is sinusoidal, then information pertaining to the magnitude and phase of a combination of the two signals can be derived; the combination of the two signals can be considered a complex signal. The cosine and sine can be represented as a series of exponentials; recalling that a multiplication by j is a counterclockwise rotation about the Re/Im plane, the phasor representation of a complex signal, with frequency f, can be shown in Figure 58. Im Im Re C A/2 A/2 2ft A Re -f 0 +f FREQUENCY A/2 C = Ae2ft = Acos(2ft) + jAsin(2ft) 2 e+j2ft + e-j2ft 2j 2 A 2 03152-PrD-012 The cosine term represents a signal on the real plane with mirror symmetry about dc; this is referred to as the real, inphase or I component of a complex signal. The sine term represents a signal on the imaginary plane with mirror asymmetry about dc; this term is referred to as the imaginary, quadrature or Q complex signal component. The AD9786 has two channels of interpolation filters, allowing both I and Q components to be shaped by the same filter transfer function. The interpolation filters' frequency response is a real transfer function. Two DACs are required to represent a complex signal. A single DAC can only synthesize a real signal. When a DAC synthesizes a real signal, negative frequency components fold onto the positive frequency axis. If the input to the DAC is mirror symmetrical about dc, the folded negative frequency components fold directly onto the positive frequency components in phase producing constructive signal summation. If the input to the DAC is not mirror symmetric about dc, negative frequency components may not be in phase with positive frequency components and will cause destructive signal summation. Different applications may or may not benefit from either type of signal summation. A/2 Acos(2ft) = A Asin(2ft) = A e+j2ft + e-j2ft = = A [e+j2ft + e-j2ft] [je+j2ft + e-j2ft] Figure 58. Complex Phasor Representation Rev. 0 | Page 33 of 60 AD9786 MODULATION MODES Table 30. Single Channel Modulation MODDUAL 0 0 0 0 0 0 0 0 CHANNEL 0 0 0 0 1 1 1 1 MOD[1] 0 0 1 1 0 0 1 1 MOD[0] 0 1 0 1 0 1 0 1 Mode I Channel, no modulation I Channel, modulation by fDAC/2 I Channel, modulation by fDAC/4 I Channel, modulation by fDAC/8 Q Channel, no modulation Q Channel, modulation by fDAC/2 Q Channel, modulation by fDAC/4 Q Channel, modulation by fDAC/8 Either channel of the AD9786's interpolation filter channels can be routed to the DAC and modulated. In single channel operation the input data may be modulated by a real sinusoid; the input data and the modulating sinusoid will contain both positive and negative frequency components. A double sideband output results when modulating two real signals. At the DAC output the positive and negative frequency components will add in phase resulting in constructive signal summation. As the modulating sinusoidal frequency becomes a larger fraction of the DAC update rate, fDAC, the more the sinc function of the DAC shapes the modulated signal bandwidth, and the closer the first image moves. As the AD9786 interpolation filter's pass band represents a large portion of the input data's Nyquist band, under certain modulation and interpolation modes it is possible for modulated signal bands to touch or overlap images if sufficient interpolation is not used. Figure 59 shows the effects of fDAC/8 modulation when using 8x interpolation. Figure 60 to Figure 62 show the effects of real modulation under all interpolation modes. The sinc shaping at the corners of the modulated signal band, and the bandwidth to the first image for those cases whose pass bands do not touch or overlap, are tabulated. Table 31. Synthesis Bandwidth vs. Interpolation Modes Modulation none fDAC/2 fDAC/4 fDAC/8 None fSIN fSIN Overlap Overlap Interpolation x2 x4 2 fSIN 4 fSIN 2 fSIN 4 fSIN Touching 2 fSIN Overlap Touching x8 8 fSIN 8 fSIN 4 fSIN 6 fSIN Table 32. Modulated Pass-Band Edges Sinc Shaping (Lower/Upper) Modulation None fDAC/2 fDAC/4 fDAC/8 None 0 -2.8241 -0.0701 -22.5378 Overlap Overlap Interpolation x2 x4 0 0 -0.6708 -0.1657 -1.1932 -2.3248 -9.1824 -6.1190 Touching -0.2921 -1.9096 Overlap Touching x8 0 -0.0413 -3.0590 -4.9337 -0.5974 -1.3607 -0.0727 -0.4614 Rev. 0 | Page 34 of 60 AD9786 FILTERED INTERPOLATION IMAGES -7fDAC/8 -3fDAC/4 -5fDAC/8 -fDAC/2 -3fDAC/8 -fDAC/4 -fDAC/8 0 fDAC/8 fDAC/4 3fDAC/8 fDAC/2 5fDAC/8 3fDAC/4 7fDAC/8 -fDAC fS/8 MODULATION fDAC 03152-PrD-014 -7fDAC/8 -3fDAC/4 -5fDAC/8 -3fDAC/8 Figure 59. Double Sideband Modulation 0 -50 -100 -150 -8 0 -50 -100 -150 -8 0 -50 -100 -150 -8 0 -50 -100 -150 -8 -6 -4 -2 0 2 4 -6 -4 -2 0 2 4 -6 -4 -2 0 2 4 -6 -4 -2 0 2 4 NO INTERPOLATION INTERP[1] = 0 INTERP[0] = 0 MOD[1] = 0 MOD[0] = 1 6 8 fSIN INTERP[1] = 0 INTERP[0] = 1 MOD[1] = 0 MOD[0] = 1 x2 INTERPOLATION 6 8 fSIN INTERP[1] = 1 INTERP[0] = 0 MOD[1] = 0 MOD[0] = 1 x4 INTERPOLATION 6 8 fSIN INTERP[1] = 1 INTERP[0] = 1 MOD[1] = 0 MOD[0] = 1 x8 INTERPOLATION 6 8 fSIN Figure 60. Real Modulation by fDAC/2 Under All Interpolation Modes Rev. 0 | Page 35 of 60 03152-PrD-013 -fDAC/2 -fDAC/4 -fDAC/8 fDAC/8 fDAC/4 3fDAC/8 fDAC/2 5fDAC/8 3fDAC/4 7fDAC/8 -fDAC fDAC AD9786 0 -50 -100 -150 -8 0 -50 -100 -150 -8 0 -6 -4 -2 0 2 4 6 -6 -4 -2 0 2 4 6 NO INTERPOLATION INTERP[1] = 0 INTERP[0] = 0 MOD[1] = 1 MOD[0] = 0 8 fSIN INTERP[1] = 0 INTERP[0] = 1 MOD[1] = 1 MOD[0] = 0 8 fSIN INTERP[1] = 1 INTERP[0] = 0 MOD[1] = 1 MOD[0] = 0 -6 -4 -2 0 2 4 6 8 fSIN INTERP[1] = 1 INTERP[0] = 1 MOD[0] = 0 -6 -4 -2 0 2 4 6 8 fSIN 03215-PrD-015 03152-PrD-017 x2 INTERPOLATION x4 INTERPOLATION -50 -100 -150 -8 0 -50 -100 -150 -8 x8 INTERPOLATION MOD[1] = 1 Figure 61. Real Modulation by fDAC/4 Under All Interpolation Modes 0 -50 -100 -150 -8 0 -50 -100 -150 -8 0 -50 -100 -150 -8 0 -50 -100 -150 8- -6 -4 -2 0 2 4 -6 -4 -2 0 2 4 -6 -4 -2 0 2 4 -6 -4 -2 0 2 4 NO INTERPOLATION INTERP[1] = 0 INTERP[0] = 0 MOD[1] = 1 MOD[0] = 0 6 8 fSIN INTERP[1] = 0 INTERP[0] = 1 MOD[1] = 1 MOD[0] = 0 8 fSIN 6 x4 INTERPOLATION INTERP[1] = 1 INTERP[0] = 0 MOD[1] = 1 MOD[0] = 0 8 fSIN 6 x8 INTERPOLATION INTERP[1] = 1 INTERP[0] = 1 MOD[1] = 1 MOD[0] = 0 6 8 fSIN x2 INTERPOLATION Figure 62. Real Modulation by fDAC/8 Under All Interpolation Modes Rev. 0 | Page 36 of 60 AD9786 Table 33. Dual Channel Complex Modulation MODSING 0 0 0 0 0 0 0 0 REALIMAG 0 0 0 0 1 1 1 1 MOD[1] 0 0 1 1 0 0 1 1 MOD[0] 0 1 0 1 0 1 0 1 Mode Real output, no modulation Real output, modulation by fDAC/2 Real output, modulation fDAC/4 Real output, modulation fDAC/8 Image output, no modulation Image output, modulation by fDAC/2 Image output, modulation by fDAC/4 Image output, modulation by fDAC/8 In dual channel mode, the two channels may be modulated by a complex signal, with either the real or imaginary modulation result directed to the DAC. Assume initially, as in Figure 63, that the complex modulating signal is defined for a positive frequency only. This causes the output spectrum to be translated in frequency by the modulation factor only. No additional sidebands are created as a result of the modulation process, and therefore the bandwidth to the first image from the baseband bandwidth is the same as the output of the interpolation filters. Furthermore, pass bands will not overlap or touch. The sinc shaping at the corners of the modulated signal band are tabulated in Table 34. Figure 64, Figure 65, and Figure 66 show the effects of complex modulation with varying interpolation rates. Table 34. Complex Modulated Pass-Band Edges Sinc Shaping (Lower/Upper) Modulation None fDAC/2 fDAC/4 fDAC/8 None 0 -2.8241 -0.0701 -22.5378 -0.4680 -6.0630 -1.3723 -4.9592 Interpolation x2 x4 0 0 -0.6708 -0.1657 -1.1932 -2.3248 -9.1824 -6.1190 -0.0175 -0.2921 -3.3447 -1.9096 -0.1160 -0.0044 -1.7195 -0.7866 x8 0 -0.0413 -3.0590 -4.9337 -0.5974 -1.3607 -0.0727 -0.4614 FILTERED INTERPOLATION IMAGES -7fDAC/8 -3fDAC/4 -5fDAC/8 -fDAC/2 -3fDAC/8 -fDAC/4 -fDAC/8 fDAC/8 fDAC/4 3fDAC/8 fDAC/2 5fDAC/8 3fDAC/4 7fDAC/8 -fDAC 0 fS/8 MODULATION NO NEGATIVE SIDEBAND fDAC 03152-PrD-018 -7fDAC/8 -3fDAC/4 -5fDAC/8 -fDAC/2 -3fDAC/8 -fDAC/4 -fDAC/8 fDAC/8 fDAC/4 3fDAC/8 fDAC/2 5fDAC/8 3fDAC/4 7fDAC/8 -fDAC 0 Figure 63. Complex Modulation Rev. 0 | Page 37 of 60 fDAC AD9786 0 -50 -100 -150 -8 0 -50 -100 -150 -8 0 -50 -100 -150 -8 -6 -4 -2 0 2 4 6 -6 -4 -2 0 2 4 -6 -4 -2 0 2 4 x2 INTERPOLATION INTERP[1] = 0 INTERP[0] = 1 MOD[1] = 0 MOD[0] = 1 6 8f SIN x4 INTERPOLATION INTERP[1] = 1 INTERP[0] = 0 MOD[1] = 0 MOD[0] = 1 6 8f SIN x8 INTERPOLATION INTERP[1] = 1 INTERP[0] = 1 MOD[1] = 0 MOD[0] = 1 8f 03152-PrD-019 SIN Figure 64. Complex Modulation by fDAC/2 Under All Interpolation Modes 0 -50 -100 -150 -8 0 -50 -100 -150 -8 0 -50 -100 -150 -8 -6 -4 -2 0 2 4 6 -6 -4 -2 0 2 4 -6 -4 -2 0 2 4 x2 INTERPOLATION INTERP[1] = 0 INTERP[0] = 1 MOD[1] = 1 MOD[0] = 0 6 8 fSIN x4 INTERPOLATION INTERP[1] = 1 INTERP[0] = 0 MOD[1] = 1 MOD[0] = 0 6 8 fSIN x8 INTERPOLATION INTERP[1] = 1 INTERP[0] = 1 MOD[1] = 1 MOD[0] = 0 8 fSIN 03152-PrD-020 03152-PrD-021 Figure 65. Complex Modulation by fDAC/4 Under All Interpolation Modes 0 -50 -100 -150 -8 0 -50 -100 -150 -8 0 -50 -100 -150 -8 -6 -4 -2 0 2 4 6 -6 -4 -2 0 2 4 -6 -4 -2 0 2 4 x2 INTERPOLATION INTERP[1] = 0 INTERP[0] = 1 MOD[1] = 1 MOD[0] = 1 6 8 fSIN x4 INTERPOLATION INTERP[1] = 1 INTERP[0] = 0 MOD[1] = 1 MOD[0] = 1 6 8 fSIN x8 INTERPOLATION INTERP[1] = 1 INTERP[0] = 1 MOD[1] = 1 MOD[0] = 1 8 fSIN Figure 66. Complex Modulation by fDAC/8 Under All Interpolation Modes Rev. 0 | Page 38 of 60 AD9786 POWER DISSIPATION The AD9786 has seven power supply domains: two 3.3 V analog domains (AVDD1 and AVDD2), two 2.5 V analog domains (ADVDD and ACVDD), one 2.5 V clock domain (CLKVDD), and two digital domains (DVDD, which runs from 2.5 V, and DRVDD, which can run from 2.5 V or 3.3 V). The current needed for the 3.3 V analog supplies, AVDD1 and AVDD2, is consistent across speed and varying modes of the AD9786. Nominally, the current for AVDD1 is 29 mA across all speeds and modes, while the current for AVDD2 is 20 mA. The current for the 2.5 V analog supplies and the digital supplies varies depending on speed and mode of operation. Figure 67, Figure 68, and Figure 69 show this variation. Note that CLKVDD, ADVDD, and ACVDD vary with clock speed and interpolation rate, but not with modulation rate. IDVDD (mA) 60 8x 4x 2x 50 40 30 1x 20 10 03152-PrD-078 03152-PrD-079 0 0 25 50 75 100 125 150 FDATA (MSPS) 175 200 225 250 Figure 68. CLKVDD Supply Current vs. Clock Speed and Interpolation Rates 03152-PrD-077 425 400 375 350 325 300 275 250 225 200 175 150 125 100 75 50 25 0 0 25 50 30 4x fs/8 8x fs/8 8x fs/4 4x 4x fs/4 2x fs/4 20 2x fs/8 25 8x 4x 2x IDVDD (mA) IDVDD (mA) 8x 2x 15 1x 10 1x 5 0 0 25 50 75 100 125 150 FDATA (MSPS) 175 200 225 250 75 100 125 150 FDATA (MSPS) 175 200 225 250 Figure 67. DVDD Supply Current vs. Clock Speed, Interpolation, and Modulation Rates Figure 69. ADVDD and ACVDD Supply Current vs. Clock Speed and Interpolation Rates Rev. 0 | Page 39 of 60 AD9786 FILTERED INTERPOLATION IMAGES -7fDAC/8 -3fDAC/4 -5fDAC/8 -fDAC/2 -3fDAC/8 -fDAC/4 -fDAC/8 fDAC/8 fDAC/4 3fDAC/8 fDAC/2 5fDAC/8 3fDAC/4 7fDAC/8 -fDAC 0 fS/8 MODULATION -7fDAC/8 -3fDAC/4 -5fDAC/8 -fDAC/2 -3fDAC/8 -fDAC/4 -fDAC/8 fDAC/8 fDAC/4 3fDAC/8 fDAC/2 5fDAC/8 3fDAC/4 7fDAC/8 -fDAC 0 fS/4 MODULATION fDAC 03152-PrD-022 -7fDAC/8 -3fDAC/4 -5fDAC/8 -fDAC/2 -3fDAC/8 -fDAC/4 -fDAC/8 fDAC/8 fDAC/4 3fDAC/8 fDAC/2 5fDAC/8 3fDAC/4 7fDAC/8 -fDAC 0 Figure 70. Complex Modulation with Negative Frequency Aliasing Table 35. Dual Channel Complex Modulation with Hilbert Hilbert 0 1 Mode Hilbert transform off Hilbert transform on When complex modulation is performed, the entire spectrum is translated by the modulation factor. If the resulting modulated spectrum is not mirror symmetric about dc, when the DAC synthesizes the modulated signal, negative frequency components will fall on the positive frequency axis and can cause destructive summation of the signals, as shown in Figure 70. For some applications, this can distort the modulated output signal. X = Ae j2(f + fm)t Im Re A/2 A/2 A/2 A/2 00 A/2 A/2 A/2 f f A Y = Ae j2(f + fm)t - /2 Im Re Z = HILBERT(Y) Im Re A/2 A/2 A/2 00 03152-PrD-023 the original complex modulation output all negative frequency components can be folded in phase to the positive frequency axis before being synthesized by the DAC. When the DAC synthesizes the modulated output there are no negative frequency components to fold onto the positive frequency axis out of phase; consequently no distortion is produced as a result of the modulation process. 0 ALIASED NEGATIVE FREQUENCY INTERPOLATION IMAGES -50 C=X-Z Re dBFS Im -100 A fDAC fDAC f A/2 A/2 f -150 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 Figure 71. Negative Frequency Image Rejection Figure 72. Negative Frequency Aliasing Distortion Referring to Figure 71, by performing a second complex modulation with a modulating signal having a fixed /2 phase difference, Figure (Y), relative to the original complex modulation signal, Figure (X), taking the Hilbert transform of the new resulting complex modulation, and subtracting it from Figure 72 shows this effect at the DAC output for a mirror asymmetric signal about dc produced by complex modulation without a Hilbert transform. The signal bandwidth was narrowed to show the aliased negative frequency interpolation images. Rev. 0 | Page 40 of 60 03152-PrD-024 AD9786 In contrast, Figure 73 shows the same waveform with the Hilbert transform applied. Clearly, the aliased interpolation images are not present. 0 Figure 74 and Figure 75 show the gain of the Hilbert transform versus frequency. Gain is essentially flat, with a pass-band ripple of 0.1 dB over the frequency range 0.07 x Sample Rate to 0.43 x Sample Rate. Figure 76 shows the phase response of the Hilbert transform implemented in the AD9786. The phase response for positive frequencies begins at -90 at 0 Hz, followed by a linear phase response (pure time delay) equal to nine filter taps (nine DACCLK cycles). For negative frequencies, the phase response at 0 Hz is +90, again followed by a linear phase delay of nine filter taps. To compensate for the unwanted 9-cycle delay, an equal delay of nine taps is used in the AD9786 digital signal path opposite to the Hilbert transform. This delay block is noted as t on the block diagram on the first page of this data sheet. 10 0 -10 -20 -30 -50 dBFS -100 -150 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 Figure 73. Effects of Hilbert Transform If the output of the AD9786 is to be used with a quadrature modulator, negative frequency images are cancelled without the need of a Hilbert transform. HILBERT TRANSFORM IMPLEMENTATION The Hilbert transform on the AD9786 is implemented as a 19-coefficient FIR. The coefficients are given in Table 36. Table 36. Coefficient H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(13) H(14) H(15) H(16) H(17) H(18) H(19) Integer Value -6 0 -17 0 -40 0 -91 0 -318 0 318 0 91 0 40 0 17 0 6 03152-PrD-025 -40 -50 -60 -70 -80 -90 -100 100 200 300 400 500 600 700 800 900 1000 03152-PrD-074 03152-PrD-075 Figure 74. Hilbert Transform Gain 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 100 200 300 400 500 600 700 800 900 1000 Figure 75. Hilbert Transform Ripple The transfer function of an ideal Hilbert transform has a +90 phase shift for negative frequencies, and a -90 phase shift for positive frequencies. Because of the discontinuities that occur at 0 Hz and at 0.5 x Sample Rate, any real implementation of the Hilbert Transform trades off bandwidth versus ripple. Rev. 0 | Page 41 of 60 AD9786 4 3 2 1 0 -1 -2 03152-PrD-076 A baseband double sideband signal modulated to IF increases IF filter complexity and reduces power efficiency. If the baseband signal is complex, a single sideband IF modulation can be used, relaxing IF filter complexity and increasing power efficiency. The AD9786 has the ability to place the baseband single sideband complex signal either above the IF frequency or below it. Figure 78, Figure 79, and Figure 80 illustrate this. -3 -4 100 0 200 400 600 800 1000 1200 Figure 76. Phase Response of Hilbert Transform -50 Table 37. Dual Channel Complex Modulation Sideband Selection Sideband 0 1 Mode Lower IF sideband rejected Upper IF sideband rejected dBFS -100 I AD9786 Re() 0 03152-PrD-026 -150 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 Figure 78. Upper IF Sideband Rejected 90 LO Q AD9786 Im() 0 Figure 77. AD9786 Driving Quadrature Modulator -150 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 Figure 79. Lower IF Sideband Rejected BASEBAND IF -fIF 0 fIF SIDEBAND = 0 -fIF fIF 0 SIDEBAND = 1 03152-PrD-029 -fIF 0 Figure 80. IF Quadrature Modulation of Real and Complex Baseband Signals Rev. 0 | Page 42 of 60 fIF 03152-PrD-028 The AD9786 can be configured to drive a quadrature modulator representatively, as in Figure 77. Where two AD9786s are used with one AD9786 producing the real output, the second AD9786 produces the imaginary output. By configuring the AD9786 as a complex modulator coupled to a quadrature modulator, IF image rejection is possible. The quadrature modulator acts as the real part of a complex modulation producing a double sideband spectrum at the local oscillator (LO) frequency, with mirror symmetry about dc. -50 dBFS -100 03152-PrD-027 AD9786 Master/Slave, Modulator/DATACLK Master Modes In applications where two or more AD9786s are used to synthesize several digital data paths, it may be necessary to ensure that the digital inputs to each device are latched synchronously. In complex data processing applications, digital modulator phase alignment may be required between two AD9786s. In order to allow data synchronization and phase alignment, only one AD9786 should be configured as a master device, providing a reference clock for another slave-configured AD9786. With synchronization enabled, a reference clock signal is generated on the DATACLK pin of the master. The DATACLK pins on the slave devices act as inputs for the reference clock generated by the master. The DATACLK pin on the master and all slaves must be directly connected. All master and slave devices must have the same clock source connected to their respective CLK+/CLK- pins. When configured as a master, the reference clock generated may take one of two forms. In modulator master mode, the reference clock will be a square wave with a period equal to 16 cycles of the DAC update clock. Internal to the AD9786 is a 16-state finite state machine, running at the DAC update rate. This state machine generates all internal and external synchronization clocks and modulator phasings. The rising edge of the master reference clock is time aligned to the internal state machine's state zero. Slave devices use the master's reference clock to synchronize their data latching and align their modulator's phase by aligning their local state machine state zero to the master. The second master mode, DATACLK master mode, generates a reference clock that is at the channel data rate. In this mode, the slave devices align their internal channel data rate clock to the master. If modulator phase alignment is needed, a concurrent serial write to all slave devices is necessary. To achieve this, the CSB pin on all slaves must be connected together and a group serial write to the MODADJ register bits must be performed; the modulator coefficient alignment is updated on the next rising edge of the internal state machine following a successful serial write, see Figure 81. Modulator master mode does not need a concurrent serial write as slaves lock to the master phase automatically. In a slave device, the local channel data rate clock and the digital modulator clock are created from the internal state machine. The local channel data rate clock is used by the slave to latch digital input data. At high data rates, the delay inherent in the signal path from master to slave may cause the slave to lag the master when acquiring synchronization. To account for this, an integer number of the DAC update clock cycles may be programmed into the slave device as an offset. The value in DATADJ allows the local channel data rate clock in the slave device to advance by up to eight cycles of the DAC clock or to be delayed by up to seven cycles, see Figure 84. The digital modulator coefficients are updated at the DAC clock rate and decoded in sequential order from the state machine according to Figure 83. The MODADJ bits can be used to align a different coefficient to the finite state machine's zero state as shown in Figure 84. DAC CLOCK STATE MACHINE MODULATOR COEFFICIENT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 -1 0 1 0 -1 0 1 0 -1 0 1 0 -1 0 -1 0 1 0 -1 0 1 0 -1 0 1 0 -1 0 1 0 MODADJ STATE MACHINE CYCLE CLOCK CHANNEL DATA RATE CLOCK 000 000 Figure 81. Synchronous Serial Modulator Phase Alignment Rev. 0 | Page 43 of 60 03152-PrD-030 AD9786 DATADJ[3:0] 0000 1111 0001 DAC CLOCK RECEIVED CHANNEL DATA RATE CLOCK LOCAL CHANNEL DATA RATE CLOCK -1 +1 03152-PrD-031 Figure 82. Local Channel Data Rate Clock Synchronized with Offset STATE DECODE fs/8 fs/4 fs/2 0 1 0 0 0 1 0 2 1/ 2 1 3 0 4 0 2 1 5 0 6 -1/ 2 3 7 0 8 -1 4 2 1 9 0 10 -1/ 2 5 11 0 12 0 6 3 13 0 14 -1/ 2 7 15 0 03152-PrD-032 Figure 83. Digital Modulator State Machine Decode MODADJ[2:0] 000 010 101 DAC CLOCK STATE MACHINE MODULATOR COEFFICIENT STATE MACHINE CYCLE CLOCK 14 15 0 1 2 3 15 0 1 15 0 1 2 -1 0 1 0 -1 0 0 -1 0 1 0 -1 0 03152-PrD-033 Figure 84. Local Modulator Coefficient Synchronized with Offset Rev. 0 | Page 44 of 60 AD9786 OPERATING THE AD9786 REV F EVALUATION BOARD This section helps the user get started with the AD9786 evaluation board. Because it is intended to provide starter information to power up the board and verify correct operation, a description of some of the more advanced modes of operation has been omitted. PECL CLOCK DRIVER The AD9786 system clock is driven from an external source via connector S1. The AD9786 Evaluation Board includes an OnSemiconductor MC100EPT22 PECL clock driver. In the factory, the evaluation board is set to use this PECL driver as a single-ended-to-differential clock receiver. The PECL driver can be set to run from 2.5 V from the CLKVDD power connector, or 3.3 V from the VDD3IN power connector. This setting is done via jumper, JP2, situated next to the CLKVDD power connector, and by setting input bias resistors R23 and R4 on the evaluation board. The factory default is for the PECL driver to be powered from CLKVDD at 2.5 V (R23 = 90.9 , R4 = 115 ). To operate the PECL driver with a 3.3 V supply, R23 must be replaced with a 115 resistor and R4 must be replaced with a 90.9 resistor, as well as changing the position of JP2. The schematic of the PECL driver section of the evaluation board is shown in Figure 85. A low jitter sine wave should be used as the clock source. Care must be taken to make sure the clock amplitude does not exceed the power supply rails for the PECL driver. POWER SUPPLIES The AD9786 Rev F Evaluation Board has five power supply connectors, labeled AVDD1, AVDD2, (ACVDD, ADVDD), CLKVDD, and DVDD. The AD9786 itself actually has seven power supply domains. To reconcile the power supply domains on the chip with the power supply connectors on the evaluation board, use Table 38. Additionally, the DRVDD power supply on the AD9786 is used to supply power for the digital input bus. DRVDD can be run from 2.5 V or 3.3 V. On the evaluation board, DRVDD is jumper selectable by JP1, just to the left of the chip on the evaluation board. With the jumper set to the 3.3 V position, DRVDD chip receives its power from VDD3IN. With the jumper set to the 2.5 V position, DRVDD receives its power from AVDIN. CLKVDDS CLKVDDS CLK+ C32 0.1F ACLKX R23 115 7 MC100EPT22 1 COND;5 U2 CLKVDDS;8 2 R5 50 CLK- Figure 85. PECL Driver on AD9786 Rev E Evaluation Board Table 38. Evaluation Board Label/ PS Domain on Chip DVDD CLKVDD (ACVDD ADVDD) AVDD2 AVDD1 Nominal Power Supply Voltage (V) 2.5 2.5 2.5 3.3 3.3 Description SPI port Clock circuitry Analog circuitry containing clock and digital interface circuitry Switching analog circuitry Analog output circuitry Rev. 0 | Page 45 of 60 03152-PrD-080 R4 90.9 R6 50 R7 50 AD9786 DATA INPUTS Digital data inputs to the AD9786 are accessed on the evaluation board through connectors J1 and J2. These are 40 pin right angle connectors that are intended to be used with standard ribbon cable connectors. The input levels should be either 3.3 V or 2.5 V CMOS, depending on the setting of the DRVDD jumper JP1. The data format is selectable through Register 02h, Bit 7 (DATAFMT). With this bit set to a default 0, the AD9786 assumes that the input data is in twos complement format. With this bit set to 1, data should be input in offset binary format. When the evaluation board is first powered up and the clock and data are running, it is recommended that the proper operating current is verified. Depress reset switch SW1 to ensure that the AD9786 is in the default mode. The default mode for the AD9786 is for the interpolation set to 1x. The modulator is turned off in the default mode. The nominal operating currents for the evaluation board in the power-up default mode are shown in Table 39. Additionally, the DRVDD power supply on the AD9786 is used to supply power for the digital input bus. DRVDD can be run from 2.5 V or 3.3 V. On the evaluation board, DRVDD is jumper selectable by JP1, just to the left of the chip on the evaluation board. With the jumper set to the 3.3 V position, DRVDD chip receives its power from VDD3IN. With the jumper set to the 2.5 V position, DRVDD receives its power from AVDIN. SERIAL PORT SW1 is a hard reset switch that sets the AD9786 to its default state. It should be used every time the AD9786 power supply is cycled or the clock is interrupted, or if new data is to be written via the SPI port. Set the SPI software to read back data from the AD9786 and verify that when the software is run, the expected values are read back. Table 39. Nominal Operating Currents in Power-Up Default Mode Evaluation Board Power Supply DVDD CLKVDD ACVDD and ADVDD AVDD1 AVDD2 50 MSPS 26 78 1 30 27 Nominal Current @ Speed (mA) 100 MSPS 150 MSPS 49 74 83 87 4 6 30 30 27 27 200 MSPS 99 92 8 30 27 Table 40. SPI Registers Register 01h Bit 7 INTERP[1] Bit 6 INTERP[0] Bit 5 Bit 4 Bit 3 Bit 0 Rev. 0 | Page 46 of 60 AD9786 ANALOG OUTPUT The analog output of the AD9786 is accessed via connector S3. Once all settings are selected and current levels and SPI port functionality are verified, the analog signal at S3 can be viewed. For most of the AD9786's applications, a spectrum analyzer is the instrument of choice to verify proper performance. A typical spectral plot is shown in Figure 86, with the AD9786 synthesizing a two-tone signal in the default mode with a 200 MSPS sample rate. A single tone CW signal should provide output power of approximately +0.5 dBm to the spectrum analyzer. If the spectrum does not look correct at this point, the data input may be violating setup and hold times with respect to the input clock. To correct this, the user should vary the input data timing. If this is not possible, SPI Register 02h, Bit 4 (DCLKPOL) can be inverted. This bit controls the clock edge upon which the data is latched. If these methods do not correct the spectrum, it is unlikely that the issue is timing related. This note should then be reread to verify that all instructions have been followed. MARKER 1 [T1] REF LVL -84.96dBm 193.00170300MHz 0dBm RBW 30kHz VBW 30kHz SWT 560ms UNIT dBm A RF ATT 20dB 0 -10 -20 -30 -40 1AVG -50 -60 -70 -80 -90 -100 -110 -120 START 100MHz 19.9MHz/ STOP 200MHz 1MA Figure 86. Typical Spectral Plot Rev. 0 | Page 47 of 60 03152-0-025 AD9786 ADVDD2_IN L8 JP30 ADVDD JP33 ACVDD TP12 FERRITE BLK C75 0.1F C76 0.1F CLKVDDS FERRITE L12 TP1 RED AVD3 L11 SMAEDGE AGND2; 3,4,5 2.5V FERRITE + C45 22F 16V C47 0.1F S7 DVDD_IN L9 JP34 DVDD VDD DVDD AVDD2 ACLKX TP16 BLK JP36 DVDDS DRVDD C48 0.1F TP18 BLK JP1 2 1 3 AB C32 0.1F TP13 RED CLK+ SMAEDGE DGND; 3,4,5 2.5VN FERRITE + C46 22F 16V TP17 BLK S5 R5 50 R7 50 R6 50 CLK- R23 90.9 MC100EPT22 1 7 CGND; 5 U2 CLKVDDS; 8 2 R4 115 ADVDD3_IN L3 JP9 AVDD2 AVD2 JP2 2 A C29 22F 16V C34 0.1F FERRITE + TP3 BLK 1 B CLKVDDS L6 3 C67 0.1F C35 0.1F TP2 RED CLKVDDS + C28 4.7F 6.3V SMAEDGE FERRITE AGND2; 3,4,5 + C65 3.3V 22F 16V S9 MC100EPT22 3 6 U2 4 CLKVDDS; 8 CGND; 5 Figure 87. Power Supply Distribution Rev F Evaluation Board Rev. 0 | Page 48 of 60 L2 JP10 AVDD C68 0.1F TP5 BLK JP7 JP8 JP6 L14 VAL L13 VAL L1 CLKVDD JP5 C69 0.1F TP7 BLK TP6 RED CVD TP30 TP31 TP32 TP33 TP34 BLK BLK BLK BLK BLK L10 VAL TP4 RED AVD1 AGND; 3,4,5 3.3VQ FERRITE + C64 22F 16V CGND;3,4,5 2.5VQ FERRITE + C63 22F 16V L7 VAL POWER INPUT FILTERS AVDD_IN S10 SMAEDGE 1 2 CLKVDD_IN SMAEDGE S11 TP36 BLK TP35 BLK 03152-0-007 R2 10k CLKVDD CLKVDD C12 0.1F 1 CLKVDD1 2 LPF R3 10k AVDD C62 0.1F C4 0.1F C18 0.001F C61 0.001F AVDD2 C13 0.1F C11 0.1F DNC2 80 ADVDDP1 79 ADVDD C14 0.1F + C2 10F 6.3V ACCOMP1 78 ACVDDP1 77 ACOM2P1 76 AVDD2P1 75 ACOM2P12 74 AVDD1P2 73 ACOM1P11 72 IOUTA 71 IOUTB 70 ACOM1P21 69 AVDD1P1 68 ACOM2P2 67 AVDD2P2 66 ACCOM2P2 65 ACVDDP2 64 ADCOMP2 63 ADVDDP2 62 DNC1 61 FSADJ 60 REFIO 59 RESET 58 SPI_CSB 57 SP-CLK 56 SP-SDI 55 SP-SDO 54 27 P1B2 28 P1B1 29 P1B0LSB 30 DRVDD1 31 DCLK-PLLL C42 0.1F C27 1pF C49 0.1F C20 0.001F C55 0.001F TP15 WHT JP22 1 2 3 T1 T1-1T JP23 6 CLK- 7 CLKCOM2 5 CLK+ 4 CLKCOM1 +C1 10F 6.3V 6 5 4 C19 0.1F R1 50 3 CLKVDD2 ACLKX S1 CGND; 3,4,5 CLK- DVDD 8 DCOM1 9 DVDD1 R10 49.9 R9 49.9 CLK+ AD15 AD14 AD13 AD12 AD11 14 P1B11 15 P1B10 16 DCOM2 17 DVDD2 13 P1B12 12 P1B13 11 P1B14 10 P1B15MSB 3 P + ACVDD C17 0.1F C15 0.1F + 1 T3 C66 10F 6.3V S 4 6 AGND; 3,4,5 S3 OUT1 R42 49.9 C3 10F 6.3V DRVDD DVDD C33 0.1F C25 0.001F AD08 AD07 AD06 AD05 AD04 AD03 TP14 WHT DVDD AD02 AD01 AD00 S2 C24 0.001F C39 0.1F 25 DCOM3 26 DVDD3 24 P1B3 23 P1B4 22 P1B5 21 P1B6 20 P1B7 19 P1B8 AD10 + C31 10F 6.3V C54 0.001F C41 0.1F + C9 10F 6.3V AD09 18 P1B9 ADTL1-12 + C10 10F 6.3V C26 0.001F C40 0.1F TP11 WHT T2B NC = 5 TP8 WHT TP10 WHT RESET SPCSB SPCLK SPSDI SPSDO + C30 10V 10F 4 5 R8 C16 2k 0.1F 0.01% 6 S P 1 TTWB-1-B AGND; 3,4,5 S8 TP29 BLK 3 Figure 88. AD9786 Local Circuitry Rev F Evaluation Board Rev. 0 | Page 49 of 60 + C8 10F 6.3V DCOM6 53 DVDD6 52 P2B0LSB 51 P2B1 50 32 P2B15MSB-IQSEL 33 P2B14-OPCLK DVDD BD00 BD01 P2B2 49 P2B3 48 BD02 BD03 C38 0.1F C21 0.001F + C5 10F 6.3V DGND; 3,4,5 DATACLK BD15 3 2 B DVDD JP27 BD12 C23 0.001F C36 0.1F BD11 BD10 BD09 OPCLK 03152-0-008 BD14 A BD13 JP28 1 S6 IQ S4 OPCLK DGND; 3,4,5 34 P2B13 35 DCOM4 36 DVDD4 37 P2B12 38 P2B11 39 P2B10 40 P2B9 P2B4 47 P2B5 46 DCOM5 45 DVDD5 44 P2B6 43 P2B7 42 U1 P2B8 41 BD04 BD05 RESET BD06 BD07 BD08 C37 0.1F 4 3 C22 0.001F DVDD + C6 10F 6.3V SW1 2 1 FLOAT; 5 DRVDD OPCLK_3 + C7 10F 6.3V AD9786BTSP AD9786 AD9786 AX15 R26 100 R30 100 R31 100 R32 100 R33 100 AX08 AX14 R27 100 R28 100 R29 100 AX09 JP3 AX10 JP12 AX11 AX13 AX12 RCOM R1 R2 R3 R4 R5 R6 R7 R8 R9 2 3 4 5 6 7 8 9 10 RP5 DNP RCOM R1 R2 R3 R4 R5 R6 R7 R8 R9 2 3 4 5 6 7 8 9 10 RP7 DNP DATA-A 1 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 AX15 AX14 AX13 AX12 AX11 AX10 AX09 AX08 AX07 AX06 AX05 AX04 AX03 AX02 AX01 AX00 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 RP1 22 RP1 22 RP1 22 RP1 22 RP1 22 RP1 22 RP1 22 RP1 22 RP2 22 RP2 22 RP2 22 RP2 22 RP2 22 RP2 22 RP2 22 RP2 22 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 AD15 AD14 AD13 AD12 AD11 AD10 AD09 AD08 AD07 AD06 AD05 AD04 AD03 AD02 AD01 AD00 39 RCOM R1 R2 R3 R4 R5 R6 R7 R8 R9 AX00 RCOM 37 1 2 3 4 5 6 7 8 9 10 RP6 DNP 1 2 3 4 5 6 7 8 9 10 RP8 DNP R1 R2 R3 R4 R5 R6 R7 R8 R9 RIBBON J1 AX07 R38 100 AX06 R39 100 R40 100 R34 100 R44 100 R43 100 R41 100 R46 100 AX01 JP21 JP19 AX02 AX05 AX03 03152-0-009 AX04 Figure 89. Digital Data Port A Input Terminations Rev F Evaluation Boards Rev. 0 | Page 50 of 60 AD9786 BX15 R62 100 R57 100 R58 100 R59 100 R63 100 BX08 BX14 R61 100 R60 100 R64 100 BX09 JP26 BX10 JP31 BX11 BX13 BX12 RCOM R1 R2 R3 R4 R5 R6 R7 R8 R9 2 3 4 5 6 7 8 9 RP12 10 DNP RCOM R1 R2 R3 R4 R5 R6 R7 R8 R9 2 3 4 5 6 7 8 9 10 RP9 DNP DATA-B 1 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 BX15 BX14 BX13 BX12 BX11 BX10 BX09 BX08 BX07 BX06 BX05 BX04 BX03 BX02 BX01 BX00 SDO CLK 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 RP3 22 RP3 22 RP3 22 RP3 22 RP3 22 RP3 22 RP3 22 RP3 22 RP4 22 RP4 22 RP4 22 RP4 22 RP4 22 RP4 22 RP4 22 RP4 22 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 BD15 BD14 BD13 BD12 BD11 BD10 BD09 BD08 BD07 BD06 BD05 BD04 BD03 BD02 BD01 BD00 CSB RCOM R1 R2 R3 R4 R5 R6 R7 R8 R9 BX00 RCOM SDI 1 2 3 4 5 6 7 8 9 10 RP11 DNP 1 2 3 4 5 6 7 8 9 10 RP10 DNP R1 R2 R3 R4 R5 R6 R7 R8 R9 RIBBON J2 BX07 R55 100 BX06 R54 100 R53 100 R56 100 R51 100 R49 100 R47 100 R52 100 BX01 JP25 JP24 BX02 BX05 BX03 03152-0-010 BX04 Figure 90. Digital Data Port B Input Terminations Rev F Evaluation Board Rev. 0 | Page 51 of 60 AD9786 DVDDS 4 PRE 3 5 J Q 1 CLK 2 6 K Q_ CLR 15 DGND;8 74LCX112 DVDDS;16 U7 + C52 4.7F 6.3V C53 0.1F OPCLK OPCLK_3 10 PRE 11 9 J Q 13 CLK 12 7 K Q_ CLR 14 74LCX112 DGND;8 U7 DVDDS;16 U5 U5 R50 9k R48 9k R45 9k SPI PORT P1 1 2 3 4 5 6 SPCSB 2 1 12 13 74AC14 SPCLK 4 U5 3 74AC14 10 U5 11 74AC14 SPSDI 6 U5 5 74AC14 8 U5 9 74AC14 SPSDO 1 U6 2 74AC14 13 U6 12 DVDDS 74AC14 R21 10k R20 10k 3 U6 4 11 74AC14 U6 10 74AC14 5 U6 6 9 74AC14 U6 8 74AC14 74AC14 Figure 91. SPI and One-Port Clock Circuitry Rev F Evaluation Board Rev. 0 | Page 52 of 60 03152-0-011 + C43 4.7F 6.3V C50 0.1F + C44 4.7F 6.3V C51 0.1F AD9786 Figure 92. PCB Assembly, Primary Side Rev F Evaluation Board Figure 93. PCB Assembly, Secondary Side Rev F Evaluation Board Rev. 0 | Page 53 of 60 03152-0-013 03152-PrD-012 AD9786 Figure 94. PCB Assembly, Layer 1 Metal Rev F Evaluation Board Rev. 0 | Page 54 of 60 03152-0-014 AD9786 Figure 95. PCB Assembly, Layer 1 Metal Rev F Evaluation Board Rev. 0 | Page 55 of 60 03152-0-014 AD9786 Figure 96. PCB Assembly, Layer 2 Metal (Ground Plane) Rev F Evaluation Board Rev. 0 | Page 56 of 60 03152-0-016 AD9786 Figure 97. PCB Assembly, Layer 3 Metal (Power Plane) Rev F Evaluation Board Rev. 0 | Page 57 of 60 03152-0-017 AD9786 Figure 98. PCB Assembly, Layer 4 Metal (Power Plane) Rev F Evaluation Board Rev. 0 | Page 58 of 60 03152-0-018 AD9786 Figure 99. PCB Assembly, Layer 5 Metal (Ground Plane) Rev F Evaluation Board Rev. 0 | Page 59 of 60 03152-0-019 AD9786 OUTLINE DIMENSIONS 0.75 0.60 0.45 SEATING PLANE 1.20 MAX 80 1 14.00 SQ 12.00 SQ 61 60 60 61 80 1 PIN 1 TOP VIEW (PINS DOWN) BOTTOM VIEW 6.00 SQ 20 21 40 41 41 40 21 20 0.15 0.05 1.05 1.00 0.95 0.20 0.09 COPLANARITY 0.08 0.50 BSC 0.27 0.22 0.17 7 3.5 0 GAGE PLANE 0.25 COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD Figure 100. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP/EP] (SV-80) Dimensions shown in millimeters ORDERING GUIDE Model AD9786BSV AD9786BSVRL AD9786-EB Temperature Range -40C to +85C -40C to +85C Package Description 80-Lead TQFP 80-Lead TQFP Evaluation Board Package Option SV-80 SV-80 (c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03152-0-7/04(0) Rev. 0 | Page 60 of 60 |
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