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TM
ICM7249
5 1/2 Digit LCD, Micro-Power Event/Hour Meter
Description
The ICM7249 Timer/Counter is intended for long-term battery-supported industrial applications. The ICM7249 typically draws 1A during active timing or counting, due to Intersil' special low-power design techniques. This allows more than 10 years of continuous operation without battery replacement. The chip offers four timing modes, eight counting modes and four test modes. The ICM7249 is a 48 lead device, powered by a single DC voltage source and controlled by a 32.768kHz quartz crystal. No other external components are required. Inputs to the chip are TTL-compatible and outputs drive standard direct drive LCD segments.
August 1997
Features
* Hour Meter Requires Only 4 Parts Total * Micropower Operation: < 1A at 2.8V (Typ) * 10 Year Operation On One Lithium Cell. 21/2 Year Battery Life with Display Connected * Directly Drives 51/2 Digit LCD * 14 Programmable Modes of Operation * Times Hrs., 0.1 Hrs., 0.01 Hrs., 0.1 Mins. * Counts 1's, 10's, 100's, 1000's * Dual Function Input Circuit - Selectable Debounce for Counter - High-Pass Filter for Timer * Direct AC Line Triggering with Input Resistor * Winking "Timer Active" Display Output * Display Test Feature
Pinout
ICM7249 (PDIP) TOP VIEW
b6/c6 f5 g5 e5 d5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 DT 47 S/S 46 C3 45 C2 44 C1 43 C0 42 GND 41 OSC OUTPUT 40 OSC INPUT 39 VDD 38 BP 37 W 36 a1 35 b1 34 c1 33 d1 32 e1 31 g1 30 f1 29 a2 28 b2 27 c2 26 d2 25 e2
Applications
* AC or DC Hour Meters * AC or DC Totalizers * Portable Battery Powered Equipment * Long Range Service Meters
c5 b5 a5
Ordering Information
PART NUMBER ICM7249IPM TEMP. RANGE ( oC) -20 to 85 PACKAGE 48 Ld PDIP PKG. NO. E48.6
f4 g4 e4 d4 c4 b4 a4 f3 g3 e3 d3 c3 b3 a3 f2 g2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2001. All Rights Reserved
File Number
3170.1
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ICM7249 Functional Block Diagram
OSC IN OSC OUT S/S V+ VOLTAGE REGLATOR SWITCH DEBOUNCE 16 OSC 1Hz 215 DIVIDER 6 SEC CONTROL DECODE
/6
32Hz
/6
C0 C1 C2 C3
V-
/2
1 SEG DEC
/ 10
4 7 SEG DEC
/ 10
7 SEG DEC
/ 10
7 SEG DEC
/ 10
7 SEG DEC
/ 10
4 7 SEG DEC
/ 10
WINK SEG 1Hz
/ 10
DISPLAY TEST
/ 10
32Hz
B6
F5
G5
A1
W
BP
DT
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ICM7249
Absolute Maximum Ratings
Supply Voltage (V DD - VSS ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V Input Voltage, Pins 43 - 48 (Note 1) . . (VSS - 0.3V) to (VDD + 0.3V)
Thermal Information
Thermal Resistance (Typical, Note 2)
JA (oC/W)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Due to the SCR structure inherent in junction-isolated CMOS devices. the circuit can be put in a latchup mode it large currents are injected into device inputs or outputs. For this reason special care should be taken in a system with multiple power supplies to prevent voltages being applied to inputs or outputs before power is applied. If only inputs are affected, latchup also can be prevented by limiting the current into the input terminal to less than 1mA. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Operating Voltage, VDD Operating Current, IDD
Temperature = -40oC to 85oC, VDD = 2.5V to 5.5V, VSS = 0V, Unless Otherwise Specified. Typical Specifications Measured at Temperature = 25oC and VDD = 2.8V, Unless Otherwise Specified TEST CONDITIONS Note 1 All Inputs = VDD or GND, Note 2 VDD = 2.8V VDD = 5.5V 1.0 4.0 10.0 20.0 A A MIN 2.5 TYP MAX 5.5 UNITS V
INPUT CURRENT C0 - C3, IIN S/S, ISS DT, IDT INPUT VOLTAGE C0 - C3, DT, S/S VIL VIH Segment Output Voltage VOL VOH Backplane Output Voltage VOL VOH OSCILLATOR STABILITY Temperature = 25oC, VDD = 2.5V to 5.5V Temperature = -40oC to 85oC, VDD = 2.5V to 5.5V S/S PULSE WIDTH High-Pass Filter (Modes 0 - 3), tHP Debounce (Modes 4, 6, 8, 10), tDE Without Debounce (Modes 5, 7, 9, 11), tDE NOTES: 1. Internal reset to 00000 requires a maximum VDD rise time of 1s. Longer rise times at power-up may cause improper reset. 2. Operating current is measured with the LCD disconnected, and input current ISS and IDT supplied externally. 3. Inputs C0 - C3 are latched internally and draw no DC current after switching. During switching, a 90A peak current may be drawn for 10ns. 5 10,000 5 10,000 s s s 0.1 5 ppm ppm IOL = 10A IOH = 10A VDD - 0.8 0.8 V V IOL = 1A IOH = 1A VDD - 0.8 0.8 V V 0.7V DD 0.3V DD V V All Inputs VDD or GND VDD = 2.8V Note 3 0.0 0.5 40.0 1.5 1 3.0 110 A A A
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ICM7249 Timing Waveforms
POWER ON VDD tr ONE 1/2 BACKPLANE CYCLE OSC OUT 1 2 3 4 5 6 511 512 fBP = 32Hz f0 = 32.768kHz RESET
BP
ON SEGMENTS
fSEG = 32Hz
OFF SEGMENTS
FIGURE 1. POWER ON/RESET WAVEFORMS
TIMING ACTIVE DURING INTERVAL
S/S VALID tHP > 12.5ms
TIMING INTERMINATE DURING INTERVAL tHP S/S INVALID 40Hz < f < 50Hz 10ms < tHP < 12.5ms
TIMING ACTIVE DURING INTERVAL tHP S/S VALID 50Hz f 120kHz 5s tHP 10ms
FIGURE 2. START/STOP INPUT HIGH-PASS FILTERING IN TIMING MODES
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ICM7249 Timing Waveforms
(Continued)
TIMING ACTIVE S/S
BP
1 WINK GOES IN PHASE
16
17 WINK GOES OUT PHASE
W
ON SEGMENTS
OFF SEGMENTS
FIGURE 3. WINK WAVEFORMS IN TIMING MODES
COUNT WITH OR WITHOUT DEBOUNCE
S/S VALID tDE > 12.5ms COUNT WITHOUT DEBOUNCE UNKNOWN RESULTS WITH DEBOUNCE tDE S/S INVALID 40Hz < f < 50Hz COUNT WITHOUT DEBOUNCE ONE COUNT WITH DEBOUNCE tDE S/S VALID 50Hz f 120kHz 5s tDE 10ms
10ms < tDE < 12.5ms
FIGURE 4. START/STOP INPUT DEBOUNCE FILTERING IN COUNTING MODES
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ICM7249 Timing Waveforms
(Continued)
S/S
BP 15 16 17 WINK GOES IN PHASE W 32 1 2 WINK GOES OUT PHASE
FIGURE 5. WINK WAVEFORMS IN COUNTING MODES
BP 14 15 16 17 64 1 2
DT
ALL SEGMENTS ON ALL SEGMENTS ON OR OFF
ALL SEGMENTS OFF
DISPLAY RESTORED
FIGURE 6. DISPLAY TESTING
Pin Descriptions
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NAME b6/c6 f5 g5 e5 d5 c5 b5 a5 f4 g4 e4 d4 c4 b4 a4 DESCRIPTION Half-Digit LCD Segment Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. PIN 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NAME f3 g3 e3 d3 c3 b3 a3 f2 g2 e2 d2 c2 b2 a2 f1 DESCRIPTION Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output.
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ICM7249
PIN 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NAME 91 e1 d1 c1 b1 a1 W BP VDD OSC IN OSC OUT GND C0 C1 C2 C3 S/S DT DESCRIPTION Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Seven-Segment LCD Output. Wink-Segment Output. Backplane for LCD Reference. Positive Supply Voltage. Quartz Crystal Connection. Quartz Crystal Connection. Supply GRouND. Mode-select Control Input. Mode-select Control Input. Mode-select Control Input. Mode-select Control Input. Start/Stop Input. Display Test Input.
As the Functional Diagram shows the device consists of the following building blocks: * A 32.768kHz crystal oscillator with the associated dividers to generate timebase signals for periods of 1s (frequency of 1Hz), 6s (1/10 min) and 36s (1/100 hour), and 32Hz signal for LCD drivers. * A debounce/high-pass detect circuit for the S/S (Start/Stop) input. * A chain of cascaded decade counters, 3 decade counters for prescaling and 51/2 BCD decade counters for display driving. * Display control circuitry and BCD to 7-segment decoder/ drivers. * A control decoder to select different modes of operation. This is done by routing different signals to the different points in the chain of decade counters. The control decoder has 4 inputs for selecting 16 possible modes of operation, numbered 0 to 15. The 16 modes are selected by placing the binary equivalent of the mode number on inputs C0 to C3. Table 2 shows the control inputs and the modes of operation. After applying power, the ICM7249 requires a rise time of tr to become active and for oscillation to begin, as shown in Figure 1. The BP (backplane) output changes state once every 512 cycles of the crystal oscillator, resulting in a square wave of 32Hz. The display segments drive signal has the same level and frequency as BP. Segments are off when in phase with BP and are on when out of phase with BP. A non-multiplexed LCD display is used because it is more stable over temperature and allows many standard LCD displays to be used. Timer Mode of Operation In modes 0 to 3 the device functions as an interval timer. In this mode, one of the timebase signals will be routed to the decade counters at a proper point in the chain. Depending on the selected mode the display will be incremented at 0.1 min, 0.01 hour, 0.1 hour or 1 hour rates. Control of timing function is handled by the S/S input. There is a high-pass filtering effect on the S/S input in timer modes. Referring to Figure 2, timing is active when either S/S is held high for more than 12.5ms, or if input frequency is 50Hz to 120kHz. Driving S/S with a frequency between 40Hz to 50Hz has an indeterminate effect on timing and should be avoided. Note that the tHP intervals shown on Figure 1 are also applied to the intervals when the S/S input is low. Counter Mode of Operation In modes 4 to 11 the device functions as an event counter or totalizer. In this mode the S/S input will be routed to the decade counters at a proper point in the chain. Each positive transition of the S/S will be registered as one count. Depending on the selected mode, the display will be incremented by each pulse, every 10 pulses, every 100 pulses or every 1000 pulses. In counter modes 4, 6, 8 and 10 the S/S input is subjected to
TABLE 1. MODE SELECT TABLE CONTROL PIN INPUTS MODE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FUNCTION 1 Hour Interval Timer 0.1 Hour Interval Timer 0.01 Hour Interval Timer 0.1 Minute Interval Timer 1's Counter with Debounce 1's Counter 10's Counter with Debounce 10's Counter 100's Counter with Debounce 100's Counter 1000's Counter with Debounce 1000's counter Test Display Digits Internal Test Internal Test Reset
Detailed Description
29
ICM7249
debounce filtering. Referring to Figure 4, only the pulses with a frequency of less than 40Hz are valid and will be counted. Input pulses with a frequency of 50Hz to 120kHz are not counted individually, but each burst of input pulses will be counted as one pulse if it lasts at least 12.5ms. Driving S/S with a frequency between 40Hz to 50Hz has an indeterminate result and should be avoided. In counter modes 5, 7, 9 and 11 the S/S input is not subjected to any debouncing action and input pulses will be counted up to a frequency of 120kHz. Wink Segment The wink segment is provided as a annunciator to indicate the ICM7249 is working. It can be connected to any kind of annunciator on an LCD, like the flashing colons in a clock type LCD. In the timer modes, the wink segment flashes while timing is taking place. The wink segment waveform is shown on Figure 3 for timer modes. On the positive transition of S/S, the wink output turns off. It remains off for 16 BP cycles and turns back on for another 16 cycles. If timing is still active, this will be repeated, giving a wink flash rate of 1Hz; otherwise, the wink segment remains on while timing is not active. In the counter modes, the wink segment stays on until a pulse occurs on S/S input, then it winks off indicating a pulse is counted. This will happen regardless of whether the display is incremented. Figure 5 shows the wink waveform for counter modes. When a count occurs, the wink segment turns off at the end of the 16th BP cycle and turns back on at the end of the 32nd BP cycle, giving a half-second wink. If the counting occurs more frequently than once a second, the wink output will continue to flash at the constant rate of 1Hz.
a f g e d FIGURE 7. DIGITS SEGMENT ASSIGNMENT c b
A typical use of the ICM7249 is seen in Figure 8, the Motor Hour Meter. In this application the ICM7249 is configured as an hours-in-use meter and shows how many whole hours of line voltage have been applied. The resistor network and high-pass filtering allow AC line activation of the S/S input. This configuration, which is powered by a 3V lithium cell, will operate continuously for 21/2 years. Without the display, which only needs to be connected when a reading is required, the span of operation is extended to 10 years. When the ICM7249 is configured as an attendance counter, as shown in Figure 9, the display shows each increment. By using mode 2, external debouncing of the gate switch is unnecessary, provided the switch bounce is less than 10ms. The 3V lithium battery can be replaced without disturbing operation if a suitable capacitor is connected in parallel with it. The display should be disconnected, if possible, during the procedure to minimize current drain. The capacitor should be large enough to store charge for the amount of time needed to physically replace the battery (t = VC/I). A 100F capacitor initially charged to 3V will supply a current of 1.0A for 50 seconds before its voltage drops to 2.5V, which is the minimum operating voltage for the ICM7249. Before the battery is removed, the capacitor should be placed in parallel, across the VDD and GND terminals. After the battery is replaced, the capacitor can be removed and the display reconnected.
Display Test and Reset The display may be tested at any time without disturbing operation by pulsing DT high, as seen in Figure 6. On the next positive transition of BP, all the segments turn on and remain on until the end of the 16th BP cycle. This takes a half-second or less. All the segments then turn off for an additional 48 BP cycles (the end of the 64th cycle), after which valid data returns to the display. As long as DT is held high, the segments will remain on. Additional display testing is provided by using mode 12. In this mode each displayed decade is incremented on each positive transition of S/S. Modes 13 and 14 are manufacturer testing only. Mode 15 resets all the decades and internal counters to zero, essentially bringing everything back to power-up status.
Applications
30
ICM7249
LCD
36 W BP A1 B6/C6 OSC1
32.768kHz CRYSTAL
10M S/S
ICM7249 OSC0 VDD + VSS C0 C1 C2 C3 DT
120VAC 60Hz
M
AC MOTOR
100K
10M
+3V Li
DISPLAY TEST
FIGURE 8. MOTOR HOUR METER
LCD
+3V TO +24V DC 36 GATE SWITCH 20k S/S OSC1 ICM7249 W BP A1 B6/C6 32.768kHz CRYSTAL
OSC0 VDD VSS C0 C1 C2 C3 DT
+3V Li
DISPLAY TEST
FIGURE 9. ATTENDANCE COUNTER
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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