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MC74LVX245 Octal Bus Transceiver With 5 V-Tolerant Inputs The MC74LVX245 is an advanced high speed CMOS octal bus transceiver. It is intended for two-way asynchronous communication between data buses. The direction of data transmission is determined by the level of the T/R input. The output enable pin (OE) can be used to disable the device, so that the buses are effectively isolated. All inputs are equipped with protection circuits against static discharge. Features http://onsemi.com MARKING DIAGRAMS 20 SOIC-20 DW SUFFIX CASE 751D 1 LVX245 AWLYYWW * * * * * * * * * High Speed: tPD = 4.7 ns (Typ) at VCC = 3.3 V Low Power Dissipation: ICC = 4 mA (Max) at TA = 25C Power Down Protection Provided on Inputs Balanced Propagation Delays Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Pb-Free Packages are Available* 20 1 20 TSSOP-20 DT SUFFIX CASE 948E 1 LVX 245 ALYW 20 1 Application Notes * Do not force a signal on an I/O pin when it is an active output, * * damage may occur All floating (high impedance) input or I/O pins must be fixed by means of pullup or pulldown resistors or bus terminator ICs A parasitic diode is formed between the bus and VCC terminals. Therefore, the LVX245 cannot be used to interface 5.0 V to 3.0 V systems directly VCC 20 OE 19 B0 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 11 20 1 20 SOEIAJ-20 M SUFFIX CASE 967 1 74LVX245 AWLYWW A WL, L Y, YY W, WW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION 1 T/R 2 A0 3 A1 4 A2 5 A3 6 A4 7 A5 8 A6 9 A7 10 GND See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Figure 1. 20-Lead Pinout (Top View) *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. (c) Semiconductor Components Industries, LLC, 2005 1 March, 2005 - Rev. 3 Publication Order Number: MC74LVX245/D MC74LVX245 OE 19 T/R 1 A0 2 18 A1 3 17 A2 4 16 A3 5 15 A4 6 14 A5 7 13 A6 8 12 A7 9 11 B7 B6 B5 B4 B3 B2 B1 B0 OE L L H Table 1. PIN NAMES Pins OE T/R A0-A7 Bo-B7 Function Output Enable Input Transmit/Receive Input Side A 3-State Inputs or 3-State Outputs Side B 3-State Inputs or 3-State Outputs INPUTS T/R L H X OPERATING MODE Non-Inverting B Data to A Bus A Data to B Bus Z H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; X = High or Low Voltage Level and Transitions are Acceptable; For ICC reasons, Do Not Float Inputs Figure 2. Logic Diagram ORDERING INFORMATION Device MC74LVX245DWR2 MC74LVX245DWR2G MC74LVX245DTR2 MC74LVX245M MC74LVX245MEL Package SOIC-20 SOIC-20 (Pb-Free) TSSOP-20* SOEIAJ-20 (Pb-Free) SOEIAJ-20 (Pb-Free) Shipping 1000 / Tape & Reel 1000 / Tape & Reel 2500 / Tape & Reel 50 Units / Rail 2000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free. http://onsemi.com 2 II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I II I I I I I I I III I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I II I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I I I I II I I I I I II I I I I IIIIIIIII IIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII I I I II I I I I I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I III I I II I I I I I II I I I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I II I I I I II I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I I II I I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS Symbol VCC VI/O Tstg ICC IOK Iout Vin PD IIK Storage Temperature Power Dissipation DC Supply Current, VCC and GND Pins DC Output Current, per Pin Output Diode Current Input Diode Current DC Output Voltage DC Input Voltage (T/R, OE) DC Supply Voltage Parameter DC ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS SymbolIIIIIIIIII Test Conditions Parameter Symbol Dt/DV VOH VCC VOL VI/O VIH ICC IOZ VIL Vin TA Iin Quiescent Supply Current Maximum 3-State Leakage Current Input Leakage Current Low-Level Output Voltage (Vin = VIH or VIL) High-Level Output Voltage (Vin = VIH or VIL) Low-Level Input Voltage High-Level Input Voltage Input Rise and Fall Time Operating Temperature, All Package Types DC Output Voltage DC Input Voltage (T/R, OE) DC Supply Voltage IOL = 50 mA IOL = 50 mA IOL = 4 mA Vin = 5.5 V or GND (T/R, OE) Vin = VCC or GND Vin = VIL or VIH Vout = VCC or GND IOH = -50 mA IOH = -50 mA IOH = -4 mA Parameter http://onsemi.com MC74LVX245 3 VCC V 3.6 3.6 3.6 2.0 3.0 3.0 2.0 3.0 3.0 2.0 3.0 3.6 2.0 3.0 3.6 1.9 2.9 2.58 Min 1.5 2.0 2.4 TA = 25C Typ 0.0 0.0 2.0 3.0 0.1 0.1 0.36 Max 0.2 5 0.1 0.5 0.8 0.8 4.0 Min -40 -0.5 to VCC +0.5 2.0 0 0 0 TA = - 40 to 85C -65 to +150 -0.5 to +7.0 -0.5 to +7.0 1.9 2.9 2.48 Min 1.5 2.0 2.4 Value 180 -20 75 25 20 Max VCC +85 100 5.5 3.6 0.1 0.1 0.44 40.0 2.5 1.0 0.5 0.8 0.8 Max ns/V Unit Unit Unit mW mA mA mA mA mA mA mA C C V V V V V V V V V V MC74LVX245 III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I III I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II I I I I II I I I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIII I I I II I I I I II I I I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIII II I I II I II I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I I II I I I I II I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns) TA = 25C Typ 6.1 8.6 4.7 7.2 TA = - 40 to 85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max Symbol tPLH, tPHL Parameter Test Conditions Min Max Unit ns Propagation Delay Input to Output VCC = 2.7 V CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF 10.7 14.2 13.5 17.0 8.0 11.5 VCC = 3.3 0.3 V VCC = 2.7 V RL = 1 kW 6.6 10.1 tPZL, tPZH Output Enable Time to High and Low Level CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 50 pF 9.0 11.5 7.1 9.6 16.9 20.4 20.5 24.0 13.0 16.5 21.0 14.5 1.5 1.5 ns VCC = 3.3 0.3 V RL = 1 kW VCC = 2.7 V RL = 1 kW 11.0 14.5 tPLZ, tPHZ Output Disable Time From High and Low Level 11.5 9.6 18.0 12.8 1.5 1.5 ns VCC = 3.3 0.3 V RL = 1 kW VCC = 2.7 V VCC = 3.3 0.3 V CL = 50 pF tOSHL tOSLH Output-to-Output Skew (Note 1) CL = 50 pF CL = 50 pF ns 1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH); parameter guaranteed by design. CAPACITIVE CHARACTERISTICS TA = 25C Typ 4 8 TA = - 40 to 85C Min Max 10 Symbol Cin Parameter Min Max 10 Unit pF pF pF Input Capacitance (T/R, OE) CI/O Maximum 3-State I/O Capacitance CPD Power Dissipation Capacitance (Note 2) 21 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per bit). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 3.3V, Measured in SOIC Package) TA = 25C Symbol VOLP VOLV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Characteristic Typ 0.5 -0.5 Max 0.8 -0.8 2.0 0.8 Unit V V V V http://onsemi.com 4 MC74LVX245 SWITCHING WAVEFORMS T/R 50% VCC GND VCC GND HIGH IMPEDANCE VOL +0.3V VOH -0.3V HIGH IMPEDANCE Input A or B Output B or A tPLH 50% tPHL 50% VCC VCC GND OE 50% VCC tPZL tPLZ 50% VCC A or B A or B 50% VCC tPZH 50% VCC tPHZ Figure 3. Figure 4. TEST CIRCUITS TEST POINT OUTPUT DEVICE UNDER TEST CL* DEVICE UNDER TEST TEST POINT OUTPUT 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. CL* *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 5. Propagation Delay Test Circuit Figure 6. 3-State Test Circuit http://onsemi.com 5 MC74LVX245 PACKAGE DIMENSIONS SOIC-20 DW SUFFIX CASE 751D-05 ISSUE G D A 11 X 45 _ q H M B M 20 10X 0.25 E NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ 1 10 20X B 0.25 M B TA S B S A SEATING PLANE h 18X e A1 T C TSSOP-20 DT SUFFIX CASE 948E-02 ISSUE B 20X K REF M L 0.15 (0.006) T U S 0.10 (0.004) TU S V S 2X L/2 L PIN 1 IDENT 1 10 B -U- J J1 N 0.15 (0.006) T U S A -V- N F C D 0.100 (0.004) -T- SEATING PLANE G H DETAIL E http://onsemi.com 6 IIII IIII IIII SECTION N-N M DETAIL E 20 11 K K1 0.25 (0.010) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ -W- DIM A B C D F G H J J1 K K1 L M MC74LVX245 PACKAGE DIMENSIONS SOEIAJ-20 M SUFFIX CASE 967-01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.032 20 11 LE Q1 M_ L DETAIL P E HE 1 10 Z D e VIEW P A c b 0.13 (0.005) M A1 0.10 (0.004) http://onsemi.com 7 MC74LVX245 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 8 MC74LVX245/D |
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