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Features
* Single 2.7V - 3.6V Supply * Serial Peripheral Interface (SPI) Compatible
- Supports SPI Modes 0 and 3
* 70 MHz Maximum Clock Frequency * Flexible, Uniform Erase Architecture
- 4-Kbyte Blocks - 32-Kbyte Blocks - 64-Kbyte Blocks - Full Chip Erase Individual Sector Protection with Global Protect/Unprotect Feature - One 32-Kbyte Top Boot Sector - Two 8-Kbyte Sectors - One 16-Kbyte Sector - Fifteen 64-Kbyte Sectors Hardware Controlled Locking of Protected Sectors Flexible Programming Options - Byte/Page Program (1 to 256 Bytes) - Sequential Program Mode Capability Automatic Checking and Reporting of Erase/Program Failures JEDEC Standard Manufacturer and Device ID Read Methodology Low Power Dissipation - 5 mA Active Read Current (Typical) - 10 A Deep Power-down Current (Typical) Endurance: 100,000 Program/Erase Cycles Data Retention: 20 Years Complies with Full Industrial Temperature Range Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options - 8-lead SOIC (150-mil and 200-mil wide)
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* *
8-megabit 2.7-volt Only Serial Firmware DataFlash(R) Memory AT26DF081A
* * *
* * * *
1. Description
The AT26DF081A is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer-based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT26DF081A, with its erase granularity as small as 4 Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices. The physical sectoring and the erase block sizes of the AT26DF081A have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density.
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The AT26DF081A also offers a sophisticated method for protecting individual sectors against erroneous or malicious program and erase operations. By providing the ability to individually protect and unprotect sectors, a system can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array securely protected. This is useful in applications where program code is patched or updated on a subroutine or module basis, or in applications where data storage segments need to be modified without running the risk of errant modifications to the program code segments. In addition to individual sector protection capabilities, the AT26DF081A incorporates Global Protect and Global Unprotect features that allow the entire memory array to be either protected or unprotected all at once. This reduces overhead during the manufacturing process since sectors do not have to be unprotected one-by-one prior to initial programming. Specifically designed for use in 3-volt systems, the AT26DF081A supports read, program, and erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing.
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2. Pin Descriptions and Pinouts
Table 2-1.
Symbol
Pin Descriptions
Name and Function CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in standby mode (not Deep Power-down mode), and the SO pin will be in a high-impedance state. When the device is deselected, data will not be accepted on the SI pin. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK. SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched on the rising edge of SCK. SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK. WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please refer to section "Protection Commands and Features" on page 15 for more details on protection features and the WP pin. The WP pin is internally pulled-high and may be left floating if hardware-controlled protection will not be used. However, it is recommended that the WP pin also be externally connected to VCC whenever possible. HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state. The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold condition to start. A Hold condition pauses serial communication only and does not have an effect on internally self-timed operations such as a program or erase cycle. Please refer to section "Hold" on page 30 for additional details on the Hold operation. The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used. However, it is recommended that the HOLD pin also be externally connected to VCC whenever possible. DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may produce spurious results and should not be attempted. GROUND: The ground reference for the power supply. GND should be connected to the system ground. Asserted State Type
CS
Low
Input
SCK
Input
SI
Input
SO
Output
WP
Low
Input
HOLD
Low
Input
VCC GND
Power Power
Figure 2-1.
CS SO WP GND
8-SOIC Top View
1 2 3 4 8 7 6 5 VCC HOLD SCK SI
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3. Block Diagram
CS
CONTROL AND PROTECTION LOGIC
I/O BUFFERS AND LATCHES
SCK SI SO
SRAM DATA BUFFER INTERFACE CONTROL AND LOGIC ADDRESS LATCH
Y-DECODER
Y-GATING
WP
X-DECODER
FLASH MEMORY ARRAY
4. Memory Array
To provide the greatest flexibility, the memory array of the AT26DF081A can be erased in four levels of granularity including a full chip erase. In addition, the array has been divided into physical sectors of various sizes, of which each sector can be individually protected from program and erase operations. The sizes of the physical sectors are optimized for both code and data storage applications, allowing both code and data segments to reside in their own isolated regions. Figure 4-1 on page 5 illustrates the breakdown of each erase level as well as the breakdown of each physical sector.
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Figure 4-1. Memory Architecture Diagram
Block Erase Detail
Internal Sectoring for Sector Protection Function 64KB 32KB Block Erase Block Erase (D8h Command) (52h Command) 4KB Block Erase (20h Command) 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB *** Block Address Range 0FFFFFh 0FEFFFh 0FDFFFh 0FCFFFh 0FBFFFh 0FAFFFh 0F9FFFh 0F8FFFh 0F7FFFh 0F6FFFh 0F5FFFh 0F4FFFh 0F3FFFh 0F2FFFh 0F1FFFh 0F0FFFh 0EFFFFh 0EEFFFh 0EDFFFh 0ECFFFh 0EBFFFh 0EAFFFh 0E9FFFh 0E8FFFh 0E7FFFh 0E6FFFh 0E5FFFh 0E4FFFh 0E3FFFh 0E2FFFh 0E1FFFh 0E0FFFh - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0FF000h 0FE000h 0FD000h 0FC000h 0FB000h 0FA000h 0F9000h 0F8000h 0F7000h 0F6000h 0F5000h 0F4000h 0F3000h 0F2000h 0F1000h 0F0000h 0EF000h 0EE000h 0ED000h 0EC000h 0EB000h 0EA000h 0E9000h 0E8000h 0E7000h 0E6000h 0E5000h 0E4000h 0E3000h 0E2000h 0E1000h 0E0000h
Page Program Detail
1-256 Byte Page Program (02h Command) 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes *** Page Address Range 0FFFFFh 0FFEFFh 0FFDFFh 0FFCFFh 0FFBFFh 0FFAFFh 0FF9FFh 0FF8FFh 0FF7FFh 0FF6FFh 0FF5FFh 0FF4FFh 0FF3FFh 0FF2FFh 0FF1FFh 0FF0FFh 0FEFFFh 0FEEFFh 0FEDFFh 0FECFFh 0FEBFFh 0FEAFFh 0FE9FFh 0FE8FFh - - - - - - - - - - - - - - - - - - - - - - - - 0FFF00h 0FFE00h 0FFD00h 0FFC00h 0FFB00h 0FFA00h 0FF900h 0FF800h 0FF700h 0FF600h 0FF500h 0FF400h 0FF300h 0FF200h 0FF100h 0FF000h 0FEF00h 0FEE00h 0FED00h 0FEC00h 0FEB00h 0FEA00h 0FE900h 0FE800h
32KB (Sector 18)
32KB
8KB (Sector 17) 8KB (Sector 16) 16KB (Sector 15)
64KB
32KB
32KB
64KB (Sector 14)
64KB
32KB
32KB
64KB (Sector 0)
64KB
32KB
4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB
00FFFFh 00EFFFh 00DFFFh 00CFFFh 00BFFFh 00AFFFh 009FFFh 008FFFh 007FFFh 006FFFh 005FFFh 004FFFh 003FFFh 002FFFh 001FFFh 000FFFh
- - - - - - - - - - - - - - - -
00F000h 00E000h 00D000h 00C000h 00B000h 00A000h 009000h 008000h 007000h 006000h 005000h 004000h 003000h 002000h 001000h 000000h
256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes
0017FFh 0016FFh 0015FFh 0014FFh 0013FFh 0012FFh 0011FFh 0010FFh 000FFFh 000EFFh 000DFFh 000CFFh 000BFFh 000AFFh 0009FFh 0008FFh 0007FFh 0006FFh 0005FFh 0004FFh 0003FFh 0002FFh 0001FFh 0000FFh
- - - - - - - - - - - - - - - - - - - - - - - -
001700h 001600h 001500h 001400h 001300h 001200h 001100h 001000h 000F00h 000E00h 000D00h 000C00h 000B00h 000A00h 000900h 000800h 000700h 000600h 000500h 000400h 000300h 000200h 000100h 000000h
***
***
***
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5. Device Operation
The AT26DF081A is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI Master. The SPI Master communicates with the AT26DF081A via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO). The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT26DF081A supports the two most common modes, SPI modes 0 and 3. The only difference between SPI modes 0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any data). With SPI modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge of SCK. Figure 5-1.
CS
SPI Mode 0 and 3
SCK
SI
MSB
LSB
SO
MSB
LSB
6. Commands and Addressing
A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted, the SPI Master must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction dependent information such as address and data bytes would then be clocked out by the SPI Master. All opcode, address, and data bytes are transferred with the most significant bit (MSB) first. An operation is ended by deasserting the CS pin. Opcodes not supported by the AT26DF081A will be ignored by the device and no operation will be started. The device will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then reasserted). In addition, if the CS pin is deasserted before complete opcode and address information is sent to the device, then no operation will be performed and the device will simply return to the idle state and wait for the next operation. Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23 - A0. Since the upper address limit of the AT26DF081A memory array is 0FFFFFh, address bits A23 - A20 are always ignored by the device.
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Table 6-1.
Command Read Commands Read Array Read Array (Low Frequency) Program and Erase Commands Block Erase (4 Kbytes) Block Erase (32 Kbytes) Block Erase (64 Kbytes) Chip Erase C7h Byte/Page Program (1 to 256 Bytes) Sequential Program Mode AFh Protection Commands Write Enable Write Disable Protect Sector Unprotect Sector Global Protect/Unprotect Read Sector Protection Registers Status Register Commands Read Status Register Write Status Register Miscellaneous Commands Read Manufacturer and Device ID Deep Power-down Resume from Deep Power-down Note: 9Fh B9h ABh 1001 1111 1011 1001 1010 1011 0 0 0 0 0 0 1 to 4 0 0 05h 01h 0000 0101 0000 0001 0 0 0 0 1+ 1 3Ch 06h 04h 36h 39h 0000 0110 0000 0100 0011 0110 0011 1001 0 0 3 3 0 0 0 0 0 0 0 0 1010 1111 02h ADh 1100 0111 0000 0010 1010 1101 0 3 3, 0
(1)
Command Listing
Opcode Address Bytes Dummy Bytes Data Bytes
0Bh 03h
0000 1011 0000 0011
3 3
1 0
1+ 1+
20h 52h D8h 60h
0010 0000 0101 0010 1101 1000 0110 0000
3 3 3 0
0 0 0 0 0 0 0 0
0 0 0 0 0 1+ 1 1
3, 0(1)
Use Write Status Register command 0011 1100 3 0 1+
1. Three address bytes are only required for the first operation to designate the address to start programming at. Afterwards, the internal address counter automatically increments, so subsequent Sequential Program Mode operations only require clocking in of the opcode and the data byte until the Sequential Program Mode has been exited.
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7. Read Commands
7.1 Read Array
The Read Array command can be used to sequentially read a continuous stream of data from the device by simply providing the SCK signal once the initial starting address has been specified. The device incorporates an internal address counter that automatically increments on every clock cycle. Two opcodes, 0Bh and 03h, can be used for the Read Array command. The use of each opcode depends on the maximum SCK frequency that will be used to read data from the device. The 0Bh opcode can be used at any SCK frequency up to the maximum specified by fSCK. The 03h opcode can be used for lower frequency read operations up to the maximum specified by fRDLF. To perform the Read Array operation, the CS pin must first be asserted and the appropriate opcode (0Bh or 03h) must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the memory array. If the 0Bh opcode is used, then one don't care byte must also be clocked in after the three address bytes. After the three address bytes (and the one don't care byte if using opcode 0Bh) have been clocked in, additional clock cycles will result in serial data being output on the SO pin. The data is always output with the MSB of a byte first. When the last byte (0FFFFFh) of the memory array has been read, the device will continue reading back at the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array. Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Figure 7-1. Read Array - 0Bh Opcode
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK
OPCODE ADDRESS BITS A23-A0
0 1 1 A
MSB
DON'T CARE
A A X
MSB
SI
0
MSB
0
0
0
1
A
A
A
A
A
A
X
X
X
X
X
X
X
DATA BYTE 1
SO
HIGH-IMPEDANCE
D
MSB
D
D
D
D
D
D
D
D
MSB
D
Figure 7-2.
Read Array - 03h Opcode
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40
SCK
OPCODE ADDRESS BITS A23-A0
0 1 1 A
MSB
SI
0
MSB
0
0
0
0
A
A
A
A
A
A
A
A
DATA BYTE 1
SO
HIGH-IMPEDANCE
D
MSB
D
D
D
D
D
D
D
D
MSB
D
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8. Program and Erase Commands
8.1 Byte/Page Program
The Byte/Page Program command allows anywhere from a single byte of data to 256 bytes of data to be programmed into previously erased memory locations. An erased memory location is one that has all eight bits set to the logical "1" state (a byte value of FFh). Before a Byte/Page Program command can be started, the Write Enable command must have been previously issued to the device (see "Write Enable" on page 15 command description) to set the Write Enable Latch (WEL) bit of the Status Register to a logical "1" state. To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device followed by the three address bytes denoting the first byte location of the memory array to begin programming at. After the address bytes have been clocked in, data can then be clocked into the device and will be stored in an internal buffer. If the starting memory address denoted by A23 - A0 does not fall on an even 256-byte page boundary (A7 - A0 are not all 0's), then special circumstances regarding which memory locations will be programmed will apply. In this situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the beginning of the same page. For example, if the starting address denoted by A23 - A0 is 0000FEh, and three bytes of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000FEh and 0000FFh while the last byte of data will be programmed at address 000000h. The remaining bytes in the page (addresses 000001h through 0000FDh) will be unaffected and will not change. In addition, if more than 256 bytes of data are sent to the device, then only the last 256 bytes sent will be latched into the internal buffer. When the CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the appropriate memory array locations based on the starting address specified by A23 - A0 and the number of data bytes sent to the device. If less than 256 bytes of data were sent to the device, then the remaining bytes within the page will not be altered. The programming of the data bytes is internally self-timed and should take place in a time of tPP. The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation and no data will be programmed into the memory array. In addition, if the address specified by A23 - A0 points to a memory location within a sector that is in the protected state (see section "Protect Sector" on page 16), then the Byte/Page Program command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical "0" state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, or because the memory location to be programmed is protected. While the device is programming, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tPP time to determine if the data bytes have finished programming. At some point before the program cycle completes, the WEL bit in the Status Register will be reset back to the logical "0" state.
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The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register. The Byte/Page Program mode is the default programming mode after the device powers-up or resumes from a device reset. Figure 8-1. Byte Program
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39
SCK
OPCODE ADDRESS BITS A23-A0
0 1 0 A
MSB
DATA IN
A A D
MSB
SI
0
MSB
0
0
0
0
A
A
A
A
A
A
D
D
D
D
D
D
D
SO
Figure 8-2. Page Program
HIGH-IMPEDANCE
CS
0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 39
SCK
OPCODE ADDRESS BITS A23-A0
0 1 0 A
MSB
DATA IN BYTE 1
D
MSB
DATA IN BYTE n
D D
MSB
SI
0
MSB
0
0
0
0
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
SO
HIGH-IMPEDANCE
8.2
Sequential Program Mode
The Sequential Program Mode improves throughput over the Byte/Page Program command when the Byte/Page Program command is used to program single bytes only into consecutive address locations. For example, some systems may be designed to program only a single byte of information at a time and cannot utilize a buffered Page Program operation due to design restrictions. In such a case, the system would normally have to perform multiple Byte Program operations in order to program data into sequential memory locations. This approach can add considerable system overhead and SPI bus traffic. The Sequential Programming Mode helps reduce system overhead and bus traffic by incorporating an internal address counter that keeps track of the byte location to program, thereby eliminating the need to supply an address sequence to the device for every byte to program. When using the Sequential Program mode, all address locations to be programmed must be in the erased state. Before the Sequential Program mode can first be entered, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical "1" state.
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To start the Sequential Program Mode, the CS pin must first be asserted, and either an opcode of ADh or AFh must be clocked into the device. For the first program cycle, three address bytes must be clocked in after the opcode to designate the first byte location to program. After the address bytes have been clocked in, the byte of data to be programmed can be sent to the device. Deasserting the CS pin will start the internally self-timed program operation, and the byte of data will be programmed into the memory location specified by A23 - A0. After the first byte has been successfully programmed, a second byte can be programmed by simply reasserting the CS pin, clocking in the ADh or AFh opcode, and then clocking in the next byte of data. When the CS pin is deasserted, the second byte of data will be programmed into the next sequential memory location. The process would be repeated for any additional bytes. There is no need to reissue the Write Enable command once the Sequential Program Mode has been entered. When the last desired byte has been programmed into the memory array, the Sequential Program Mode operation can be terminated by reasserting the CS pin and sending the Write Disable command to the device to reset the WEL bit in the Status Register back to the logical "0" state. If more than one byte of data is ever clocked in during each program cycle, then only the last byte of data sent on the SI pin will be stored in the internal latches. The programming of each byte is internally self-timed and should take place in a time of tBP. For each program cycle, a complete byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the byte of data will not be programmed into the memory array, and the WEL bit in the Status Register will be reset back to the logical "0" state. If the address initially specified by A23 - A0 points to a memory location within a sector that is in the protected state, then the Sequential Program Mode command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will also be reset back to the logical "0" state. There is no address wrapping when using the Sequential Program Mode. Therefore, when the last byte (0FFFFFh) of the memory array has been programmed, the device will automatically exit the Sequential Program mode and reset the WEL bit in the Status Register back to the logical "0" state. In addition, the Sequential Program mode will not automatically skip over protected sectors; therefore, once the highest unprotected memory location in a programming sequence has been programmed, the device will automatically exit the Sequential Program mode and reset the WEL bit in the Status Register. For example, if Sector 1 was protected and Sector 0 was currently being programmed, once the last byte of Sector 0 was programmed, the Sequential Program mode would automatically end. To continue programming with Sector 2, the Sequential Program mode would have to be restarted by supplying the ADh or AFh opcode, the three address bytes, and the first byte of Sector 2 to program. While the device is programming a byte, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled at the end of each program cycle rather than waiting the tBP time to determine if the byte has finished programming before starting the next Sequential Program mode cycle. The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.
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Figure 8-3.
Sequential Program Mode - Status Register Polling
CS
Seqeuntial Program Mode Command Status Register Read Seqeuntial Program Mode Command Command A15-8 A7-0 Data 05h Opcode Data 05h Seqeuntial Program Mode Write Disable Command Command Opcode Data 04h 05h
SI
Opcode A23-16
First Address to Program STATUS REGISTER DATA STATUS REGISTER DATA STATUS REGISTER DATA
SO
HIGH-IMPEDANCE
Note: Each transition
shown for SI represents one byte (8 bits)
Figure 8-4.
Sequential Program Mode - Waiting Maximum Byte Program Time
tBP
Seqeuntial Program Mode Command Seqeuntial Program Mode Command A15-8 A7-0 Data Opcode Data
CS
tBP
Seqeuntial Program Mode Command Opcode Data
tBP
Write Disable Command 04h
SI
Opcode A23-16
First Address to Program
SO
HIGH-IMPEDANCE
Note: Each transition
shown for SI represents one byte (8 bits)
8.3
Block Erase
A block of 4, 32, or 64 Kbytes can be erased (all bits set to the logical "1" state) in a single operation by using one of three different opcodes for the Block Erase command. An opcode of 20h is used for a 4-Kbyte erase, an opcode of 52h is used for a 32-Kbyte erase, and an opcode of D8h is used for a 64-Kbyte erase. Before a Block Erase command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical "1" state. To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h or D8h) must be clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address within the 4-, 32-, or 64-Kbyte block to be erased must be clocked in. Any additional data clocked into the device will be ignored. When the CS pin is deasserted, the device will erase the appropriate block. The erasing of the block is internally selftimed and should take place in a time of tBLKE. Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded by the device. Therefore, for a 4-Kbyte erase, address bits A11 - A0 will be ignored by the device and their values can be either a logical "1" or "0". For a 32-Kbyte erase, address bits A14 - A0 will be ignored, and for a 64-Kbyte erase, address bits A15 - A0 will be ignored by the device. Despite the lower order address bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and no erase operation will be performed.
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If the address specified by A23 - A0 points to a memory location within a sector that is in the protected state, then the Block Erase command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. In addition, with the larger Block Erase sizes of 32K and 64 Kbytes, more than one physical sector may be erased (e.g. sectors 18 through 15) at one time. Therefore, in order to erase a larger block that may span more than one sector, all of the sectors in the span must be in the unprotected state. If one of the physical sectors within the span is in the protected state, then the device will ignore the Block Erase command and will return to the idle state once the CS pin is deasserted. The WEL bit in the Status Register will be reset back to the logical "0" state if the erase cycle aborts due to an incomplete address being sent or because a memory location within the region to be erased is protected. While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tBLKE time to determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status Register will be reset back to the logical "0" state. The device also incorporates an intelligent erasing algorithm that can detect when a byte location fails to erase properly. If an erase error occurs, it will be indicated by the EPE bit in the Status Register. Figure 8-5. Block Erase
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31
SCK
OPCODE ADDRESS BITS A23-A0
C C A
MSB
SI
C
MSB
C
C
C
C
C
A
A
A
A
A
A
A
A
A
A
A
SO
HIGH-IMPEDANCE
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8.4
Chip Erase
The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip Erase command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical "1" state. Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in device functionality when utilizing the two opcodes, so they can be used interchangeably. To perform a Chip Erase, one of the two opcodes (60h or C7h) must be clocked into the device. Since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the device will erase the entire memory array. The erasing of the device is internally self-timed and should take place in a time of tCHPE. The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no erase will be performed. In addition, if any sector of the memory array is in the protected state, then the Chip Erase command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical "0" state if a sector is in the protected state. While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tCHPE time to determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status Register will be reset back to the logical "0" state. The device also incorporates an intelligent erasing algorithm that can detect when a byte location fails to erase properly. If an erase error occurs, it will be indicated by the EPE bit in the Status Register. Figure 8-6. Chip Erase
CS
0 1 2 3 4 5 6 7
SCK
OPCODE
SI
C
MSB
C
C
C
C
C
C
C
SO
HIGH-IMPEDANCE
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9. Protection Commands and Features
9.1 Write Enable
The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Register to a logical "1" state. The WEL bit must be set before a program, erase, Protect Sector, Unprotect Sector, or Write Status Register command can be executed. This makes the issuance of these commands a two step process, thereby reducing the chances of a command being accidentally or erroneously executed. If the WEL bit in the Status Register is not set prior to the issuance of one of these commands, then the command will not be executed. To issue the Write Enable command, the CS pin must first be asserted and the opcode of 06h must be clocked into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit in the Status Register will be set to a logical "1". The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change. Figure 9-1. Write Enable
CS
0 1 2 3 4 5 6 7
SCK
OPCODE
SI
0
MSB
0
0
0
0
1
1
0
SO
HIGH-IMPEDANCE
9.2
Write Disable
The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Register to the logical "0" state. With the WEL bit reset, all program, erase, Protect Sector, Unprotect Sector, and Write Status Register commands will not be executed. The Write Disable command is also used to exit the Sequential Program Mode. Other conditions can also cause the WEL bit to be reset; for more details, refer to the WEL bit section of the Status Register description. To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h must be clocked into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit in the Status Register will be reset to a logical "0". The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change.
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Figure 9-2.
Write Disable
CS
0 1 2 3 4 5 6 7
SCK
OPCODE
SI
0
MSB
0
0
0
0
1
0
0
SO
HIGH-IMPEDANCE
9.3
Protect Sector
Every physical sector of the device has a corresponding single-bit Sector Protection Register that is used to control the software protection of a sector. Upon device power-up or after a device reset, each Sector Protection Register will default to the logical "1" state indicating that all sectors are protected and cannot be programmed or erased. Issuing the Protect Sector command to a particular sector address will set the corresponding Sector Protection Register to the logical "1" state. The following table outlines the two states of the Sector Protection Registers. Table 9-1.
Value 0 1
Sector Protection Register Values
Sector Protection Status Sector is unprotected and can be programmed and erased. Sector is protected and cannot be programmed or erased. This is the default state.
Before the Protect Sector command can be issued, the Write Enable command must have been previously issued to set the WEL bit in the Status Register to a logical "1". To issue the Protect Sector command, the CS pin must first be asserted and the opcode of 36h must be clocked into the device followed by three address bytes designating any address within the sector to be locked. Any additional data clocked into the device will be ignored. When the CS pin is deasserted, the Sector Protection Register corresponding to the physical sector addressed by A23 - A0 will be set to the logical "1" state, and the sector itself will then be protected from program and erase operations. In addition, the WEL bit in the Status Register will be reset back to the logical "0" state. The complete three address bytes must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation, the state of the Sector Protection Register will be unchanged, and the WEL bit in the Status Register will be reset to a logical "0". As a safeguard against accidental or erroneous protecting or unprotecting of sectors, the Sector Protection Registers can themselves be locked from updates by using the SPRL (Sector Protection Registers Locked) bit of the Status Register (please refer to the Status Register description for more details). If the Sector Protection Registers are locked, then any attempts to issue the Protect Sector command will be ignored, and the device will reset the WEL bit in the Status Register back to a logical "0" and return to the idle state once the CS pin has been deasserted.
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Figure 9-3. Protect Sector
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31
SCK
OPCODE ADDRESS BITS A23-A0
1 1 0 A
MSB
SI
0
MSB
0
1
1
0
A
A
A
A
A
A
A
A
A
A
A
SO
HIGH-IMPEDANCE
9.4
Unprotect Sector
Issuing the Unprotect Sector command to a particular sector address will reset the corresponding Sector Protection Register to the logical "0" state (see Table 9-1 for Sector Protection Register values). Every physical sector of the device has a corresponding single-bit Sector Protection Register that is used to control the software protection of a sector. Before the Unprotect Sector command can be issued, the Write Enable command must have been previously issued to set the WEL bit in the Status Register to a logical "1". To issue the Unprotect Sector command, the CS pin must first be asserted and the opcode of 39h must be clocked into the device. After the opcode has been clocked in, the three address bytes designating any address within the sector to be unlocked must be clocked in. Any additional data clocked into the device after the address bytes will be ignored. When the CS pin is deasserted, the Sector Protection Register corresponding to the sector addressed by A23 - A0 will be reset to the logical "0" state, and the sector itself will be unprotected. In addition, the WEL bit in the Status Register will be reset back to the logical "0" state. The complete three address bytes must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation, the state of the Sector Protection Register will be unchanged, and the WEL bit in the Status Register will be reset to a logical "0". As a safeguard against accidental or erroneous locking or unlocking of sectors, the Sector Protection Registers can themselves be locked from updates by using the SPRL (Sector Protection Registers Locked) bit of the Status Register (please refer to the Status Register description for more details). If the Sector Protection Registers are locked, then any attempts to issue the Unprotect Sector command will be ignored, and the device will reset the WEL bit in the Status Register back to a logical "0" and return to the idle state once the CS pin has been deasserted. Figure 9-4. Unprotect Sector
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31
SCK
OPCODE ADDRESS BITS A23-A0
0 0 1 A
MSB
SI
0
MSB
0
1
1
1
A
A
A
A
A
A
A
A
A
A
A
SO
HIGH-IMPEDANCE
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9.5
Global Protect/Unprotect
The Global Protect and Global Unprotect features can work in conjunction with the Protect Sector and Unprotect Sector functions. For example, a system can globally protect the entire memory array and then use the Unprotect Sector command to individually unprotect certain sectors and individually reprotect them later by using the Protect Sector command. Likewise, a system can globally unprotect the entire memory array and then individually protect certain sectors as needed. Performing a Global Protect or Global Unprotect is accomplished by writing a certain combination of data to the Status Register using the Write Status Register command (see "Write Status Register" section on page 26 for command execution details). The Write Status Register command is also used to modify the SPRL (Sector Protection Registers Locked) bit to control hardware and software locking. To perform a Global Protect, the appropriate WP pin and SPRL conditions must be met, and the system must write a logical "1" to bits 5, 4, 3, and 2 of the Status Register. Conversely, to perform a Global Unprotect, the same WP and SPRL conditions must be met but the system must write a logical "0" to bits 5, 4, 3, and 2 of the Status Register. Table 9-2 details the conditions necessary for a Global Protect or Global Unprotect to be performed.
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Table 9-2. Valid SPRL and Global Protect/Unprotect Conditions
New Write Status Register Data Bit 76543210 0x0000xx 0x0001xx 0x1110xx 0x1111xx 0 0 1x0000xx 1x0001xx 1x1110xx 1x1111xx Global Unprotect - all Sector Protection Registers reset to 0 No change to current protection. No change to current protection. No change to current protection. Global Protect - all Sector Protection Registers set to 1 1 1 1 1 1 Protection Operation Global Unprotect - all Sector Protection Registers reset to 0 No change to current protection. No change to current protection. No change to current protection. Global Protect - all Sector Protection Registers set to 1
WP State
Current SPRL Value
New SPRL Value 0 0 0 0 0
No change to the current protection level. All sectors currently protected will remain protected and all sectors currently unprotected will remain unprotected. 0 1 xxxxxxxx The Sector Protection Registers are hard-locked and cannot be changed when the WP pin is LOW and the current state of SPRL is 1. Therefore, a Global Protect/Unprotect will not occur. In addition, the SPRL bit cannot be changed (the WP pin must be HIGH in order to change SPRL back to a 0). Global Unprotect - all Sector Protection Registers reset to 0 No change to current protection. No change to current protection. No change to current protection. Global Protect - all Sector Protection Registers set to 1 Global Unprotect - all Sector Protection Registers reset to 0 No change to current protection. No change to current protection. No change to current protection. Global Protect - all Sector Protection Registers set to 1 No change to the current protection level. All sectors currently protected will remain protected, and all sectors currently unprotected will remain unprotected. The Sector Protection Registers are soft-locked and cannot be changed when the current state of SPRL is 1. Therefore, a Global Protect/Unprotect will not occur. However, the SPRL bit can be changed back to a 0 from a 1 since the WP pin is HIGH. To perform a Global Protect/Unprotect, the Write Status Register command must be issued again after the SPRL bit has been changed from a 1 to a 0. 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1
0x0000xx 0x0001xx 0x1110xx 0x1111xx 1 0 1x0000xx 1x0001xx 1x1110xx 1x1111xx 0x0000xx 0x0001xx 0x1110xx 0x1111xx 1 1 1x0000xx 1x0001xx 1x1110xx 1x1111xx
Essentially, if the SPRL bit of the Status Register is in the logical "0" state (Sector Protection Registers are not locked), then writing a 00h to the Status Register will perform a Global Unprotect without changing the state of the SPRL bit. Similarly, writing a 7Fh to the Status Register will perform a Global Protect and keep the SPRL bit in the logical "0" state. The SPRL bit can, of course, be changed to a logical "1" by writing an FFh if software-locking or hardware-locking is desired along with the Global Protect.
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3600F-DFLASH-03/07
If the desire is to only change the SPRL bit without performing a Global Protect or Global Unprotect, then the system can simply write a 0Fh to the Status Register to change the SPRL bit from a logical "1" to a logical "0" provided the WP pin is deasserted. Likewise, the system can write an F0h to change the SPRL bit from a logical "0" to a logical "1" without affecting the current sector protection status (no changes will be made to the Sector Protection Registers). When writing to the Status Register, bits 5, 4, 3, and 2 will not actually be modified but will be decoded by the device for the purposes of the Global Protect and Global Unprotect functions. Only bit 7, the SPRL bit, will actually be modified. Therefore, when reading the Status Register, bits 5, 4, 3, and 2 will not reflect the values written to them but will instead indicate the status of the WP pin and the sector protection status. Please refer to the "Read Status Register" section and Table 10-1 on page 23 for details on the Status Register format and what values can be read for bits 5, 4, 3, and 2.
9.6
Read Sector Protection Registers
The Sector Protection Registers can be read to determine the current software protection status of each sector. Reading the Sector Protection Registers, however, will not determine the status of the WP pin. To read the Sector Protection Register for a particular sector, the CS pin must first be asserted and the opcode of 3Ch must be clocked in. Once the opcode has been clocked in, three address bytes designating any address within the sector must be clocked in. After the last address byte has been clocked in, the device will begin outputting data on the SO pin during every subsequent clock cycle. The data being output will be a repeating byte of either FFh or 00h to denote the value of the appropriate Sector Protection Register. Table 9-3.
Output Data 00h FFh
Read Sector Protection Register - Output Data
Sector Protection Register Value Sector Protection Register value is 0 (sector is unprotected). Sector Protection Register value is 1 (sector is protected).
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. In addition to reading the individual Sector Protection Registers, the Software Protection Status (SWP) bit in the Status Register can be read to determine if all, some, or none of the sectors are software protected (refer to the "Status Register Commands" on page 23 for more details). Figure 9-5. Read Sector Protection Register
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40
SCK
OPCODE ADDRESS BITS A23-A0
1 0 0 A
MSB
SI
0
MSB
0
1
1
1
A
A
A
A
A
A
A
A
DATA BYTE
SO
20
HIGH-IMPEDANCE
D
MSB
D
D
D
D
D
D
D
D
MSB
D
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9.7 Protected States and the Write Protect (WP) Pin
The WP pin is not linked to the memory array itself and has no direct effect on the protection status of the memory array. Instead, the WP pin, in conjunction with the SPRL (Sector Protection Registers Locked) bit in the Status Register, is used to control the hardware locking mechanism of the device. For hardware locking to be active, two conditions must be met - the WP pin must be asserted and the SPRL bit must be in the logical "1" state. When hardware locking is active, the Sector Protection Registers are locked and the SPRL bit itself is also locked. Therefore, sectors that are protected will be locked in the protected state, and sectors that are unprotected will be locked in the unprotected state. These states cannot be changed as long as hardware locking is active, so the Protect Sector, Unprotect Sector, and Write Status Register commands will be ignored. In order to modify the protection status of a sector, the WP pin must first be deasserted, and the SPRL bit in the Status Register must be reset back to the logical "0" state using the Write Status Register command. When resetting the SPRL bit back to a logical "0", it is not possible to perform a Global Protect or Global Unprotect at the same time since the Sector Protection Registers remain soft-locked until after the Write Status Register command has been executed. If the WP pin is permanently connected to GND, then once the SPRL bit is set to a logical "1", the only way to reset the bit back to the logical "0" state is to power-cycle or reset the device. This allows a system to power-up with all sectors software protected but not hardware locked. Therefore, sectors can be unprotected and protected as needed and then hardware locked at a later time by simply setting the SPRL bit in the Status Register. When the WP pin is deasserted, or if the WP pin is permanently connected to VCC, the SPRL bit in the Status Register can still be set to a logical "1" to lock the Sector Protection Registers. This provides a software locking ability to prevent erroneous Protect Sector or Unprotect Sector commands from being processed. When changing the SPRL bit to a logical "1" from a logical "0", it is also possible to perform a Global Protect or Global Unprotect at the same time by writing the appropriate values into bits 5, 4, 3, and 2 of the Status Register. Tables 9-4 and 9-5 detail the various protection and locking states of the device. Table 9-4.
WP X (Don't Care) Note: 1. "n" represents a sector number
Sector Protection Register States
Sector Protection Register n(1) 0 1 Sector n(1) Unprotected Protected
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Table 9-5.
WP
Hardware and Software Locking
Locking SPRL Change Allowed Sector Protection Registers Unlocked and modifiable using the Protect and Unprotect Sector commands. Global Protect and Unprotect can also be performed. Locked in current state. Protect and Unprotect Sector commands will be ignored. Global Protect and Unprotect cannot be performed. Unlocked and modifiable using the Protect and Unprotect Sector commands. Global Protect and Unprotect can also be performed. Locked in current state. Protect and Unprotect Sector commands will be ignored. Global Protect and Unprotect cannot be performed.
SPRL
0
0
Can be modified from 0 to 1
0
1
Hardware Locked
Locked
1
0
Can be modified from 0 to 1
1
1
Software Locked
Can be modified from 1 to 0
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10. Status Register Commands
10.1 Read Status Register
The Status Register can be read to determine the device's ready/busy status, as well as the status of many other functions such as Hardware Locking and Software Protection. The Status Register can be read at any time, including during an internally self-timed program or erase operation. To read the Status Register, the CS pin must first be asserted and the opcode of 05h must be clocked into the device. After the last bit of the opcode has been clocked in, the device will begin outputting Status Register data on the SO pin during every subsequent clock cycle. After the last bit (bit 0) of the Status Register has been clocked out, the sequence will repeat itself starting again with bit 7 as long as the CS pin remains asserted and the SCK pin is being pulsed. The data in the Status Register is constantly being updated, so each repeating sequence will output new data. Deasserting the CS pin will terminate the Read Status Register operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Table 10-1.
Bit(1) 7 SPRL
Status Register Format
Name Sector Protection Registers Locked Type(2) R/W 1 0 Sector Protection Registers are locked. Byte/Page Programming Mode (default). Sequential Programming Mode entered. Erase or program operation was successful. Erase or program error detected. WP is asserted. WP is deasserted. All sectors are software unprotected (all Sector Protection Registers are 0). Some sectors are software protected. Read individual Sector Protection Registers to determine which sectors are protected. Reserved for future use. All sectors are software protected (all Sector Protection Registers are 1 - default). Device is not write enabled (default). Device is write enabled. Device is ready. Device is busy with an internal operation. Description 0 Sector Protection Registers are unlocked (default).
6
SPM
Sequential Program Mode Status
R 1 0
5
EPE
Erase/Program Error
R 1 0
4
WPP
Write Protect (WP) Pin Status
R 1 00
01 3:2 SWP Software Protection Status R 10 11 0 1 WEL Write Enable Latch Status R 1 0 0 Notes: RDY/BSY Ready/Busy Status R 1 2. R/W = Readable and writable R = Readable only
1. Only bit 7 of the Status Register will be modified when using the Write Status Register command.
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10.1.1
SPRL Bit The SPRL bit is used to control whether the Sector Protection Registers can be modified or not. When the SPRL bit is in the logical "1" state, all Sector Protection Registers are locked and cannot be modified with the Protect Sector and Unprotect Sector commands (the device will ignore these commands). In addition, the Global Protect and Global Unprotect features cannot be performed. Any sectors that are presently protected will remain protected, and any sectors that are presently unprotected will remain unprotected. When the SPRL bit is in the logical "0" state, all Sector Protection Registers are unlocked and can be modified (the Protect Sector and Unprotect Sector commands, as well as the Global Protect and Global Unprotect features, will be processed as normal). The SPRL bit defaults to the logical "0" state after a power-up or a device reset. The SPRL bit can be modified freely whenever the WP pin is deasserted. However, if the WP pin is asserted, then the SPRL bit may only be changed from a logical "0" (Sector Protection Registers are unlocked) to a logical "1" (Sector Protection Registers are locked). In order to reset the SPRL bit back to a logical "0" using the Write Status Register command, the WP pin will have to first be deasserted. The SPRL bit is the only bit of the Status Register than can be user modified via the Write Status Register command.
10.1.2
SPM Bit The SPM bit indicates whether the device is in the Byte/Page Program mode or the Sequential Program Mode. The default state after power-up or device reset is the Byte/Page Program mode.
10.1.3
EPE Bit The EPE bit indicates whether the last erase or program operation completed successfully or not. If at least one byte during the erase or program operation did not erase or program properly, then the EPE bit will be set to the logical "1" state. The EPE bit will not be set if an erase or program operation aborts for any reason such as an attempt to erase or program a protected region or if the WEL bit is not set prior to an erase or program operation. The EPE bit will be updated after every erase and program operation.
10.1.4
WPP Bit The WPP bit can be read to determine if the WP pin has been asserted or not.
10.1.5
SWP Bits The SWP bits provide feedback on the software protection status for the device. There are three possible combinations of the SWP bits that indicate whether none, some, or all of the sectors have been protected using the Protect Sector command or the Global Protect feature. If the SWP bits indicate that some of the sectors have been protected, then the individual Sector Protection Registers can be read with the Read Sector Protection Registers command to determine which sectors are in fact protected.
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10.1.6 WEL Bit The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is in the logical "0" state, the device will not accept any program, erase, Protect Sector, Unprotect Sector, or Write Status Register commands. The WEL bit defaults to the logical "0" state after a device power-up or reset. In addition, the WEL bit will be reset to the logical "0" state automatically under the following conditions: * Write Disable operation completes successfully * Write Status Register operation completes successfully or aborts * Protect Sector operation completes successfully or aborts * Unprotect Sector operation completes successfully or aborts * Byte/Page Program operation completes successfully or aborts * Sequential Program Mode reaches highest unprotected memory location * Sequential Program Mode reaches the end of the memory array * Sequential Program Mode aborts * Block Erase operation completes successfully or aborts * Chip Erase operation completes successfully or aborts * Hold condition aborts If the WEL bit is in the logical "1" state, it will not be reset to a logical "0" if an operation aborts due to an incomplete or unrecognized opcode being clocked into the device before the CS pin is deasserted. In order for the WEL bit to be reset when an operation aborts prematurely, the entire opcode for a program, erase, Protect Sector, Unprotect Sector, or Write Status Register command must have been clocked into the device. 10.1.7 RDY/BSY Bit The RDY/BSY bit is used to determine whether or not an internal operation, such as a program or erase, is in progress. To poll the RDY/BSY bit to detect the completion of a program or erase cycle, new Status Register data must be continually clocked out of the device until the state of the RDY/BSY bit changes from a logical "1" to a logical "0". Figure 10-1. Read Status Register
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCK
OPCODE
SI
0
MSB
0
0
0
0
1
0
1
STATUS REGISTER DATA
STATUS REGISTER DATA
D
MSB
SO
HIGH-IMPEDANCE
D
MSB
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
MSB
D
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10.2
Write Status Register
The Write Status Register command is used to modify the SPRL bit of the Status Register and/or to perform a Global Protect or Global Unprotect operation. Before the Write Status Register command can be issued, the Write Enable command must have been previously issued to set the WEL bit in the Status Register to a logical "1". To issue the Write Status Register command, the CS pin must first be asserted and the opcode of 01h must be clocked into the device followed by one byte of data. The one byte of data consists of the SPRL bit value, a don't care bit, four data bits to denote whether a Global Protect or Unprotect should be performed, and two additional don't care bits (see Table 10-2). Any additional data bytes that are sent to the device will be ignored. When the CS pin is deasserted, the SPRL bit in the Status Register will be modified, and the WEL bit in the Status Register will be reset back to a logical "0". The values of bits 5, 4, 3, and 2 and the state of the SPRL bit before the Write Status Register command was executed (the prior state of the SPRL bit) will determine whether or not a Global Protect or Global Unprotect will be performed. Please refer to the "Global Protect/Unprotect" section on page 18 for more details. The complete one byte of data must be clocked into the device before the CS pin is deasserted; otherwise, the device will abort the operation, the state of the SPRL bit will not change, no potential Global Protect or Unprotect will be performed, and the WEL bit in the Status Register will be reset back to the logical "0" state. If the WP pin is asserted, then the SPRL bit can only be set to a logical "1". If an attempt is made to reset the SPRL bit to a logical "0" while the WP pin is asserted, then the Write Status Register command will be ignored, and the WEL bit in the Status Register will be reset back to the logical "0" state. In order to reset the SPRL bit to a logical "0", the WP pin must be deasserted. Table 10-2.
Bit 7 SPRL
Write Status Register Format
Bit 6 X Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 X Bit 0 X
Global Protect/Unprotect
Figure 10-2. Write Status Register
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
OPCODE STATUS REGISTER IN
0 0 1 D
MSB
SI
0
MSB
0
0
0
0
X
D
D
D
D
X
X
SO
HIGH-IMPEDANCE
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11. Other Commands and Functions
11.1 Read Manufacturer and Device ID
Identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. The identification method and the command opcode comply with the JEDEC standard for "Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices". The type of information that can be read from the device includes the JEDEC defined Manufacturer ID, the vendor specific Device ID, and the vendor specific Extended Device Information. To read the identification information, the CS pin must first be asserted and the opcode of 9Fh must be clocked into the device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO pin during the subsequent clock cycles. The first byte that will be output will be the Manufacturer ID followed by two bytes of Device ID information. The fourth byte output will be the Extended Device Information String Length, which will be 00h indicating that no Extended Device Information follows. After the Extended Device Information String Length byte is output, the SO pin will go into a high-impedance state; therefore, additional clock cycles will have no affect on the SO pin and no data will be output. As indicated in the JEDEC standard, reading the Extended Device Information String Length and any subsequent data is optional. Deasserting the CS pin will terminate the Manufacturer and Device ID read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Table 11-1. Manufacturer and Device ID Information
Byte No. 1 2 3 4 Data Type Manufacturer ID Device ID (Part 1) Device ID (Part 2) Extended Device Information String Length Value 1Fh 45h 01h 00h
Table 11-2.
Data Type Manufacturer ID
Manufacturer and Device ID Details
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Hex Value 1Fh 0 0 Family Code 0 1 1 1 Density Code 45h 0 1 MLC Code 0 0 0 1 0 1 01h 0 0 0 0 0 0 0 1 Product Version Code 1 1 Family Code: Density Code: 010 (AT26DFxxx series) 00101 (8-Mbit) Details JEDEC Code: 0001 1111 (1Fh for Atmel)
JEDEC Assigned Code
Device ID (Part 1)
Device ID (Part 2)
MLC Code: 000 (1-bit/cell technology) Product Version: 00001 (First major revision)
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Figure 11-1. Read Manufacturer and Device ID
CS
0 6 7 8 14 15 16 22 23 24 30 31 32 38
SCK
OPCODE
SI
9Fh
SO
HIGH-IMPEDANCE
1Fh
45h
01h
00h
MANUFACTURER ID
DEVICE ID BYTE 1
DEVICE ID BYTE 2
EXTENDED DEVICE INFORMATION STRING LENGTH
Note: Each transition
shown for SI and SO represents one byte (8 bits)
11.2
Deep Power-down
During normal operation, the device will be placed in the standby mode to consume less power as long as the CS pin remains deasserted and no internal operation is in progress. The Deep Power-down command offers the ability to place the device into an even lower power consumption state called the Deep Power-down mode. When the device is in the Deep Power-down mode, all commands including the Read Status Register command will be ignored with the exception of the Resume from Deep Power-down command. Since all commands will be ignored, the mode can be used as an extra protection mechanism against program and erase operations. Entering the Deep Power-down mode is accomplished by simply asserting the CS pin, clocking in the opcode of B9h, and then deasserting the CS pin. Any additional data clocked into the device after the opcode will be ignored. When the CS pin is deasserted, the device will enter the Deep Power-down mode within the maximum time of tEDPD. The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the standby mode once the CS pin is deasserted. In addition, the device will default to the standby mode after a power-cycle or a device reset.
The Deep Power-down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. The Deep Power-down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the Deep Power-down mode.
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Figure 11-2. Deep Power-down
CS
tEDPD
0 1 2 3 4 5 6 7
SCK
OPCODE
SI
1
MSB
0
1
1
1
0
0
1
SO
HIGH-IMPEDANCE
Active Current
ICC
Standby Mode Current Deep Power-Down Mode Current
11.3
Resume from Deep Power-down
In order exit the Deep Power-down mode and resume normal device operation, the Resume from Deep Power-down command must be issued. The Resume from Deep Power-down command is the only command that the device will recognize while in the Deep Power-down mode. To resume from the Deep Power-down mode, the CS pin must first be asserted and opcode of ABh must be clocked into the device. Any additional data clocked into the device after the opcode will be ignored. When the CS pin is deasserted, the device will exit the Deep Powerdown mode within the maximum time of tRDPD and return to the standby mode. After the device has returned to the standby mode, normal command operations such as Read Array can be resumed. If the complete opcode is not clocked in before the CS pin is deasserted, or if the CS pin is not deasserted on an even byte boundary (multiples of eight bits), then the device will abort the operation and return to the Deep Power-down mode. Figure 11-3. Resume from Deep Power-down
CS
tRDPD
0 1 2 3 4 5 6 7
SCK
OPCODE
SI
1
MSB
0
1
0
1
0
1
1
SO
HIGH-IMPEDANCE
Active Current
ICC
Deep Power-Down Mode Current Standby Mode Current
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11.4
Hold
The HOLD pin is used to pause the serial communication with the device without having to stop or reset the clock sequence. The Hold mode, however, does not have an affect on any internally self-timed operations such as a program or erase cycle. Therefore, if an erase cycle is in progress, asserting the HOLD pin will not pause the operation, and the erase cycle will continue until it is finished. The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated simply by asserting the HOLD pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse, then the Hold mode won't be started until the beginning of the next SCK low pulse. The device will remain in the Hold mode as long as the HOLD pin and CS pin are asserted. While in the Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the SCK pin will be ignored. The WP pin, however, can still be asserted or deasserted while in the Hold mode. To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the SCK low pulse. If the HOLD pin is deasserted during the SCK high pulse, then the Hold mode won't end until the beginning of the next SCK low pulse. If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be aborted, and the device will reset the WEL bit in the Status Register back to the logical "0" state.
Figure 11-4. Hold Mode
CS
SCK
HOLD
Hold
Hold
Hold
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12. Electrical Specifications
12.1 Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Temperature under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground .....................................-0.6V to +4.1V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.5V
12.2
DC and AC Operating Range
AT26DF081A Ind. -40C to 85C 2.7V to 3.6V
Operating Temperature (Case) VCC Power Supply
12.3
DC Characteristics
Parameter Standby Current Deep Power-down Current Condition CS, WP, HOLD = VCC, all inputs at CMOS levels CS, WP, HOLD = VCC, all inputs at CMOS levels f = 70 MHz; IOUT = 0 mA; CS = VIL, VCC = Max f = 66 MHz; IOUT = 0 mA; CS = VIL, VCC = Max Min Typ 25 10 Max 35 15 Units A A
Symbol ISB IDPD
11 10 9
16 15 14 mA
ICC1
Active Current, Read Operation
f = 50 MHz; IOUT = 0 mA; CS = VIL, VCC = Max f = 33 MHz; IOUT = 0 mA; CS = VIL, VCC = Max f = 20 MHz; IOUT = 0 mA; CS = VIL, VCC = Max
8 7 12 14
12 10 18 20 1 1 0.3 x VCC mA mA A A V V 0.4 V V
ICC2 ICC3 ILI ILO VIL VIH VOL VOH
Active Current, Program Operation Active Current, Erase Operation Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
CS = VCC, VCC = Max CS = VCC, VCC = Max VIN = CMOS levels VOUT = CMOS levels
0.7 x VCC IOL = 1.6 mA; VCC = Min IOH = -100 A VCC - 0.2V
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12.4
fSCK fRDLF tSCKH tSCKL tSCKR
(1)
AC Characteristics
Parameter Serial Clock (SCK) Frequency SCK Frequency for Read Array (Low Frequency - 03h opcode) SCK High Time SCK Low Time SCK Rise Time, Peak-to-Peak (Slew Rate) SCK Fall Time, Peak-to-Peak (Slew Rate) Chip Select High Time Chip Select Low Setup Time (relative to SCK) Chip Select Low Hold Time (relative to SCK) Chip Select High Setup Time (relative to SCK) Chip Select High Hold Time (relative to SCK) Data In Setup Time Data In Hold Time Output Disable Time Output Valid Time Output Hold Time HOLD Low Setup Time (relative to SCK) HOLD Low Hold Time (relative to SCK) HOLD High Setup Time (relative to SCK) HOLD High Hold Time (relative to SCK) HOLD Low to Output High-Z HOLD High to Output Low-Z Write Protect Setup Time Write Protect Hold Time Sector Protect Time (from Chip Select High) Sector Unprotect Time (from Chip Select High) Chip Select High to Deep Power-down Chip Select High to Standby Mode 1. Not 100% tested (value guaranteed by design and characterization). 2. 15 pF load at 70 MHz, 30 pF load at 66 MHz. 3. Only applicable as a constraint for the Write Status Register command when SPRL = 1 20 100 20 20 3 3 0 5 5 5 5 6 6 6.4 6.4 0.1 0.1 50 5 5 5 5 2 3 6 6 Min Max 70 33 Units MHz MHz ns ns V/ns V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s
Symbol
tSCKF(1) tCSH tCSLS tCSLH tCSHS tCSHH tDS tDH tDIS(1) tV(2) tOH tHLS tHLH tHHS tHHH tHLQZ(1) tHHQX(1) tWPS(1)(3) tWPH
(1)(3)
tSECP(1) tSECUP(1) tEDPD Notes:
(1)
tRDPD(1)
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12.5
tPP(1) tBP tBLKE(1) tCHPE(2) tWRSR Notes:
(2)
Program and Erase Characteristics
Parameter Page Program Time (256 Bytes) Byte Program Time 4 Kbytes Block Erase Time 32 Kbytes 64 Kbytes Chip Erase Time Write Status Register Time 1. Maximum values indicate worst-case performance after 100,000 erase/program cycles. 2. Not 100% tested (value guaranteed by design and characterization). Min Typ 1.2 7 50 250 400 6 200 600 950 14 200 sec ns ms Max 5 Units ms s
Symbol
12.6
Power-up Conditions
Min 50 10 1.5 2.5 Max Units s ms V
Parameter Minimum VCC to Chip Select Low Time Power-up Device Delay Before Program or Erase Allowed Power-on Reset Voltage
12.7
Input Test Waveforms and Measurement Levels
AC DRIVING LEVELS
tR, tF < 2 ns (10% to 90%)
2.4V 1.5V 0.45V
AC MEASUREMENT LEVEL
12.8
Output Test Load
DEVICE UNDER TEST 30 pF
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13. Waveforms
Figure 13-1. Serial Input Timing
tCSH
CS
tCSLS tSCKH tCSLH tSCKL tCSHH tCSHS
SCK
tDS tDH
MSB LSB MSB
SI
SO
HIGH-IMPEDANCE
Figure 13-2. Serial Output Timing
CS
tSCKH tSCKL tDIS
SCK
SI
tV tOH tV
SO
Figure 13-3. HOLD Timing - Serial Input
CS
SCK
tHHH tHLS tHLH tHHS
HOLD
SI
SO
HIGH-IMPEDANCE
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Figure 13-4. HOLD Timing - Serial Output
CS
SCK
tHHH tHLS tHLH tHHS
HOLD
SI
tHLQZ tHHQX
SO
Figure 13-5. WP Timing for Write Status Register Command When SPRL = 1
CS
tWPS tWPH
WP
SCK
SI
0
MSB OF WRITE STATUS REGISTER OPCODE
0
0
X
LSB OF WRITE STATUS REGISTER DATA BYTE
MSB
MSB OF NEXT OPCODE
SO
HIGH-IMPEDANCE
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14. Ordering Information
14.1 Green Package Options (Pb/Halide-free/RoHS Compliant)
Ordering Code AT26DF081A-SSU 70 AT26DF081A-SU 8S2 Package 8S1 Operation Range Industrial (-40C to 85C)
fSCK (MHz)
Package Type 8S1 8S2 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8-lead, 0.209" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
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15. Packaging Information
15.1 8S1 - JEDEC SOIC
C
1
E
E1
N
L
O
TOP VIEW END VIEW
e b A A1
SYMBOL A1 COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM - MAX NOTE
0.10
0.25
D
SIDE VIEW
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
3/17/05 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. C
R
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15.2
8S2 - EIAJ SOIC
C
1
E
E1
L
N
TOP VIEW
END VIEW
e A
SYMBOL
b
COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE
A1
A A1 b C
1.70 0.05 0.35 0.15 5.13 5.18 7.70 0.51 0 1.27 BSC
2.16 0.25 0.48 0.35 5.35 5.40 8.26 0.85 8 4 2, 3 5 5
D
D E1 E
SIDE VIEW
Notes: 1. 2. 3. 4. 5.
L e
This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs are not included. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. Determines the true geometric position. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
4/7/06 TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) DRAWING NO. 8S2 REV. D
R
2325 Orchard Parkway San Jose, CA 95131
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16. Revision History
Revision Level - Release Date A - November 2005 History Initial Release Added Global Protect and Global Unprotect Feature - Made various minor text changes throughout document - Added Global Protect/Unprotect section to document - Changed Write Status Register section Removed EPE bit from Status Register Changed Note 5 of 8S2 package drawing to generalize terminal plating comment Removed "Preliminary" designation. Changed page and byte program specifications in Section 12.5 - Increased typical page program time from 1.5 ms to 3.0 ms - Increased maximum page program time from 3.0 ms to 5.0 ms - Increased typical byte program time from 6 s to 12 s Added footnote (1) to tCHPE parameter in Section 12.5 Added EPE bit description to the Read Status Register section. Reduced typical read currents in Section 12.3. Improved program and erase times in Section 12.5. - Reduced typical page program time from 3.0 ms to 1.2 ms - Reduced typical byte program time from 12 s to 7 s - Reduced 32KB typical block erase time from 350 ms to 250 ms - Reduced 64KB typical block erase time from 700 ms to 400 ms - Reduced typical Chip Erase time from 10 sec to 6 sec Corrected 8S1 package drawing heading from EIAJ SOIC to JEDEC SOIC.
B - March 2006
C - April 2006
D - May 2006
E - January 2007
F - March 2007
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