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FAST CMOS 18-BIT REGISTER
Integrated Device Technology, Inc.
IDT54/74FCT16823AT/BT/CT/ET IDT54/74FCT162823AT/BT/CT/ET
FEATURES:
* Common features: - 0.5 MICRON CMOS Technology - High-speed, low-power CMOS replacement for ABT functions - Typical tSK(o) (Output Skew) < 250ps - Low input and output leakage 1A (max.) - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) - Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack - Extended commercial range of -40C to +85C - VCC = 5V 10% * Features for FCT16823AT/BT/CT/ET: - High drive outputs (-32mA IOH, 64mA IOL) - Power off disable outputs permit "live insertion" - Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25C * Features for FCT162823AT/BT/CT/ET: - Balanced Output Drivers: 24mA (commercial), 16mA (military) - Reduced system switching noise - Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V,TA = 25C
DESCRIPTION:
The FCT16823AT/BT/CT/ET and FCT162823AT/BT/CT/ ET 18-bit bus interface registers are built using advanced, dual metal CMOS technology. These high-speed, low-power registers with clock enable (xCLKEN) and clear (xCLR) controls are ideal for parity bus interfacing in high-performance synchronous systems. The control inputs are organized to operate the device as two 9-bit registers or one 18-bit register. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT16823AT/BT/CT/ET are ideally suited for driving high-capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers. The FCT162823AT/BT/CT/ET have balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times - reducing the need for external series terminating resistors. The FCT162823AT/BT/CT/ET are plug-in replacements for the FCT16823AT/BT/CT/ET and ABT16823 for on-board interface applications.
FUNCTIONAL BLOCK DIAGRAM
1OE 1CLR 1CLK 1CLKEN
2OE 2CLR 2CLK 2CLKEN
R C D 1D1
1Q1 2D1
R C D
2Q1
TO 8 OTHER CHANNELS
2772 drw 01
TO 8 OTHER CHANNELS
2772 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc.
AUGUST 1996
DSC-2772/8
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IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET FAST CMOS 18-BIT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1CLR 1OE 1Q1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 SO56-1 43 SO56-2 SO56-3 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1CLK 1CLKEN 1D1
1CLR 1OE 1Q1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CERPACK TOP VIEW E56-1
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1CLK 1CLKEN 1D1
GND
1Q2 1Q3
GND
1D2 1D3
GND
1Q2 1Q3
GND
1D2 1D3
VCC
1Q4 1Q5 1Q6
VCC
1D4 1D5 1D6
VCC
1Q4 1Q5 1Q6
VCC
1D4 1D5 1D6
GND
1Q7 1Q8 1Q9 2Q1 2Q2 2Q3
GND
1D7 1D8 1D9 2D1 2D2 2D3
GND
1Q7 1Q8 1Q9 2Q1 2Q2 2Q3
GND
1D7 1D8 1D9 2D1 2D2 2D3
GND
2Q4 2Q5 2Q6
GND
2D4 2D5 2D6
GND
2Q4 2Q5 2Q6
GND
2D4 2D5 2D6
VCC
2Q7 2Q8
VCC
2D7 2D8
VCC
2Q7 2Q8
VCC
2D7 2D8
GND
2Q9 2OE 2CLR
GND
2D9 2CLKEN 2CLK
GND
2Q9 2OE 2CLR
GND
2D9 2CLKEN 2CLK
SSOP/ TSSOP/TVSOP TOP VIEW
2772 drw 03
2772 drw 04
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IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET FAST CMOS 18-BIT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names xDx xCLK xCLKEN xCLR xOE xQx Description Data inputs Clock Inputs Clock Enable Inputs (Active LOW) Asynchronous clear Inputs (Active LOW) Output Enable Inputs (Active LOW) 3-State Outputs
2772 tbl 01
FUNCTION TABLE(1)
xOE OE H L L H H L L xCLR CLR X L H H H H H Inputs xCLKEN CLKEN X X H L L L L xCLK X X X xDx X X X L H L H Outputs xQx Function Z L Q(2) Z Z L H High Z Clear Hold Load
ABSOLUTE MAXIMUM RATINGS
(1)
Unit V V C mA
Symbol Description Max. VTERM(2) Terminal Voltage with Respect to -0.5 to +7.0 GND VTERM(3) Terminal Voltage with Respect to -0.5 to GND VCC +0.5 TSTG Storage Temperature -65 to +150 IOUT DC Output Current -60 to +120
NOTES: 2772 tbl 02 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance 2. Output level before indicated steady-state input conditions were established.
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. Unit 6.0 pF 8.0
pF
2772 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXXT Output and I/O terminals. 3. Output and I/O terminals for FCT162XXXT.
2772 lnk 04 NOTE: 1. This parameter is measured at characterization but not tested.
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IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET FAST CMOS 18-BIT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = -40C to +85C, VCC = 5.0V 10%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL II H II L IOZH IOZL VIK IOS VH ICCL ICCH ICCZ Parameter Input HIGH Level Input LOW Level Input HIGH Current (Input pins)(5) Input HIGH Current (I/O pins)(5) Input LOW Current (Input pins)(5) VCC = Max. VCC = Min., IIN = -18mA VCC = Max., VO = GND (3)
--
Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC VI = GND VO = 2.7V VO = 0.5V
Min. 2.0 -- -- -- -- -- -- -- -- -80 -- --
Typ.(2) --
-- -- -- -- -- -- -- -0.7 -140
Max.
--
Unit V V A
0.8 1 1 1 1 1 1
-1.2 -225 --
Input LOW Current (I/O pins)(5) High Impedance Output Current (3-State Output pins) (5) Clamp Diode Voltage Short Circuit Current Input Hysteresis Quiescent Power Supply Current
A V mA mV A
100 5
VCC = Max., VIN = GND or VCC
500
2772 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16823T
Symbol IO VOH Parameter Output Drive Current Output HIGH Voltage Test Conditions(1) VCC = Max., VO = 2.5V(3) VCC = Min. VIN = VIH or VIL IOH = -3mA IOH = -12mA MIL. IOH = -15mA COM'L. IOH = -24mA MIL. IOH = -32mA COM'L.(4) VCC = Min. IOL = 48mA MIL. VIN = VIH or VIL IOL = 64mA COM'L. VCC = 0V, VIN or VO 4.5V Min. -50 2.5 2.4 2.0 -- -- Typ.(2)
--
Max.
-180
Unit mA V V V V
3.5 3.5 3.0 0.2 --
-- -- -- 0.55
VOL IOFF
Output LOW Voltage Input/Output Power Off Leakage(5)
1
A
2772 lnk 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162823T
Symbol IODL IODH VOH VOL Parameter Output LOW Current Output HIGH Current Output HIGH Voltage Output LOW Voltage Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3) VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or VIL IOH = -16mA MIL. IOH = -24mA COM'L. IOL = 16mA MIL. IOL = 24mA COM'L. Min. 60 -60 2.4 -- Typ.(2) 115 -115 3.3 0.3 Max. 200 -200 -- 0.55 Unit mA mA V V
2772 lnk 07
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5. The test limit for this parameter is 5A at TA = -55C.
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IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET FAST CMOS 18-BIT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current (4) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open xOE = xCLKEN = GND One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fCP= 10MHz 50% Duty Cycle xOE = xCLKEN = GND at fi = 5MHz 50% Duty Cycle One Bit Toggling VCC = Max. Outputs Open fCP= 10MHz 50% Duty Cycle xOE = xCLKEN = GND at fi = 2.5MHz 50% Duty Cycle Eighteen Bits Toggling VIN = VCC VIN = GND Min. -- -- Typ.(2) 0.5 75 Max. 1.5 120 Unit mA A/ MHz
IC
Total Power Supply Current (6)
VIN = VCC VIN = GND
--
0.8
1.7
mA
VIN = 3.4V VIN = GND
--
1.3
3.2
VIN = VCC VIN = GND
--
4.2
7.1 (5)
VIN = 3.4V VIN = GND
--
9.2
22.1 (5)
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi
2772 tbl 08
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IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET FAST CMOS 18-BIT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16823AT/162823AT Com'l. Symbol Parameter Condition(1) Min.(2) Max. Mil. Min.(2) Max. FCT16823BT/162823BT Com'l. Min.(2) Max. Mil. Min.(2) Max. Unit
tPLH tPHL
Propagation Delay xCLK to xQx
tPHL tPZH tPZL
Propagation Delay xCLR to xQx Output Enable Time xOE to xQx
tPHZ tPLZ
Output Disable Time xOE to xQx
tSU tH tSU tH tW tW tREM
Set-up Time HIGH or LOW xDx to xCLK Hold Time HIGH or LOW xDx to xCLK Set-up Time HIGH or LOW xCLKEN to xCLK Hold Time HIGH or LOW xCLKEN to xCLK xCLK Pulse Width HIGH or LOW xCLR Pulse Width LOW Recovery Time xCLR to xCLK Skew (3)
CL = 50pF RL = 500 CL = 300pF(5) RL = 500 CL = 50pF RL = 500 CL = 50pF RL = 500 CL = 300pF(5) RL = 500 CL = 5pF(5) RL = 500 CL = 50pF RL = 500 CL = 50pF RL = 500
1.5 1.5 1.5 1.5 1.5 1.5 1.5 4.0 2.0 4.0 2.0 7.0 6.0 6.0 --
10.0 20.0 14.0 12.0 23.0 7.0 8.0 -- -- -- -- -- -- -- 0.5
1.5 1.5 1.5 1.5 1.5 1.5 1.5 4.0 2.0 4.0 2.0 7.0 7.0 7.0 --
11.5 20.0 15.0 13.0 25.0 8.0 9.0 -- -- -- -- -- -- -- 0.5
1.5 1.5 1.5 1.5 1.5 1.5 1.5 3.0 1.5 3.0 0 6.0 6.0 6.0 --
7.5 15.0 9.0 8.0 15.0 6.5 7.5 -- -- -- -- -- -- -- 0.5
1.5 1.5 1.5 1.5 1.5 1.5 1.5 3.0 1.5 3.0 0 6.0 6.0 6.0 --
8.5 16.0 9.5 9.0 16.0 7.0 8.0 -- -- -- -- -- -- -- 0.5
ns
ns ns
ns
ns ns ns ns ns ns ns ns
2772 tbl 09
tSK(o) Output
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. This limit is guaranteed but not tested. 5. This condition is guaranteed but not tested.
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IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET FAST CMOS 18-BIT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16823CT/162823CT Com'l. Symbol Parameter Condition(1) Min.(2) Max. Mil. Min.(2) Max. FCT16823ET/162823ET Com'l. Min.(2) Max. Mil. Min.(2) Max. Unit
tPLH tPHL
Propagation Delay xCLK to xQx
tPHL tPZH tPZL
Propagation Delay xCLR to xQx Output Enable Time xOE to xQx
tPHZ tPLZ
Output Disable Time xOE to xQx
tSU tH tSU tH tW tW tREM
Set-up Time HIGH or LOW xDx to xCLK Hold Time HIGH or LOW xDx to xCLK Set-up Time HIGH or LOW xCLKEN to xCLK Hold Time HIGH or LOW xCLKEN to xCLK xCLK Pulse Width HIGH or LOW xCLR Pulse Width LOW Recovery Time xCLR to xCLK
CL = 50pF RL = 500 CL = 300pF(5) RL = 500 CL = 50pF RL = 500 CL = 50pF RL = 500 CL = 300pF(5) RL = 500 CL = 5pF(5) RL = 500 CL = 50pF RL = 500 CL = 50pF RL = 500
1.5 1.5 1.5 1.5 1.5 1.5 1.5 3.0 1.5 3.0 0 6.0 6.0 6.0 --
6.0 12.5 8.0 7.0 12.5 6.2 6.5 -- -- -- -- -- -- -- 0.5
1.5 1.5 1.5 1.5 1.5 1.5 1.5 3.0 1.5 3.0 0 6.0 6.0 6.0 --
7.0 13.5 8.5 8.0 13.5 6.2 6.5 -- -- -- -- -- -- -- 0.5
1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 0.0 2.5 0.0 3.0 (4) 3.0 (4) 3.0 --
4.4 8.0 4.4 4.4 9.0 3.6 3.6 -- -- -- -- -- -- -- 0.5
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
ns
ns ns
ns
ns ns ns ns ns ns ns ns
2772 tbl 10
tSK(o) Output Skew (3)
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. This limit is guaranteed but not tested. 5. This condition is guaranteed but not tested.
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IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET FAST CMOS 18-BIT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
V CC 500 VIN Pulse Generator RT D.U.T. 50pF CL 500 VOUT 7.0V
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Open
2772 lnk 10 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Switch
Closed
2772 drw 05
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU
tH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
2772 drw 06
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
tREM
1.5V
2772 drw 07
tSU
tH
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE DISABLE 3V 1.5V tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 1.5V 0V 3.5V 1.5V tPHZ 0.3V VOH 0V
2772 drw 09
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
2772 drw 08
CONTROL INPUT tPLZ
0V 3.5V 0.3V VOL
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns
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IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET FAST CMOS 18-BIT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT FCT XX XXXX Temp. Range Device Type X Package X Process Blank B PV PA PF E Commercial MIL-STD-883, Class B Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) CERPACK (E56-1)
16823AT Non-Inverting 18-Bit Register 16823BT 16823CT 16823ET 162823AT 162823BT 162823CT 162823ET 54 74 -55C to +125C -40C to +85C
2772 drw 10
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