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(/1, /2/3) OR (/2, /4/6) CLOCK GENERATION CHIP
ClockWorksTM SY100S838 SY100S838L
FEATURES
s s s s s s 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75K input pull-down resistors Available in 20-pin SOIC package
DESCRIPTION
The SY100S838/L is a low skew (/1, /2/3) or (/2, /4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be ACcoupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01F capacitor. The VBB output is designed to act as the switching reference for the input of the SY100S838/L under singleended input conditions. As a result, this pin can only source/sink up to 0.5mA of current. The Function Select (FSEL) input is used to determine what clock generation chip function is. When FSEL input is LOW, SY100S838/L functions as a divide by 2 and by 4/6 clock generation chip. However, if FSEL input is HIGH, it functions as a divide by 1 and by 2/3 clock chip. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as for multiple SY100S838/Ls in a system.
PIN CONFIGURATION
VCC 20 Q0 19 Q0 18 Q1 17 Q1 16 Q2 15 Q2 14 Q3 13 Q3 12 VEE 11
TOP VIEW SOIC Z20-1
1 VCC
2 EN
3
4
5 CLK
6 VBB
7 MR
8 VCC
9 NC
10 FSEL
DIVSEL CLK
TRUTH TABLE
CLK Z ZZ X EN L H X MR L L H Function Divide Hold Q0-3 Reset Q0-3
NOTES: Z = LOW-to-HIGH transition ZZ = HIGH-to-LOW transition
PIN NAMES
Pin CLK Function Differential Clock Inputs Function Select Input Synchronous Enable Master Reset Reference Output Differential /1 or /2 Outputs Differential /2/3 or /4/6 Outputs Frequency Select Input
Rev.: E Amendment: /1
FSEL L L H H
DIVSEL L H L H
Q0, Q1 OUTPUTS Divide by 2 Divide by 2 Divide by 1 Divide by 1
Q2, Q3 OUTPUTS Divide by 4 Divide by 6 Divide by 2 Divide by 3
FSEL EN MR VBB Q0, Q1 Q2, Q3 DIVSEL
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Issue Date: August, 1998
Micrel
ClockWorksTM SY100S838 SY100S838L
BLOCK DIAGRAM
CLK CLK
/1
1 Q0 Q0 Q1 Q1
/2
0
EN
R
/ 2 or /3
1 Q2 Q2 Q3 Q3
MR FSEL DIVSEL
/ 4 or /6
0
DC ELECTRICAL CHARACTERISTICS(1)
VEE = VEE (Min.) to VEE (Max.); VCC = GND
TA = -40C Symbol IEE VBB IIH Parameter Power Supply Current Output Reference Voltage Input High Current TA = 0C TA = +25C TA = +85C Unit mA V A Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 35 -1.38 -- 50 -- -- 65 35 50 -- -- 65 35 50 -- -- 65 35 54 -- -- 75 -1.26 150
-1.26 -1.38 150 --
-1.26 -1.38 150 --
-1.26 -1.38 150 --
NOTE: 1. Parametric values specified at:
5 volt Power Supply Range 3 volt Power Supply Range
100S838 Series: 100S838L Series
-4.2V to -5.5V. -3.0V to -3.8V.
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Micrel
ClockWorksTM SY100S838 SY100S838L
AC ELECTRICAL CHARACTERISTICS(1)
VEE = VEE (Min.) to VEE (Max.); VCC = GND
TA = -40C Symbol fMAX tPLH tPHL Parameter Maximum Toggle Frequency Propagation Delay to Output CLK Output (Diff.) CLK Output (S.E.) MR Q Within-Device Skew(2) Q0 -- Q3 Part-to-Part tS tH VPP VCMR tRR tPW tr tf Set-up Time Hold Time Q0 -- Q3 (Diff.) EN CLK DIVSEL CLK CLK EN CLK DIVSEL CLK CLK Range(4) TA = 0C TA = +25C TA = +85C Unit MHz ps 950 900 600 -- -- 300 300 400 400 250 (4) -- CLK MR Q 800 700 280 -- -- -- -- -- 150 -- 150 200 -- -- -- -- -- -- 1150 1200 900 50 200 -- -- -- -- -- -0.55 100 -- -- 550 950 900 600 -- -- 300 300 400 400 250 (4) -- 800 700 280 -- -- -- -- -- 150 -- 150 200 -- -- -- -- -- -- 1150 1200 900 50 200 -- -- -- -- -- -0.55 100 -- -- 550 970 920 600 -- -- 300 300 400 400 250 (4) -- 800 700 280 -- -- -- -- -- 150 -- 150 200 -- -- -- -- -- -- 1170 1050 1220 1000 900 600 50 200 -- -- -- -- -- -0.55 100 -- -- 550 -- -- 300 300 400 400 250 (4) -- 800 700 280 -- -- -- -- -- 150 -- 150 200 -- -- -- -- -- -- 1250 1300 900 50 200 -- -- -- -- -- -0.55 100 -- -- 550 ps ps mV V ps ps ps ps Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 1000 -- -- 1000 -- -- 1000 -- -- 1000 -- --
tskew
Minimum Input Swing(3) Common Mode Reset Recovery Time Minimum Pulse Width Output Rise/Fall Times (20% --80%)
NOTES: 1. Parametric values specified at:
5 volt Power Supply Range 100S838 Series: -4.2V to -5.5V. 3 volt Power Supply Range 100S838L Series -3.0V to -3.8V. 2. Skew is measured between outputs under identical transitions. 3. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV. 4. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP (min) and 1.0V. The lower end of the CMR range is dependent on VEE and is equal to VEE +1.65V.
TIMING DIAGRAM
CLK Q (/1) Q (/2) Q (/3) Q (/4) Q (/6)
PRODUCT ORDERING CODE
Ordering Code SY100S838ZC SY100S838ZCTR SY100S838LZC SY100S838LZCTR Package Type Z20-1 Z20-1 Z20-1 Z20-1 Operating Range Commercial Commercial Commercial Commercial VEE Range (V) -4.2 to -5.5 -4.2 to -5.5 -3.0 to -3.8 -3.0 to -3.8 3 Ordering Code SY100S838ZI SY100S838ZITR SY100S838LZI SY100S838LZITR Package Type Z20-1 Z20-1 Z20-1 Z20-1 Operating Range Industrial Industrial Industrial Industrial VEE Range (V) -4.2 to -5.5 -4.2 to -5.5 -3.0 to -3.8 -3.0 to -3.8
Micrel
ClockWorksTM SY100S838 SY100S838L
20 LEAD SOIC .300" WIDE (Z20-1)
Rev. 03
MICREL-SYNERGY
TEL
3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
FAX
+ 1 (408) 980-9191
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated
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