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A617308 Series
Preliminary
Document Title 128K X 8 BIT HIGH SPEED CMOS SRAM Revision History
Rev. No.
0.0 0.1
128K X 8 BIT HIGH SPEED CMOS SRAM
History
Initial issue Change VDR(Max.) from 3.6V to 5.5V Add 32-pin SOP package Modify 32-pin SOJ package outline drawing and Dimensions
Issue Date
September 17, 1999 November 30, 1999
Remark
Preliminary
0.2
Add 15ns part Change operating current from 180mA to 150mA (Max.) Change VDR(Min.) from 2V to 3V Remove 32-pin SOP package
January 19, 2000
PRELIMINARY
(January, 2000, Version 0.2)
AMIC Technology, Inc.
A617308 Series
Preliminary
Features
n Single + 5V power supply n Access times: 10/12/15 ns (max.) n Current: Operating: 150mA (max.) Standby: 12mA (max.) n Full static operation, no clock or refreshing required n n n n All inputs and outputs are directly TTL compatible Common I/O using three-state output Data retention voltage: 3V (min.) Available in 32-pin SOJ and TSOP packages
128K X 8 BIT HIGH SPEED CMOS SRAM
General Description
The A617308 is a high-speed, low-power 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 5V power supply. It is built using high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Minimum standby power is drawn by this device when chip enable is disable, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 3V.
Pin Configurations
n SOJ n TSOP
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O 0 I/O 1 I/O 2 GND
1 2 3 4 5 6
32 31 30 29 28 27
VCC
CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3
~
A15 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
7 8 9 10 11 12 13 14 15 16
26 25 24 23 22 21 20 19 18 17
A617308V
PRELIMINARY
(January, 2000, Version 0.2)
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AMIC Technology, Inc.
~ ~
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE1 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 GND I/O 2 I/O 1 I/O 0 A0 A1 A2 A3
A617308S
A617308 Series
Block Diagram
A0 ADDRESS DECODER A16 1,048,576-BIT MEMORY ARRAY
I/O0 - I/O7
8 I/O CONTROL
8
8
WE OE CE1 CE2
CONTROL LOGIC
Pin Descriptions - SOJ
Pin No. 2 - 12, 23, 25 - 28, 31 13 - 15, 17 - 21 22 30 24 29 32 16 1 Symbol A0 - A16 Description Address Inputs
Pin Description - TSOP
Pin No. 1 - 4, 7, 10 - 20, 31 21 - 23, 25 - 29 30 6 32 5 8 24 9 Symbol A0 - A16 Description Address Inputs
I/O0 - I/O7
CE1
Data Inputs/Outputs Chip Enable 1 Chip Enable 2 Output Enable Write Enable Power Supply Ground No Connection
I/O0 - I/O7
CE1
Data Inputs/Outputs Chip Enable 1 Chip Enable 2 Output Enable Write Enable Power Supply Ground No Connection
CE2
OE WE
CE2
OE WE
VCC GND NC
VCC GND NC
PRELIMINARY
(January, 2000, Version 0.2)
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AMIC Technology, Inc.
A617308 Series
Recommended DC Operating Conditions
(TA = 0C to + 70C) Symbol VCC GND VIH VIL CL Parameter Supply Voltage Ground Input High Voltage Input Low (1) Voltage Output Load Min. 4.5 0 2.2 -0.5 Typ. 5.0 0 0 Max. 5.5 0 VCC + 0.5 +0.8 30 Unit V V V V pF
Absolute Maximum Ratings*
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V IN, IN/OUT Volt to GND . . . . . . . . . . -0.5V to VCC +0.5V Operating Temperature, Topr . . . . . . . . . . . 0C to +70C Storage Temperature, Tstg . . . . . . . . . . -55C to +125C Temperature Under Bias, Tbias . . . . . . . . -10C to +85C Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . . . 1.0W
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics
Symbol Parameter
(TA = 0C to + 70C, VCC = 5V 10%, GND = 0V) A617308-10/12/15 Min. Max. 5 5 A A VIN = GND to VCC CE1 = VIH, CE2= VIL or OE = VIH VI/O = GND to VCC CE1 = VIL, CE2 = VIH , II/O = 0 mA Min. Cycle, Duty = 100% CE1 = VIH or CE2 = VIL CE1 VCC - 0.2V, CE2 0.2V VIN VCC -0.2V or VIN 0.2V IOL = 8 mA IOH = -4 mA Unit Conditions
ILI ILO
Input Leakage Output Leakage
-
ICC1 (2) ISB
Dynamic Operating Current
-
150 35
mA mA
ISB1 VOL VOH
Standby Power Supply Current
2.4
12 0.4 -
mA V V
Output Low Voltage Output High Voltage
Notes: 1. VIL = -3.0V for pulses less than 20 ns. 2. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns.
PRELIMINARY
(January, 2000, Version 0.2)
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AMIC Technology, Inc.
A617308 Series
Truth Table
Mode
CE1
H
CE2 X L H H H
OE
WE
I/O Operation High Z High Z High Z DOUT DIN
Supply Current ISB, ISB1 ISB, ISB1 ICC1 ICC1 ICC1
X X H L X
X X H H L
Standby Output Disable Read Write Note: X = H or L
X L L L
Capacitance (TA = 25C, f = 1.0MHz)
Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. 8 8 Unit pF pF Conditions VIN = 0V VI/O = 0V
* These parameters are sampled and not 100% tested.
AC Characteristics (TA = 0C to +70C, VCC = 5V 10%)
Symbol Parameter A617308-10 Min. Read Cycle tRC tAA tACE tOE tCLZ tOLZ tCHZ tOHZ tOH Read Cycle Time Address Access Time Chip Enable Access Time Output Enable to Output Valid Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable Output in High Z Output Disable to Output in High Z Output Hold from Address Change 10 3 0 0 0 3 10 10 5 5 5 12 3 0 0 0 3 12 12 6 6 6 15 3 0 0 3 15 15 8 8 8 ns ns ns ns ns ns ns ns ns Max. A617308-12 Min. Max. A617308-15 Min. Max. Unit
PRELIMINARY
(January, 2000, Version 0.2)
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AMIC Technology, Inc.
A617308 Series
AC Characteristics (continued)
Symbol Parameter A617308-10 Min. Write Cycle tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW Write Cycle Time Chip Enable to End of Write Address Setup Time of Write Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 10 9 0 9 9 0 0 5 0 3 5 12 10 0 10 10 0 0 6 0 3 6 15 12 0 12 12 0 0 7 0 3 8 ns ns ns ns ns ns ns ns ns ns Max. A617308-12 Min. Max. A617308-15 Min. Max. Unit
Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.
Timing Waveforms
Read Cycle 1(1)
tRC Address tAA
OE
tOE tOLZ5
tOH
CE1
CE2 tACE tCLZ 5 DOUT tCHZ5 tOHZ5
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(January, 2000, Version 0.2)
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AMIC Technology, Inc.
A617308 Series
Timing Waveforms (continued)
Read Cycle 2(1, 2, 4)
tRC Address
tAA tOH tOH
DOUT
Read Cycle 3(1, 3, 4, 6)
CE1
tACE tCLZ 5
tCHZ 5
DOUT
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(January, 2000, Version 0.2)
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AMIC Technology, Inc.
A617308 Series
Timing Waveforms (continued)
Read Cycle 4(1, 4, 7, 8)
CE2
tACE tCLZ 5
tCHZ 5
DOUT
Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled, CE1= VIL and CE2= VIH 3. Address valid prior to or coincident with CE1 transition low. 4. 5. 6. 7. 8.
OE = VIL. Transition is measured 200mV from steady state. This parameter is sampled and not 100% tested. CE2 is high. CE1 is low. Address valid prior to or coincident with CE2 transition high.
Write Cycle 1(6) (Write Enable Controlled)
tWC Address tAW tCW5 CE1 (4) tWR3
CE2
(4) tAS1 tWP2
WE
tDW
tDH
DIN tWHZ7 tOW7 DOUT
PRELIMINARY
(January, 2000, Version 0.2)
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AMIC Technology, Inc.
A617308 Series
Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled)
tWC Address tAW tCW5 CE1 tAS1 (4) tWR3
CE2
(4)
tWP2 WE
tDW
tDH
DIN
tWHZ7
DOUT
Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low WE . 3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle. 4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured 200mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY
(January, 2000, Version 0.2)
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AMIC Technology, Inc.
A617308 Series
AC Test Conditions
Input Pulse Levels Input Rise and Fall Time Input and Output Timing Reference Levels Output Load 0V to 3.0V 2 ns 1.5V See Figures 1 and 2
5V 480 DATAOUT 30pF 255 DATAOUT 5pF*
5V 480
255
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW
Data Retention Characteristics (TA = 0C to 70C)
Symbol VDR Parameter VCC for Data Retention Min. 3 Max. 5.5 Unit V Conditions
CE1 VCC - 0.2V
ICCDR
Data Retention Current
-
1
mA
VCC = 3.0V CE1 VCC - 0.2V CE2 0.2V VIN VCC - 0.2V or VIN 0.2V
tCDR tR
Chip Disable to Data Retention Time Operation Recovery Time
0 TRC*
-
ns See Retention Waveform ms
tRC = Read Cycle Time
PRELIMINARY
(January, 2000, Version 0.2)
9
AMIC Technology, Inc.
A617308 Series
Low VCC Data Retention Waveform (1) (CE1 controlled)
DATA RETENTION MODE VCC 4.5V tCDR VDR > 3.0V 4.5V tR
CE1
VIH CE1 > VDR - 0.2V
VIH
Low VCC Data Retention Waveform (2) (CE2 controlled)
DATA RETENTION MODE VCC 4.5V tCDR VDR > 3.0V 4.5V tR
CE2
VIL CE2 < 0.2V
VIL
Ordering Information
Part No. A617308S-10 A617308S-12 A617308S-15 A617308V-10 A617308V-12 A617308V-15 Access Time (ns) 10 12 15 10 12 15 Operating Current Max. (mA) 150 150 150 150 150 150 Standby Current Max. (mA) 12 12 12 12 12 12 Package 32L SOJ 32L SOJ 32L SOJ 32L TSOP 32L TSOP 32L TSOP
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(January, 2000, Version 0.2)
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AMIC Technology, Inc.
A617308 Series
Package Information SOJ 32L Outline Dimensions
unit: inches/mm
D 32 17
1
16
E1
E A2 C A y E2 y S Seating Plane D
Symbol A A1 A2 b b1 C D E E1 E2 e S y
Dimensions in inches Min 0.128 0.052 0.095 0.016 0.026 0.006 0.820 0.330 0.295 0.260 Nom 0.132 0.100 0.018 0.028 0.008 0.825 0.335 0.300 0.267 0.050 Max 0.140 0.105 0.020 0.032 0.012 0.830 0.340 0.305 0.274 0.048 0.004
Min 0.025"
y
b b1
e
0.004
Dimensions in mm Min 3.25 2.08 2.41 0.41 0.66 0.15 20.83 8.39 7.49 6.61 Nom 3.35 2.54 0.46 0.71 0.20 20.96 8.51 7.62 6.78 1.27 Max 3.56 2.67 0.51 0.81 0.30 21.08 8.63 7.75 6.96 1.22 0.10
Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension E1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash.
A1
PRELIMINARY
(January, 2000, Version 0.2)
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AMIC Technology, Inc.
A617308 Series
Package Information TSOP 32L TYPE I (8 X 20mm) Outline Dimensions
unit: inches/mm
D
e
A2
E
A1
c
L LE
HD Detail "A"
Detail "A"
y
D
S
b
Dimensions in inches Symbol A A1 A2 b c D E e HD L LE S y 0.779 0.016 0 Min 0.002 0.037 0.007 0.004 0.720 Nom 0.039 0.009 0.724 0.315 0.020 BSC 0.787 0.020 0.032 0.795 0.024 0.020 0.003 5 Max 0.047 0.006 0.041 0.011 0.008 0.728 0.319
Dimensions in mm Min 0.05 0.95 0.18 0.11 18.30 Nom 1.00 0.22 18.40 8.00 0.50 BSC 19.80 0.40 0 20.00 0.50 0.80 20.20 0.60 0.50 0.08 5 Max 1.20 0.15 1.05 0.27 0.20 18.50 8.10
Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash.
PRELIMINARY
(January, 2000, Version 0.2)
12
AMIC Technology, Inc.
A
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