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LCP1521S/LCP152DEE ASD (Application Specific Devices) Programmable transient voltage suppressor for SLIC protection Features Dual programmable transient suppressor Wide negative firing voltage range: VMGL = -150 V max. Low dynamic switching voltages: VFP and VDGL Low gate triggering current: IGT = 5 mA max Peak pulse current: IPP = 30 A (10/1000 s) Holding current: IH = 150 mA min Low space consuming package SO-8 LCP1521S QFN 3x3 6 leads LCP152DEE Order codes Part Number LCP1521S LCP1521SRL LCP152DEERL Marking CP152S CP152S LCP152 Description These devices have been especially designed to protect new high voltage, as well as classical SLICs, against transient overvoltages. Positive overvoltages are clamped by 2 diodes. Negative surges are suppressed by 2 thyristors, their breakdown voltage being referenced to -VBAT through the gate. These components present a very low gate triggering current (IGT) in order to reduce the current consumption on printed circuit board during the firing phase. Figure 1. LCP1521S Functional diagram TIP 1 TIP GATE GND NC GND Benefits TRISILsTM are not subject to ageing and provide a fail safe mode in short circuit for a better level of protection. Trisils are used to ensure equipment meets various standards such as UL60950, IEC950 / CSA C22.2, UL1459 and FCC part 68. Trisils have UL94 V0 approved resin (Trisils are UL497B approved [file: E136224]). RING RING Figure 2. LCP152DEE Functional diagram TIP TIP GATE GND NC RING RING TM: TRISIL is a trademark of STMicroelectronics July 2006 Rev 5 1/11 www.st.com 11 Characteristics LCP1521S/LCP152DEE 1 Characteristics Table 1. Standards compliance Standard Peak surge voltage (V) 2500 1000 5000 1500 6000 1500 8000 15000 4000 2000 4000 2000 4000 4000 1500 800 1000 Voltage waveform 2/10 s 10/1000 s 2/10 s 2/10 s 10/700 s 1/60 ns 10/700 s 1.2/50 s 10/700 s 1.2/50 s 10/160 s 10/560 s 9/720 s Required peak current (A) 500 100 500 100 150 37.5 Current waveform 2/10 s 10/1000 s 2/10 s 2/10 s 5/310 s Minimum serial resistor to meet standard () 12 24 24 0 110 0 0 0 60 10 0 0 60 0 22.5 15 0 GR-1089 Core First level GR-1089 Core Second level GR-1089 Core Intra-building ITU-T-K20/K21 ITU-T-K20 (IEC 61000-4-2) VDE0433 VDE0878 IEC61000-4-5 FCC Part 68, lightning surge type A FCC Part 68, lightning surge type B ESD contact discharge ESD air discharge 100 50 100 50 100 100 200 100 25 5/310 s 1/20 s 5/310 s 8/20 s 10/160 s 10/560 s 5/320 s Table 2. Symbol Rth(j-a) Thermal resistances Parameter Junction to ambient SO-8 QFN Value 120 140 Unit C/W 2/11 LCP1521S/LCP152DEE Table 3. Symbol IGT IH IRM IRG VRM VGT VF VFP VDGL VRG C Characteristics Electrical characteristics (Tamb = 25 C) Parameter I Gate triggering current Holding current Reverse leakage current LINE / GND Reverse leakage current GATE / LINE Reverse voltage LINE / GND Gate triggering voltage Forward drop voltage LINE / GND Peak forward voltage LINE / GND Dynamic switching voltage GATE / LINE Reverse voltage GATE / LINE Capacitance LINE / GND IPP VR VRM VF IRM IR IH V Table 4. Symbol Absolute ratings (Tamb = 25 C, unless otherwise specified) Parameter 10/1000 s 8/20 s 10/560 s 5/310 s 10/160 s 1/20 s 2/10 s t = 20 ms t = 200 ms t=1s t = 10 ms -40 C < Tamb < +85 C -40 C < Tamb < +85 C Value 30 100 35 40 50 100 150 18 10 7 2 -150 -150 -55 to +150 150 260 Unit IPP Peak pulse current A ITSM IGSM VMLG VMGL Tstg Tj TL Non repetitive surge peak on-state current (50Hz sinusoidal) Maximum gate current (50Hz sinusoidal) Maximum voltage LINE/GND Maximum voltage GATE/LINE Storage temperature range Maximum junction temperature A A V C C Maximum lead temperature for soldering during 10 s. Table 5. Symbol tr tp Repetitive peak pulse current Definition Rise time (s) Pulse duration (s) Example Pulse waveform 10/1000 s: tr = 10 s tp = 1000 s % IPP 100 50 0 tr tp t 3/11 Characteristics Table 6. Symbol VF VFP(1) 1. LCP1521S/LCP152DEE Parameters related to the diode LINE / GND (Tamb = 25 C) Test conditions IF = 5A 10/700 s 1.2/50 s 2/10 s 1.5 kV 1.5 kV 2.5 kV t = 500 s RS = 10 RS = 10 RS = 62 Max 3 5 9 30 Unit V V See test circuit for VFP (Figure 4.): RS is the protection resistor located on the line card. Table 7. Symbol IGT IH VGT IRG Parameters related to the protection Thyristors (Tamb = 25 C, unless otherwise specified) Test conditions VGND / LINE = -48 V VGATE = -48 V(1) at IGT VRG = -150 V VRG = -150 V VGATE = -48 V(2) RS = 10 RS = 10 RS = 62 Tj = 25 C Tj = 85 C Typ 0.1 150 2.5 5 50 Max 5 Unit mA mA V A VDGL 10/700 s 1.2/50 s 2/10 s 1.5 kV 1.5 kV 2.5 kV IPP = 30 A IPP = 30 A IPP = 38 A 7 10 25 V 1. 2. see functional holding current (IH) test circuit see test circuit for VDG The oscillations with a time duration lower than 50ns are not taken into account. Table 8. Symbol IRM C Parameters related to diode and protection Thyristors (Tamb = 25 C, unless otherwise specified) Test conditions VGATE / LINE = -1 V VGATE / LINE = -1 V VRM = -150 V VRM = -150 V Tj = 25 C Tj = 85 C 15 35 Typ Max 5 50 Unit A pF VR = 50 V bias, VRMS = 1 V, F = 1 MHz VR = 2 V bias, VRMS = 1 V, F = 1 MHz 4/11 LCP1521S/LCP152DEE Figure 3. Characteristics Functional Holding Current (IH) test circuit: GO-NO GO test R Surge generator VBAT = - 100V D.U.T This is a GO-NO GO test which allows to confirm the holding current (IH) level in a functional test circuit. TEST PROCEDURE: - Adjust the current level at the IH value by short circuiting the D.U.T. - Fire the D.U.T. with a surge current: IPP = 10A, 10/1000s - The D.U.T. will come back to the off-state within a duration of 50ms max. Figure 4. Test circuit for VFP and VDGL parameters (V is defined in unload condition) P R4 TIP R2 RING R3 L VP C1 R1 C2 G ND Pulse (s) tr 10 1.2 2 tp 700 50 10 Vp (V) 1500 1500 2500 C1 (F) 20 1 10 C2 (nF) 200 33 0 L (H) 0 0 1.1 R1 () R2 () R3 () R4 () IPP (A) 30 30 38 Rs () 50 76 1.3 15 13 0 25 25 3 25 25 3 10 10 62 5/11 Technical information LCP1521S/LCP152DEE 2 Technical information Figure 5. LCP152 concept behavior Rs1 L1 TIP IG ID1 T1 Gate V Tip Th1 D1 GND GND -Vbat C Rs2 RING VRing L2 Figure 5. shows the classical protection circuit using the LCP152 crowbar concept. This topology has been developed to protect the new high voltage SLICs. It allows to program the negative firing threshold while the positive clamping value is fixed at GND. When a negative surge occurs on one wire (L1 for example) a current IG flows through the base of the transistor T1 and then injects a current in the gate of the thyristor Th1. Th1 fires and all the surge current flows through the ground. After the surge when the current flowing through Th1 becomes less negative than the holding current IH, then Th1 switches off. When a positive surge occurs on one wire (L1 for example) the diode D1 conducts and the surge current flows through the ground. Figure 6. Example of PCB layout based on LCP152S protection LCP1521S 220 nF To line side GND To SLIC side Figure 6. shows the classical PCB layout used to optimize line protection. The capacitor C is used to speed up the crowbar structure firing during the fast surge edges. This allows to minimize the dynamical breakover voltage at the SLIC Tip and Ring inputs during fast strikes. Note that this capacitor is generally present around the SLIC - Vbat pin. So to be efficient it has to be as close as possible from the LCP152 Gate pin and from the reference ground track (or plan) (see Figure 6.). The optimized value for C is 220 nF. The series resitors Rs1 and Rs2 designed in Figure 5. represent the fuse resistors or the PTC which are mandatory to withstand the power contact or the power induction tests 6/11 LCP1521S/LCP152DEE Technical information imposed by the various country standards. Taking into account this fact the actual lightning surge current flowing through the LCP is equal to: I surge = V surge / (Rg + Rs) With: V surge = peak surge voltage imposed by the standard. Rg = series resistor of the surge generator Rs = series resistor of the line card (e.g. PTC) e.g. For a line card with 30 of series resistors which has to be qualified under GR1089 Core 1000V 10/1000 s surge, the actual current through the LCP152 is equal to: I surge = 1000 / (10 + 30) = 25 A The LCP152 is particularly optimized for the new telecom applications such as the fiber in the loop, the WLL, the remote central office. In this case, the operating voltages are smaller than in the classical system. This makes the high voltage SLICs particularly suitable. The schematics of Figure 7. give the most frequent topology used for these applications. Figure 7. Protection of high voltage SLIC -Vbat Rs (*) TIP Gate TIP GND GND RING Rs (*) RING Line GND 220nF SLIC LCP152xx Line card Rs (*) = PTC or fuse resistor Figure 8. Surge peak current versus overload Figure 9. duration Relative variation of holding current versus junction temperature ITSM(A) 1.3 IH[Tj] / IH[Tj=25C] F=50Hz Tj initial=25C 24 20 1.2 1.1 16 1 12 0.9 8 0.8 4 Tj(C) t(s) 0 1.E-02 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 0.7 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 7/11 Package information LCP1521S/LCP152DEE 3 Package information Table 9. SO-8 Dimensions Dimensions Ref. Millimeters Min. A ccc C A2 A Inches Min. Typ. Max. 0.069 0.004 0.049 0.011 0.007 0.010 0.019 0.009 Typ. Max. 1.75 C (Seating Plane) C h x 45 0.25mm (Gage Plane) A1 A2 b C D E 0.1 1.25 0.28 0.17 4.80 5.80 3.80 0.25 0.40 1.04 0 4.90 6.00 3.90 1.27 0.25 0.48 0.23 5.00 6.20 4.00 0.50 1.27 8 0.10 b e A1 L k L1 D 0.189 0.193 0.197 0.228 0.236 0.244 0.150 0.154 0.157 0.050 0.010 0.016 0.041 0 8 0.004 0.020 0.050 8 5 E1 E E1 e h L L1 k ccc 1 4 Figure 10. Footprint (dimensions in mm) 8/11 LCP1521S/LCP152DEE Table 10. QFN 3x3 6 Leads Package dimensions Package information DIMENSIONS REF. Min. Millimeters Typ. Max. Min. Inches Typ. Max. A A1 A2 A3 b D D2 E E2 e L L1 L2 K < 0.80 0 0.65 20 0.33 2.90 1.92 2.90 1.11 0.95 0.20 0.24 3 3 1 0.05 0.75 0.031 0 0.026 0.787 0.040 0.002 0.030 0.43 3.10 2.12 3.10 1.31 0.013 0.017 0.114 0.118 0.122 0.076 0.083 0.114 0.118 0.122 0.044 0.037 0.051 0.45 0.008 0.009 0.018 0.13 0.20 0 12 0.008 0 0.005 12 Figure 11. QFN 3x3 6 Leads Footprint dimensions (in mm) 0.95 0.48 1.05 0.35 0.34 1.21 2.02 4.00 9/11 Ordering information LCP1521S/LCP152DEE 4 Ordering information Part Number LCP1521S LCP1521SRL (1) Marking CP152S Package SO-8 Weight 0.11 g Base qty 100 2500 Delivery mode Tube Tape and reel Tape and reel CP152S LCP152 QFN 3x3 6L 0.022 g LCP152DEERL(1) 1. Preferred device 3000 5 Revision history Date Sep-2003 08-Dec-2004 17-Feb-2005 03-May-2005 07-Jul-2006 Revision 1A 2 3 4 5 First issue. 1/ Page 2 table 3: Thermal resistances changed from 130 C/W (SO-8) to 120 C/W and from 170 C/W (QFN) to 140 C/W. 2/ SO-8 and QFN footprint dimensions added. Table 9 on page 4: correction of typo on capacitance unit. Table 5 on page 3: ITSM value @ t= 1s from 4 A to 4.5 A. Replaced QFN package illustration on page 1. Reformatted document to current layout standard. Values of ITSM modified in Table 4. SO-8 package dimensions updated in Table 9. Description of Changes 10/11 LCP1521S/LCP152DEE Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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