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| M61530FP 4ch Electronic Volume with 5.1ch Analog Input REJ03F0058-0100Z Rev.1.0 Sep.19.2003 Description The M61530FP is a four-channel volume IC which is optimal for combination with the M61519FP two-channel electronic volume. A multi-channel system is easily configured with the aid of these two chips. Features Function names Main volume control Low pass filter (LPF) AGC Bass boost Output gain control Input gain control Microcomputer I/F Features 0 to -87 dB in 1-dB steps, - Four independently controlled volumes (SL, SR, C, LFE) On-chip operational amplifiers for configuration of post-filters through the addition of external C and R elements AGC circuit is included to prevent clipping Application Mini-component systems, micro-component systems, etc. Recommended Operating Conditions Power-supply voltage range: Vcc = 8 to 10 V Rated power-supply voltage: Vcc = 9 V Rev.1.0, Sep.19.2003, page 1 of 18 M61530FP System Block Diagram M 61530FP LI N RIN FLIN FRIN SLIN SL_EXTIN M61519FP Input selector L-LPF R-LPF 0,+5,+10dB Input selector Surround or DPL buffer Tone VOL Bass booster LOUT ROUT Tone VOL Bass booster FL-LPF 0,+5,+10dB FR-LPF SL-LPF SR-LPF +6dB SLchVOL +6dB Bass booster SLOUT SRchVOL Bass booster SRIN SR_EXTIN SROUT C-LPF +6dB CchVOL CIN LFEIN SWIN COUT LFEchVOL AGC SW-LPF 0,+6, +9,+12dB SWOUT Rev.1.0, Sep.19.2003, page 2 of 18 M61530FP Block diagram with pin connections FR_LPFOUT FR_LPFIN SL_EXTIN SL_VOLIN SL_LPFOUT SL_LPFIN SR_EXTIN SR_VOLIN SR_LPFOUT 1 2 3 FRch LPF amp FR input gain control 0,+5,+10dB FL input gain control 0,+5,+10dB FLch LPF amp 42 FL_LPFOUT 41 FL_LPFIN 40 R_LPFIN SLVOLXY input SW SL ch volume Rch LPF amp 4 5 6 +6dB 0 to -87dB,- 39 R_LPFOUT 38 L_LPFOUT 37 L_LPFIN SLch LPF amp Lch LPF amp 7 SRVOL input SW SRch volume VREF amp 36 REFIN 35 REFOUT 34 FL_OUT 8 9 0 to -87dB,- SRch LPF amp FL output SW SR_LPFIN 10 +6dB 33 FR_IN Cch volume 0 to -87dB ,- OFF FR output SW ON C_VOLIN 11 C_LPFOUT 12 C_LPFIN 13 +6dB 32 FR_OUT 31 SL_BB1 Cch LPF amp Bass booster ON/OFF 30 SL_BB2 29 SL_OUT LFEch volume 0 to -87dB,- Bass booster LFE_VOLIN 14 SW_IN 15 VCC 16 28 SR_BB1 Bass booster ON/OFF 27 SR_BB2 26 SR_OUT DATA 17 Microcomputer I/F SW MIX SW LFEMIX SW Bass booster CLOCK 18 GND 19 TEST 20 AGC 21 25 C_OUT AGC SW output-gain control 0,+6,+9,+12dB 24 SW_OUT 23 SW_LPFIN 22 SW_LPFOUT SWch LPF amp Rev.1.0, Sep.19.2003, page 3 of 18 M61530FP Pin description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin Name FR_LPFOUT FR_LPFIN SL_EXTIN SL_VOLIN SL_LPFOUT SL_LPFIN SR_EXTIN SR_VOLIN SR_LPFOUT SR_LPFIN C_VOLIN C_LPFOUT C_LPFIN LFE_VOLIN SW_IN VCC DATA CLOCK GND TEST AGC SW_LPFOUT SW_LPFIN SW_OUT C_OUT SR_OUT SR_BB2 SR_BB1 SL_OUT SL_BB2 SL_BB1 FR_OUT FR_IN FL_OUT REFOUT REFIN L_LPFI N L_LPFOUT R_LPFOUT R_LPFIN FL_LPFIN FL_LPFOUT Description Configure a low-pass filter by adding external C and R elements to the input of the FR channel SL channel external input pin SL channel volume input pin Configure a low-pass filter by adding external C and R elements to the input of the SL channel SR channel external input pin SR channel volume input pin Configure a low-pass filter by adding external C and R elements to the input of SR channel C channel volume input pin Configure a low-pass filter by adding external C and R elements to the input of the C channel LFE channel volume input pin SW channel input pin Power-supply pin for internal analog and digital circuitry (VCC = 9 V) DATA input pin for serial data transfer CLOCK input pin for serial data transfer GND pin for internal analog and digital circuitry Pin for setting the test mode (normally fixed low) C connection pin for setting attack/recovery time for AGC Configure a low-pass filter by adding external C and R elements to the input of the SW channel SW channel output pin C channel output pin SR channel output pin Pin for connecting external components that set bass-boost frequency characteristics for the SR channel SL channel output pin Pin for connecting external components that set bass-boost frequency characteristics for the SL channel FR channel output pin Pin for interfacing with the M61519FP surround circuit FL channel output pin Internal reference output pin Internal reference input pin Configure a low-pass filter by adding external C and R elements to the input of the L channel Configure a low-pass filter by adding external C and R elements to the input of the R channel Configure a low-pass filter by adding external C and R elements to the input the of FL channel Rev.1.0, Sep.19.2003, page 4 of 18 M61530FP Absolute Maximum Ratings Parameter Power-supply voltage Internal power dissipation Thermal reduction rate Ambient operating temperature Storage temperature Symbol VCC Pd K Topr Tstg Ratings 10.5 850 8.6 -20 to +75 -40 to +125 Unit V mW mW/C C C Ta25C Ta>25C Conditions Thermal derating curve 1.0 0.85W Internal power dissipation pd [W] 0.75 0.5 0.42 0.25 0 25 50 75 100 125 150 Ambient temperature Ta [C] Recommended Operating Condition (Unless otherwise noted, Ta = 25C) Limits Item Power-supply voltage Logical high level input voltage Logical low level input voltage Symbol VCC VIH VIL Min. 8 2.2 0 Typ. 9 Max. 10 5.5 0.6 Unit V V V VCC=9V VCC=9V Condition Rev.1.0, Sep.19.2003, page 5 of 18 M61530FP Relation between DATA and CLOCK Latch condition CLOCK D0 D1 D2 D3 D13 D14 D15 DATA The data signal is read on the rising edges of the CLOCK signal The DATA line is driven high to latch D0 to D15 at this time 1. Data transmission The DATA signal is read on the rising edges of the CLOCK signal. The DATA line must always be low on the falling edge of the CLOCK signal during transmission of the DATA signal. 2. Data Latch Data for this IC is in 16-bits (D0 to D15) words. Latch the transmitted data by driving the DATA line high on the falling edge of the CLOCK signal after the transmission of D15. CLOCK and DATA timing (D0 to D15) (D15) L ATCH signal tcr DATA tSLD 75% tHLD tSHD tHHD tSLD tHLD CLOCK 25% tr tWHC tf tWLC Rev.1.0, Sep.19.2003, page 6 of 18 M61530FP Digital module timing Limits Item Clock: Cycle time Clock: Pulse width (high) Clock: Pulse width (low) Clock: Rising time Clock: Falling time Data: Setup time (high), clock rising Data: Setup time (low), clock falling Data: Hold time (high) Data: Hold time (low) Symbol tcr tWHC tWLC tr tf tSHD tSLD tHHD tHLD Min. 4 1.6 1.6 0.8 0.8 0.8 0.8 Typ. Max. 0.4 0.4 Unit S Rev.1.0, Sep.19.2003, page 7 of 18 M61530FP Data input format (Set all data shown below to the initial values every time power is turned on.) (1) D0a D1a D2a (8) SLch trim potentiometer D3a D4a D5a D6a (8) D7a D8a D9a (1) D10a D11a D12a D13a D14 (2) (3) (4) (5) FL/FR Input LFEMIX SWMIX output SW for SW SW SW SL/SR volume D15 0 SRch trim potentiometer FL/FR input gain control 0 (2) D0b D1b D2b (8) Cch trim potentiometer D3b D4b D5b D6b (8) D7b D8b (6) D9b D10b D11b D12b D13b D14 (7) D15 1 LFEch trim volume Bass SW output gain control boost 0 0 0 0 (3) D0c D1c D2c (9) SLch master volume D3c D4c D5c D6c D7c (9) D8c D9c D10c D11c D12c D13c D14 0 0 0 0 1 D15 0 SRch master volume (4) D0d D1d D2d (9) Cch master volume D3d D4d D5d D6d D7d (9) D8d D9d D10d D11d D12d D13d D14 0 0 0 0 1 D15 1 LFEch master volume Code settings (1) FL/FR input gain control Setting 0dB +5dB +10dB D8a 0 0 1 D9a 0 1 0 (3) Input switch for SL/SR volume (5) SW MIX SW Setting SL/SRch input External input D11a 0 1 Setting ON OFF D13a 0 1 : Initial setting (6) Bass boost Setting OFF ON D8b 0 1 (2) FL/FR output SW Setting ON OFF D10a 0 1 (4) LFE MIX SW Setting ON OFF D12a 0 1 (7) SW output gain control Setting 0dB +6dB +9dB +12dB D9b 0 0 1 1 D10b 0 1 0 1 Note: Do not use data codes other than those specified above. Rev.1.0, Sep.19.2003, page 8 of 18 M61530FP (8) SL/SR/C/LFEch trim volume SLch Attenu ation SRch Cch D0a D4a D0b D4b 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D1a D5a D1b D5b 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D2a D6a D2b D6b 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D3a D7a D3b D7b 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Attenu ation (9) SL/SR/C/LFEch master volume SLch SRch Cch D0c D5c D0d D5d 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D1c D6c D1d D6d 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2c D7c D2d D7d 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D3c D8c D3d D8d 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D4c D9c D4d D9d 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 LFEch 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB -8dB -9dB -10dB -11dB -12dB -13dB -14dB -15dB LFEch 0dB -2dB -4dB -6dB -8dB -10dB -12dB -14dB -16dB -18dB -20dB -22dB -24dB -26dB -28dB -30dB -32dB -34dB -36dB -38dB -40dB -42dB -44dB -48dB -52dB -56dB -60dB -64dB -68dB -72dB -76dB -dB Note: When the sum of the trim potentiometer and master volume settings is -87 dB or less, the overall level is -87 dB (e.g. when the trim potentiometer is -15 dB and master volume is -76 dB, the total level becomes -87 dB). Note: Do not use data codes other than those specified above. Rev.1.0, Sep.19.2003, page 9 of 18 M61530FP Electrical characteristics Unless otherwise noted, Ta = 25C, Vcc = 9 V, f = 1 kHz, input gain control = 0 dB, bass boost = off, trim/master volume = 0 dB, FL/FR output SW = on, SL/SR VOL input SW = SL/SR input, LFE MIXS SW = on, SW MIX= off, output gain control = 0 dB Limits Item Power supply I/O Circuit current Max. input voltage Symbol IACC VIM1 VIM2 VIM3 Absolute max. input voltage Max. output voltage AVIM VOM1 VOM2 VOM3 Bypass gain GV1 GV2 GV3 Output noise voltage Vno1 Min. 1.6 0.8 1.6 1.8 1.6 1.4 +2.3 -2 -2 Typ. 14 2.0 1.0 2.0 2.4 2.0 1.8 +4.3 0 0 6.0 2.5 6.0 2.0 6.5 6.5 Max. 25 2.0 Note +6.3 +2 +2 12.0 8.0 10.0 4.0 16.0 16.0 Unit mA Vrms Vrms Vrms Vrms Vrms Vrms Vrms dB dB dB Vrms Vrms Vrms Vrms Vrms Vrms Condition When no signal is detected, current flows to pin 16 Pins 2, 37, 40, and 41: Input, pins 1, 38, 39, and 42: Output, RL = 10 k, THD = 1% Pins 6, 10, and 13: Input, pins 5, 9, and 12: Output, RL = 10 k, THD = 1% Pin 14: Input, pin 22: Output, RL = 10 k, THD = 5%, f = 100 kHz Pins 3, 7, 14, and 15: Input Pins 6 and 10: Input, pins 29 and 26: Output, RL = 10 k, THD = 5%, bass boost = on, f = 100 Hz Pin 13: Input, pin 25: Output, RL = 10 k, THD = 5% Gain between pins 14 and 22, Vi = 0.5 Vrms, FLAT, f = 100 Hz Gain from pins 6 to 29, pin 10 to 26, and pins 13 to 25, Vi = 0.5 Vrms, FLAT Gain from pins 2 to 32 and 41 to 34, Vi = 0.5 Vrms, FLAT Gain from pin 14 to 22, Vi = 0.5 Vrms, FLAT, f = 100 Hz DIN-Audio, when no signal is present, Rg = 0 for pins 6 and 10, pins 29 and 26 are outputs DIN-Audio, when no signal is present, Rg = 0 for pin 13, pin 25 is an output DIN-Audio, when no signal is detected, Rg = 0 for pin 14, pin 22 is an output, SW ch LPF: fc=300 Hz SL/SR ch volume = - dB C ch volume = 0 dB C ch volume = - dB LFE ch volume = 0 dB LFE ch volume = - dB Vno2 Vno3 Total harmonic distortion rate THD1 THD2 THD3 0.003 0.003 0.008 0.2 0.1 0.2 % % % Pins 6 and 10: input, pins 29 and 26: output, bandwidth: 400 Hz to 30 kHz, Vo = 0.5 Vrms, RL = 10 k Pin 13: input, pin 25: output, bandwith: 400 Hz to 30 kHz, Vo = 0.5 Vrms, RL = 10 k Pin 14: input, pin 22: output, 30-kHz low-pass filter, Vo = 0.5 Vrms, RL = 10 k, output gain control = 0 dB, when AGC is not operating, f = 100 Hz Pin 14: input, pin 22: output, 30-kHz low-pass filter, RL = 10 k, Vi = 700 mVrms, f = 100 Hz, when AGC is operating, output gain control = + 12 dB Vo = 1 Vrms, pins 22, 25, 26, and 29 are outputs, JIS-A, volume = - THD4 2 % Volume max. attenuation ATT -100 -87 dB Rev.1.0, Sep.19.2003, page 10 of 18 M61530FP Limits Item I/O Max. gain Symbol GVM1 GVM2 Crosstalk between channels CT Min. +8 +10 Typ. +10 +12 -90 Max. +12 +14 -55 Unit dB dB dB Condition Gain from pin 2 to 32 and 41 to 34, Vi = 0.1 Vrms, FLAT, input gain control = + 10 dB Gain between pins 14 and 22, f = 100 Hz Vi = 0.1 Vrms, FLAT, output gain control = + 12 dB Gain from pins 6 to 29, pins 10 to 26, pins 13 to 25, and pins 14 to 22, Vi = 0.5 Vrms, JIS-A, RL = 47 k, Rg = 0 , input on a channel other than the measurement target Pin 14: input, pin 22: output, RL = 10 k, output gain control = +12 dB Pin 14: input, pin 22: output, RL = 10 k, output gain control = +12 dB AGC Attack time Recovery time TAGCAT TAGCRE 40 850 ms ms Note: The voltage on pins 3, 7, 14, and 15 must not exceed the the absolute maximum input-voltage range (2 Vrms). Rev.1.0, Sep.19.2003, page 11 of 18 MD TAPE TUNER MIC IN MIC IN M61530FP CD DVD MIC SW M61519FP Tone control (bass/mid/treble) Master volume Bass booster Tone control (bass/mid/treble) Pre-tone control attenuator Bypass RECA SW Rch 4-ch input selector + mute Pre-tone-control attenuator Bypass System block diagram Lch Lch Vocal cut Surround /DPL Buff 38 37 RECB1 RECB2 Master volume Bass booster Rev.1.0, Sep.19.2003, page 12 of 18 Rch 39 4-ch input selector + mute 40 RECA2/INex2 RECA1/INex1 M61530FP + M61519FP application example Spectrum analyzer FLch 41 34 42 FL output SW 0, +5,+10dB 33 FRch 2 32 1 M61519FP Max. output voltage 2Vrms 0, +5,+10dB FR output SW SLVOL input SW 0 to -87dB,- SLchVOL +6dB 28 3 4 5 M 61530FP 31 Bass booster 30 29 S-Lch 6 SLch OUT 7 8 9 0 to -87dB,- SRVOL input SW SRchVOL Bass booster 27 26 S-Rch +6dB 11 12 10 SRch OUT 25 Cch OUT 22 23 0 to -87dB,- CchVOL +6dB Cch 13 14 SWch OUT LFEch max:2Vrms 0 to -87dB,- LFEchVOL LFEMIX SW AGC SWMIX SW LPF fc =300Hz 24 SW ch output noise (values for reference) (DIN-Audio) Output gain 0dB : 8 Vrms +6dB: 15 Vrms +12dB: 30 Vrms 0, +6,+9,+12dB LOGIC 21 20 17 18 36 SW-IN 15 REF 35 19 16 Note: In the above application, the voltage input to pin 14 (LFE ch) must not exceed the absolute maximum input voltage (2 Vrms). TEST DATA CLOCK M61530FP Functional description (1) Equivalent circuit of the bass-boost circuit Input Output G0 Q=4 (G=10dB) 0dB F0 R1 VI N C1 C2 +K R2 K=1 VO Note: Resistor R2 is within the IC. (R2 214k 30%) fo = 1 2 R1R2C1C2 Hz Q= R1R2C1C2 R1(C1+C2)+(1-K)R2C2 Amplitude characteristics of the second-order high-pass filter (reference) Q 1 2 4 5 10 G0 0 to1dB 6dB 10dB 13dB 20dB Rev.1.0, Sep.19.2003, page 13 of 18 M61530FP Bass-boost characteristic curve R1 =680, R2 = 214k , C1 = C2 = 0.22 F (f0 60Hz ,Q 8.9) (2) AGC circuit MAX 2Vrms LFEch volume MAX 2Vrms SW ch output gain control +26 dB (total: 0 dB) to +38 dB (total: +12 dB) LFEch -26dB SWOUT AGCout SWch AGCin Precaution on inputting the same phase to LFE ch and SW ch Waveform detector circuit When C for setting the times = 1.0 F, attack time = 40 ms, and recovery time = 850 ms The input voltage range for AGC operation is from the input voltage at which AGC operation starts (taking the output gain into consideration, LFEin + SWin when the output voltage is 1.8 Vrms) to the same voltage x 10 dB. 1.0 C for setting the attack and recovery times AGC circuit Rev.1.0, Sep.19.2003, page 14 of 18 M61530FP Diagrams AGC input/output characteristics Output gain :0dB +5.1dBV +10 (1.8Vrms: TYP) Output gain :+6dB +5.1dBV +10 (1.8Vrms: TYP) AGCout:SWout(dBV) AGCout:SWout(dBV) 0 0 10dB + 9.1dBV (2.85Vrms) -10 +5.1dBV (1.8Vrms) -10 -0.9dBV (0.90Vrms) -20 -20 -10 0 +10 -20 -20 -10 0 +10 AGCin: LFEin+SWin(dBV) Output gain :+9dB +5.1dBV +10 (1.8Vrms:TYP) AGCin: LFEin+SWin(dBV) Output gain :+12dB AGCout:SWout(dBV) +5.1dBV +10 (1.8Vrms: TYP) AGCout:SWout(dBV) 0 10dB +6.1dBV (2.02Vrms) 0 10dB +3.1dBV (1.43Vrms) -10 -3.9dBV (0.64Vrms) -20 -20 -10 0 +10 -10 -6.9dBV (0.45Vrms) -20 -20 -10 0 +10 AGCin: LFEin+SWin(dBV) AGCin: LFEin+SWin(dBV) System reset (a) Power-on operation Immediately after power is supplied, this IC generates a reset signal. * * * * Generation of the reset signal is governed by the time constant for the rise in power voltage when power is supplied. When VCC rises above roughly 5.5 V (1), the reset signal is transmitted (logic circuit is turned on). (1) The reset operation takes place in the period from reset signal transmission to (2) reset signal cancellation. Trst = "Timing A + about 20 s" is the time up to reset cancellation (Timing A is time until VCC reaches 5.5 V) Rev.1.0, Sep.19.2003, page 15 of 18 M61530FP Reset timing diagram (1) Reset signal transmission V (2) Reset signal cancellation Reset operation VCC VDD (internal power supply) 5.5V VSS (internal power supply) t Trst About 20 s A Reset cancellation (normal operation) As is shown in the above figure, the reset is cancelled after time Trst after the power-supply voltage has started to rise. The chip is then able to receive serial data. (b) Power-off operation (for reference) * The internal VDD and VSS voltages fall as VCC falls (the opposite trend to that in the above figure). * When the logic circuits are turned off, all setting data becomes invalid. Rev.1.0, Sep.19.2003, page 16 of 18 M61530FP Application Examle FR_LPFOUT FL_LPFOUT FRch IN 10 470 47k 220p 10k 220p 1 FR_LPFIN FRch LPF amp FR input gain control 0,+5,+10dB FL input gain control 0,+5,+10dB FLch LPF amp 42 FL_LPFIN 220p 10 10k 220p 2.2k 1000p 2200p 470 47k 2.2k 47k 10 FLch IN 2 SL_EXTIN 41 R_LPFIN Rch IN SL_EXTIN from M61519FP Max:2Vrms 3 10 47k SL_VOLIN 40 SLVOL input SW 0 to -87dB,- SLch volume Rch LPF amp R_LPFOUT 4 10 SL_LPFOUT 39 L_LPFOUT 10 2200p 2.2k 1000p 2.2k 47k 10 SLch IN 10 2.2k 10k 1000p 4.7k 1000p 5 SL_LPFIN SLch LPF amp Lch LPF amp 38 L_LPFIN Lch OUT Lch IN 6 SR_EXTIN 37 +6dB VREF amp SRVOL input SW 0 to -87dB,- SRch volume REFIN SR_EXTIN from M61519FP Max:2Vrms 10 47k 7 8 36 REFOUT SR_VOLIN 100 35 FL_OUT 10 SR_LPFOUT VREF out 10k 1M 100 10 FLch OUT to M61519FP SRch IN 10 2.2k 10k 9 1000p 4.7k 1000p SR_LPFIN 34 SRch LPF amp FL output SW FR_IN 0.047 1M 10k 1M 10 10 C_VOLIN 33 +6dB Cch volume 0 to -87dB,- FR_OUT OFF FR output SW ON 11 10 C_LPFOUT 32 SL_BB1 FRch OUT Cch IN 10 2.2k 10k 12 1000p 4.7k 1000p C_LPFIN Cch LPF amp 31 Bass booster ON/OFF SL_BB2 0.22 13 LFE_VOLI N 30 +6dB LFEch volume SL_OUT 0.22 680 10 SLch OUT LFEch IN Max:2Vrms 10 14 SW_IN 0 to -87dB,- Bass booster 29 SR_BB1 0.22 SWch IN from M61519FP Max:2Vrms 10 47k 15 VCC 28 Bass booster ON/OFF SR_BB2 0.22 16 DATA 27 SR_OUT SWMIX SW LFEMIX SW 680 10 SRch OUT Cch OUT 17 Microcomputer CLOCK 26 Bass booster C_OUT Microcomputer I/F 18 GND 25 SW_OUT 10 19 TEST AGC SW output gain control 0,+6,+9,+12dB 24 SW_LPFIN 20 AGC 23 SW_LPFOUT 2.2k 0.1 1k 0.22 10 21 1 SWch LPF amp 22 SW ch OUT Note: The voltage input to pins 3, 7, 14, and 15 must not exceed the absolute maximum input voltage (2 Vrms). Rev.1.0, Sep.19.2003, page 17 of 18 to M61519FP 10 Rch OUT M61530FP 42P2R-E MMP JEDEC Code -- e b2 22 Plastic 42pin 450mil SSOP Weight(g) -- Lead Material Cu Alloy+42 Alloy EIAJ Package Code SSOP42-P-450-0.80 I2 Package Dimensions 42 HE E L1 L Rev.1.0, Sep.19.2003, page 18 of 18 e1 Recommended Mount Pad F Symbol 21 1 G D A A2 e y b A1 A A1 A2 b c D E e HE L L1 z Z1 y c z Z1 Detail G Detail F b2 e1 I2 Dimension in Millimeters Min Nom Max 2.4 -- -- -- 0.05 -- -- 2.0 -- 0.4 0.3 0.25 0.2 0.15 0.13 17.7 17.5 17.3 8.6 8.4 8.2 -- 0.8 -- 12.23 11.93 11.63 0.7 0.5 0.3 -- 1.765 -- -- -- 0.75 -- -- 0.9 0.15 -- -- -- 0 10 -- 0.5 -- -- 11.43 -- -- 1.27 -- Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. 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